-module(viva_tensor@backend@capability).
-compile([no_auto_import, nowarn_unused_vars, nowarn_unused_function, nowarn_nomatch, inline]).
-define(FILEPATH, "src/viva_tensor/backend/capability.gleam").
-export([hardware_profiles/2]).
-export_type([hardware_generation/0, hardware_feature/0, hardware_profile/0]).

-if(?OTP_RELEASE >= 27).
-define(MODULEDOC(Str), -moduledoc(Str)).
-define(DOC(Str), -doc(Str)).
-else.
-define(MODULEDOC(Str), -compile([])).
-define(DOC(Str), -compile([])).
-endif.

?MODULEDOC(false).

-type hardware_generation() :: generation_beam_cpu |
    generation_native_cpu |
    generation_ada |
    generation_blackwell |
    generation_rubin |
    generation_vera |
    generation_rubin_cpx.

-type hardware_feature() :: feature_cuda |
    feature_tensor_cores |
    feature_sparse_tensor_cores |
    feature_int8_imma |
    feature_nvfp4 |
    feature_block_scaled_mma |
    feature_unified_cpu_gpu_memory |
    feature_context_paging |
    feature_hadamard_preprocess |
    feature_experimental_int2.

-type hardware_profile() :: {hardware_profile,
        binary(),
        hardware_generation(),
        boolean(),
        integer(),
        integer(),
        integer(),
        integer(),
        integer(),
        list(hardware_feature()),
        binary()}.

-file("src/viva_tensor/backend/capability.gleam", 47).
?DOC(false).
-spec hardware_profiles(boolean(), list(viva_tensor@native@tflops:backend())) -> list(hardware_profile()).
hardware_profiles(Zig_loaded, Backends) ->
    Cuda_available = gleam@list:any(
        Backends,
        fun(Backend) ->
            (((Backend =:= cuda_f_p32) orelse (Backend =:= cuda_f_p16)) orelse (Backend
            =:= cuda_i_n_t8))
            orelse (Backend =:= cuda_sparse)
        end
    ),
    [{hardware_profile,
            <<"BEAM CPU"/utf8>>,
            generation_beam_cpu,
            true,
            0,
            0,
            0,
            0,
            1,
            [],
            <<"Portable pure Gleam fallback."/utf8>>},
        {hardware_profile,
            <<"Native CPU NIF"/utf8>>,
            generation_native_cpu,
            Zig_loaded,
            0,
            0,
            0,
            0,
            1,
            [feature_hadamard_preprocess],
            <<"Loaded NIF path for CPU SIMD, MKL, and future native preprocessing."/utf8>>},
        {hardware_profile,
            <<"RTX 4090 / Ada"/utf8>>,
            generation_ada,
            Cuda_available,
            24000000000,
            1008,
            0,
            0,
            16,
            [feature_cuda, feature_tensor_cores, feature_int8_imma],
            <<"Current local CUDA development target."/utf8>>},
        {hardware_profile,
            <<"Blackwell B200"/utf8>>,
            generation_blackwell,
            false,
            192000000000,
            8000,
            10,
            0,
            16,
            [feature_cuda,
                feature_tensor_cores,
                feature_sparse_tensor_cores,
                feature_nvfp4,
                feature_block_scaled_mma],
            <<"Known target profile; no Blackwell-specific runtime detection is wired yet."/utf8>>},
        {hardware_profile,
            <<"Rubin R100"/utf8>>,
            generation_rubin,
            false,
            288000000000,
            22000,
            50,
            0,
            16,
            [feature_cuda,
                feature_tensor_cores,
                feature_sparse_tensor_cores,
                feature_nvfp4,
                feature_block_scaled_mma,
                feature_hadamard_preprocess,
                feature_experimental_int2],
            <<"Future target profile; kept unavailable until the runtime can detect Rubin hardware/toolchains."/utf8>>},
        {hardware_profile,
            <<"Vera CPU"/utf8>>,
            generation_vera,
            false,
            1500000000000,
            1200,
            0,
            1800,
            16,
            [feature_unified_cpu_gpu_memory],
            <<"Future coherent CPU memory target for Vera Rubin systems."/utf8>>},
        {hardware_profile,
            <<"Rubin CPX"/utf8>>,
            generation_rubin_cpx,
            false,
            0,
            0,
            0,
            0,
            16,
            [feature_context_paging, feature_cuda],
            <<"Future long-context inference target; no stable dispatch path yet."/utf8>>}].