diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-abbbi.dts b/arch/arm/boot/dts/am335x-abbbi.dts --- a/arch/arm/boot/dts/am335x-abbbi.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-abbbi.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright 2015 Konsulko Group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" + +/ { + model = "Arrow BeagleBone Black Industrial"; + compatible = "arrow,am335x-abbbi", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + adi_hdmi_bbbi_pins: adi_hdmi_bbbi_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + adi_hdmi_bbbi_off_pins: adi_hdmi_bbbi_off_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + 0x1ac (PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ + 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ + 0x194 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + 0x190 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + 0x06c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; + + mcasp0_pins_sleep: mcasp0_pins_sleep { + pinctrl-single,pins = < + 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.mcasp0_ahclkx */ + 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkr.mcasp0_axr2 */ + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsx.mcasp0_fsx */ + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_aclkx.mcasp0_aclkx */ + 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; +}; + +&lcdc { + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + adv7511w { + compatible = "adi,adv7511w"; + reg = <0x39>; + pinctrl-names = "default", "off"; + pinctrl-0 = <&adi_hdmi_bbbi_pins>; + pinctrl-1 = <&adi_hdmi_bbbi_off_pins>; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; +}; + +&mcasp0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp0_pins>; + pinctrl-1 = <&mcasp0_pins_sleep>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + hdmi_audio: hdmi_audio@0 { + compatible = "linux,hdmi-audio"; + status = "okay"; + }; + + sound { + compatible = "ti,beaglebone-black-audio"; + ti,model = "TI BeagleBone Black"; + ti,audio-codec = <&hdmi_audio>; + ti,mcasp-controller = <&mcasp0>; + ti,audio-routing = + "HDMI Out", "TX"; + clocks = <&clk_mcasp0>; + clock-names = "mclk"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-arduino-tre.dts b/arch/arm/boot/dts/am335x-arduino-tre.dts --- a/arch/arm/boot/dts/am335x-arduino-tre.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-arduino-tre.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,582 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" + +/ { + model = "TI AM335x Arduino Tre"; + compatible = "ti,am335x-arduino-tre", "ti,am335x-boneblack", "ti,am335x-bone", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 512 MB */ + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&userled_pins>; + + compatible = "gpio-leds"; + + led@0 { + label = "arduino_tre:yel:usr0"; + gpios = <&gpio1 21 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@1 { + label = "arduino_tre:red:usr1"; + gpios = <&gpio1 22 0>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@2 { + label = "arduino_tre:blu:usr2"; + gpios = <&gpio1 23 0>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@3 { + label = "arduino_tre:grn:usr3"; + gpios = <&gpio1 24 0>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; + + hdmi { + compatible = "ti,tilcdc,slave"; + i2c = <&i2c0>; + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + status = "okay"; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "DA830 EVM"; + ti,audio-codec = <&tlv320aic3x>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE2L", "Line In", + "LINE2R", "Line In"; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&userled_pins>; + + userled_pins: pinmux_userled_pins { + pinctrl-single,pins = < + 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */ + 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */ + 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */ + 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */ + >; + }; + + can_bus_pins: pinmux_can_bus_pins { + pinctrl-single,pins = < + 0x120 0x31 /* DCAN0_RX MODE1 */ + 0x11c 0x01 /* DCAN0_TX MODE1 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + emac_rmii1_pins: pinmux_emac_rmii1_pins { + pinctrl-single,pins = < + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */ + 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 0x70 /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + 0x18c 0x70 /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x158 0x72 /*spi0_d1-i2c1_sda,SLEWCTRL_SLOW | INPUT_PULLUP | MODE2*/ + 0x15c 0x72 /*spi0_cs0-i2c1_scl,SLEWCTRL_SLOW | INPUT_PULLUP |MODE2*/ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + 0x150 0x72 /*spi0_scl.i2c2_sda,SLEWCTRL_SLOW | INPUT_PULLUP |MODE2*/ + 0x154 0x72 /*spi0_d0.i2c2_scl,SLEWCTRL_SLOW | INPUT_PULLUP | MODE2*/ + >; + }; + + mmc1_pins_default: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + pinctrl-single,pins = < + 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + tre_ehrpwm1_pins: pinmux_tre_ehrpwm1_pins { + pinctrl-single,pins = < + 0x48 0x06 /* PWM1A ~102 MODE6 */ + 0x4c 0x06 /* PWM1B ~103 MODE6 */ + >; + }; + + tre_ehrpwm2_pins: pinmux_tre_ehrpwm2_pins { + pinctrl-single,pins = < + 0x20 0x04 /* PWM2A ~100 MODE4 */ + 0x24 0x04 /* PWM2B ~101 MODE4 */ + >; + }; + + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + >; + }; + + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + >; + }; + + tre_audio_pins: pinmux_tre_audio_pins { + pinctrl-single,pins = < + 0x1ac 0x00 /*mcasp0_ahclkx (AUD_MCLK)->12MHz, INPUT | MODE0*/ + 0x190 0x20 /* mcasp0_aclkx (AUD_BCLK)->, INPUT | MODE0*/ + 0x194 0x20 /* mcasp0_fsx (AUD_FSX)-> , INPUT | MODE0*/ + 0x198 0x20 /* mcasp0_axr0 (AUD_DIN)<-, INPUT | MODE0*/ + 0x19c 0x22 /* mcasp0_ahclkr-_axr2 (AUD_DOUT)->, | MODE2*/ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + 0x168 0x14 /* MOSI1 OUTPUT_PULLUP | MODE0 */ + 0x16c 0x34 /* MISO1 INPUT_PULLUP | MODE0 */ + 0x108 0x12 /* SCK1 OUTPUT_PULLUP | MODE0 */ + 0x164 0x12 /* SS1 OUTPUT_PULLUP | MODE0 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x180 0x30 /* UART1_rxd PULL_UP | MODE0 */ + 0x184 0x00 /* UART1_txd MODE0 */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x12c 0x31 /* UART2_rxd PULL_UP | MODE1 */ + 0x130 0x01 /* UART2_txd MODE1 */ + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x70 0x36 /* UART4_rxd PULL_UP | MODE6 */ + 0x74 0x06 /* UART4_txd MODE6 */ + >; + }; +}; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can_bus_pins>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + tps: tps@24 { + reg = <0x24>; + }; + + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + }; + + tlv320aic3x: tlv320aic3x@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <100000>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <100000>; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&tre_ehrpwm1_pins>; +}; + +&epwmss2 { + status = "okay"; +}; + +&ehrpwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&tre_ehrpwm2_pins>; +}; + +&lcdc { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; + + control@44e10620 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@47402000 { + status = "okay"; + }; +}; + +&tps { + compatible = "ti,tps65217"; + ti,pmic-shutdown-controller; + + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-always-on; + }; + + rtc@44e3e000 { + ti,system-power-controller; + }; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&tre_audio_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + num-serializer = <16>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 0 1 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&mac { + slaves = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emac_rmii1_pins>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-inverted; + vmmc-supply = <&vmmcsd_fixed>; +}; + +&rtc { + system-power-controller; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts 2016-05-11 13:31:53.189225170 -0400 @@ -240,7 +240,12 @@ status = "okay"; nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; ti,nand-xfer-type = "polled"; @@ -261,12 +266,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-argus.dtsi b/arch/arm/boot/dts/am335x-bone-argus.dtsi --- a/arch/arm/boot/dts/am335x-bone-argus.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-argus.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + ocp { + P8_07_pinmux { + /* gpio2[2] */ + status = "disabled"; + }; + P8_08_pinmux { + /* gpio2[3] */ + status = "disabled"; + }; + P8_09_pinmux { + /* gpio2[5] */ + status = "disabled"; + }; + P8_10_pinmux { + /* gpio2[4] */ + status = "disabled"; + }; + P9_11_pinmux { + /* gpio0[30] */ + status = "disabled"; + }; + P9_17_pinmux { + /* gpio0[5] */ + status = "disabled"; + }; + P9_18_pinmux { + /* gpio0[4] */ + status = "disabled"; + }; + P9_41_pinmux { + /* gpio0[20] */ + status = "disabled"; + }; + P9_42_pinmux { + /* gpio0[7] */ + status = "disabled"; + }; + }; +}; + +/ { + argus-ups { + compatible = "argus-ups"; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&argus_ups_pins>; /* Refer to previous label */ + /* This section communicates the gpio numbers to the driver module */ + /* Note that gpio controllers appear to be numbered from 1-n here rather than 0-(n-1)????? */ + gpios = <&gpio0 30 0>, /* Request */ + <&gpio0 5 0>, /* Acknowledge */ + <&gpio0 4 0>, /* Watchdog */ + <&gpio2 2 0>, /* LED 1 Green */ + <&gpio2 3 0>, /* LED 1 Red */ + <&gpio2 5 0>, /* LED 2 Green */ + <&gpio2 4 0>, /* LED 2 Red */ + <&gpio0 20 0>, /* General Output #1 */ + <&gpio0 7 0>; /* General Output #2 */ + debug = <1>; + shutdown = <1>; + }; +}; + +&am33xx_pinmux { + argus_ups_pins: pinmux_argus_ups_pins { /* Set up pinmux */ + pinctrl-single,pins = < + 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */ + 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* spi0_cs0.gpio0_5 */ + 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* spi0_d1.gpio0_4 */ + 0x090 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_advn_ale.gpio_2 */ + 0x094 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */ + 0x09c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */ + 0x098 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_gpmc_wen.gpio2_4 */ + 0x1b4 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0_20 */ + 0x164 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + BONE_P9_20 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_ctsn.i2c2_sda */ + BONE_P9_19 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_rtsn.i2c2_scl */ + >; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; + + rtc@68 { + compatible = "maxim,ds1307"; + reg = <0x68>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-audio.dts b/arch/arm/boot/dts/am335x-boneblack-audio.dts --- a/arch/arm/boot/dts/am335x-boneblack-audio.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-audio.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; + + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-bbb-exp-c.dts b/arch/arm/boot/dts/am335x-boneblack-bbb-exp-c.dts --- a/arch/arm/boot/dts/am335x-boneblack-bbb-exp-c.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-bbb-exp-c.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common-no-capemgr.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +#include "am335x-cape-bbb-exp-c.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-bbb-exp-r.dts b/arch/arm/boot/dts/am335x-boneblack-bbb-exp-r.dts --- a/arch/arm/boot/dts/am335x-boneblack-bbb-exp-r.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-bbb-exp-r.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common-no-capemgr.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +#include "am335x-cape-bbb-exp-r.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-bbbmini.dts b/arch/arm/boot/dts/am335x-boneblack-bbbmini.dts --- a/arch/arm/boot/dts/am335x-boneblack-bbbmini.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-bbbmini.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Modified by Mirko Denecke + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" + +#include +#include + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + /* P9_26: uart1_rxd.d_can1_tx */ + BONE_P9_26 (PIN_OUTPUT_PULLUP | MUX_MODE2) + /* P9_24: uart1_txd.d_can1_rx */ + BONE_P9_24 (PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; + + pru_pins: pinmux_pru_pins { + pinctrl-single,pins = < + 0x03c 0x35 /* ecap0_in_pwm0_out.pr1_ecap0_ecap_capin, MODE5 | INPUT_PULLUP | PRU, PPM-sum, SBUS, DSM */ + + 0x0e8 0x25 /* lcd_pclk.pr1_pru1_pru_r30_10, MODE5 | OUTPUT | PRU, CH_1 */ + 0x0e0 0x25 /* lcd_vsync.pr1_pru1_pru_r30_8, MODE5 | OUTPUT | PRU, CH_2 */ + 0x0ec 0x25 /* lcd_ac_bias_en.pr1_pru1_pru_r30_11, MODE5 | OUTPUT | PRU, CH_3 */ + 0x0e4 0x25 /* lcd_hsync.pr1_pru1_pru_r30_9, MODE5 | OUTPUT | PRU, CH_4 */ + 0x0bc 0x25 /* lcd_data7.pr1_pru1_pru_r30_7, MODE5 | OUTPUT | PRU, CH_5 */ + 0x0b8 0x25 /* lcd_data6.pr1_pru1_pru_r30_6, MODE5 | OUTPUT | PRU, CH_6 */ + 0x0b4 0x25 /* lcd_data5.pr1_pru1_pru_r30_5, MODE5 | OUTPUT | PRU, CH_7 */ + 0x0b0 0x25 /* lcd_data4.pr1_pru1_pru_r30_4, MODE5 | OUTPUT | PRU, CH_8 */ + 0x0ac 0x25 /* lcd_data3.pr1_pru1_pru_r30_3, MODE5 | OUTPUT | PRU, CH_9 */ + 0x0a8 0x25 /* lcd_data2.pr1_pru1_pru_r30_2, MODE5 | OUTPUT | PRU, CH_10 */ + 0x0a4 0x25 /* lcd_data1.pr1_pru1_pru_r30_1, MODE5 | OUTPUT | PRU, CH_11 */ + 0x0a0 0x25 /* lcd_data0.pr1_pru1_pru_r30_0, MODE5 | OUTPUT | PRU, CH_12 */ + + BONE_P8_12 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* HC-SR04 TRIG */ + BONE_P8_16 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* HC-SR04 ECHO */ + + BONE_P9_25 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* MPU9250 INT */ + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + /* P9_22: spi0_sclk.spi0_sclk */ + BONE_P9_22 (PIN_INPUT_PULLUP | MUX_MODE0) + /* P9_21: spi0_d0.spi0_d0 */ + BONE_P9_21 (PIN_INPUT_PULLUP | MUX_MODE0) + /* P9_18: spi0_d1.spi0_d1 */ + BONE_P9_18 (PIN_OUTPUT_PULLUP | MUX_MODE0) + /* P9_17: spi0_cs0.spi0_cs0 */ + BONE_P9_17 (PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + /* P9_31: mcasp0_aclkx.spi1_sclk */ + BONE_P9_31 (PIN_INPUT_PULLUP | MUX_MODE3) + + /* P9_29: mcasp0_fsx.spi1_d0 */ + BONE_P9_29 (PIN_INPUT_PULLUP | MUX_MODE3) + + /* P9_30: mcasp0_axr0.spi1_d1 */ + BONE_P9_30 (PIN_OUTPUT_PULLUP | MUX_MODE3) + + /* P9_28: mcasp0_ahclkr.spi1_cs0 */ + BONE_P9_28 (PIN_OUTPUT_PULLUP | MUX_MODE3) + + /* P9_19: uart1_rtsn.spi1_cs1 */ +/* BONE_P9_19 (PIN_OUTPUT_PULLUP | MUX_MODE4)*/ + + /* P9_42: ecap0_in_pwm0_out.spi1_cs1 */ + BONE_P9_42A (PIN_OUTPUT_PULLUP | MUX_MODE2) + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + /* P9_11: gpmc_wait0.uart4_rxd_mux2 */ + BONE_P9_11 (PIN_INPUT_PULLUP | MUX_MODE6) + /* P9_13: gpmc_wpn.uart4_txd_mux2 */ + BONE_P9_13 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) + >; + }; + + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + /* P8_38: lcd_data9.uart5_rxd */ + BONE_P8_38 (PIN_INPUT_PULLUP | MUX_MODE4) + /* P8_37: lcd_data8.uart5_txd */ + BONE_P8_37 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) + >; + }; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi0_0 { + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <24000000>; + reg = <0>; + compatible = "spidev"; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi1_0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + spi-max-frequency = <24000000>; + compatible = "spidev"; + }; + + spi1_1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + spi-max-frequency = <24000000>; + compatible = "spidev"; + }; +}; + +&tscadc { + adc { + ti,adc-channels = <0 1>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-cape-bone-argus.dts b/arch/arm/boot/dts/am335x-boneblack-cape-bone-argus.dts --- a/arch/arm/boot/dts/am335x-boneblack-cape-bone-argus.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-cape-bone-argus.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common-no-capemgr.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; +}; + +&lcdc { + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + port { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; +}; + +#include "am335x-bone-argus.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts --- a/arch/arm/boot/dts/am335x-boneblack.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-boneblack.dts 2016-05-11 13:31:53.189225170 -0400 @@ -8,7 +8,11 @@ /dts-v1/; #include "am33xx.dtsi" +#include "am33xx-es2.dtsi" #include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" +#include +/* #include "am335x-bone-jtag.dtsi" */ / { model = "TI AM335x BeagleBone Black"; @@ -33,35 +37,49 @@ status = "okay"; }; +&sgx { + status = "okay"; +}; + &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ - 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ - 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ - 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ >; }; nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { pinctrl-single,pins = < - 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ >; }; }; @@ -76,21 +94,69 @@ }; &i2c0 { - tda19988 { + tda19988: tda19988 { compatible = "nxp,tda998x"; reg = <0x70>; + pinctrl-names = "default", "off"; pinctrl-0 = <&nxp_hdmi_bonelt_pins>; pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; - port { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcdc_0>; + #sound-dai-cells = <0>; + audio-ports = < AFMT_I2S 0x03>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; }; }; }; }; -&rtc { - system-power-controller; +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-emmc-overlay.dts b/arch/arm/boot/dts/am335x-boneblack-emmc-overlay.dts --- a/arch/arm/boot/dts/am335x-boneblack-emmc-overlay.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-emmc-overlay.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-hdmi-overlay.dts b/arch/arm/boot/dts/am335x-boneblack-hdmi-overlay.dts --- a/arch/arm/boot/dts/am335x-boneblack-hdmi-overlay.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-hdmi-overlay.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +/* EMMC in reset */ +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + mcasp0_pins: mcasp0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.GPIO1_27 */ + >; + }; +}; + +&lcdc { + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + #sound-dai-cells = <0>; + audio-ports = < AFMT_I2S 0x03>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +/ { + clk_mcasp0_fixed: clk_mcasp0_fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk_mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Black"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + + dailink0_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&tda19988>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-nhdmi-overlay.dts b/arch/arm/boot/dts/am335x-boneblack-nhdmi-overlay.dts --- a/arch/arm/boot/dts/am335x-boneblack-nhdmi-overlay.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-nhdmi-overlay.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" +#include + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +/* EMMC in reset */ +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; +}; + +&lcdc { + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&i2c0 { + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-overlay.dts b/arch/arm/boot/dts/am335x-boneblack-overlay.dts --- a/arch/arm/boot/dts/am335x-boneblack-overlay.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-overlay.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&sgx { + status = "okay"; +}; + +/* EMMC in reset */ +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts --- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-wl1835.dtsi" + +/ { + model = "TI AM335x BeagleBone Black Wireless"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&mmc3 { + status = "okay"; +}; + +&mac { + status = "disabled"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-wl1835.dtsi b/arch/arm/boot/dts/am335x-boneblack-wl1835.dtsi --- a/arch/arm/boot/dts/am335x-boneblack-wl1835.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-wl1835.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,136 @@ + +#include + +/ { + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* WL_EN */ +// gpio = <&gpio3 9 0>; +// enable-active-high; + }; + + tibt { + compatible = "tibt"; + nshutdown_gpio = <28>; + dev_name = "/dev/ttyS3"; + flow_cntrl = <1>; + baud_rate = <3000000>; + }; + + btwilink { + compatible = "btwilink"; + }; +}; + +&am33xx_pinmux { + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + 0x128 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (K17) gmii1_txd0.gpio0[28] - BT_EN */ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + 0x13c ( PIN_INPUT_PULLUP | MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */ + 0x114 ( PIN_INPUT_PULLUP | MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */ + 0x118 ( PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ + 0x11c ( PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */ + 0x120 ( PIN_INPUT_PULLUP | MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */ + 0x108 ( PIN_INPUT_PULLUP | MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + pinctrl-single,pins = < + 0x13c ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (L15) gmii1_rxd1.mmc2_clk */ + 0x114 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J16) gmii1_txen.mmc2_cmd */ + 0x118 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J17) gmii1_rxdv.mmc2_dat0 */ + 0x11c ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (J18) gmii1_txd3.mmc2_dat1 */ + 0x120 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (K15) gmii1_txd2.mmc2_dat2 */ + 0x108 ( PIN_INPUT_PULLDOWN | MUX_MODE7 ) /* (H16) gmii1_col.mmc2_dat3 */ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x12c ( PIN_OUTPUT_PULLDOWN | MUX_MODE7 ) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + 0x144 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */ + 0x130 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (L18) gmii1_rxclk.gpio3[10] - Cape_Buffer_EN */ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x12c ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (K18) gmii1_txclk.gpio3[9] - WL_EN */ + 0x144 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (H18) rmii1_refclk.gpio0[29] - WL_IRQ */ + 0x130 ( PIN_OUTPUT_PULLUP | MUX_MODE7 ) /* (L18) gmii1_rxclk.gpio3[10] - Cape_Buffer_EN */ + >; + }; + + uart3_pins_default: pinmux_uart3_pins_default { + pinctrl-single,pins = < + 0x134 ( PIN_INPUT_PULLUP | MUX_MODE1 ) /* (L17) gmii1_rxd3.uart3_rxd */ + 0x138 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (L16) gmii1_rxd2.uart3_txd */ + 0x148 ( PIN_INPUT | MUX_MODE3 ) /* (M17) mdio_data.uart3_ctsn */ + 0x14c ( PIN_OUTPUT_PULLDOWN | MUX_MODE3 ) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + uart3_pins_sleep: pinmux_uart3_pins_sleep { + pinctrl-single,pins = < + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L17) gmii1_rxd3.uart3_rxd */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L16) gmii1_rxd2.uart3_txd */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M17) mdio_data.uart3_ctsn */ + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M18) mdio_clk.uart3_rtsn */ + + >; + }; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; +// vmmc-supply = <&wlan_en_reg>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins &wlan_pins>; + pinctrl-1 = <&mmc3_pins_sleep &wlan_pins_sleep>; + ti,non-removable; + ti,needs-special-hs-handling; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&gpio0 { + wl_en { + gpio-hog; + gpios = <26 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "WL_EN"; + }; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart3_pins_default>; + pinctrl-1 = <&uart3_pins_sleep>; + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-wl1835mod-cape.dtsi b/arch/arm/boot/dts/am335x-boneblack-wl1835mod-cape.dtsi --- a/arch/arm/boot/dts/am335x-boneblack-wl1835mod-cape.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-wl1835mod-cape.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include + +/ { + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* WL_EN */ + gpio = <&gpio0 26 0>; + enable-active-high; + }; + + kim { + compatible = "kim"; + nshutdown_gpio = <44>; /* Bank1, pin12 */ + dev_name = "/dev/ttyO4"; + flow_cntrl = <1>; + baud_rate = <3000000>; + }; + + btwilink { + compatible = "btwilink"; + }; +}; + +&am33xx_pinmux { + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + 0x30 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1_12 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + mmc2_pins_sleep: pinmux_mmc2_pins_sleep { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.mmc1_dat3 */ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN*/ + 0x2C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ*/ + 0x7C (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpio1_29 BF_EN*/ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x28 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN*/ + 0x2C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ*/ + 0x7C (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpio1_29 BF_EN*/ + >; + }; + + uart4_pins_default: pinmux_uart4_pins_default { + pinctrl-single,pins = < + 0xD0 (PIN_INPUT | MUX_MODE6) /* lcd_data12.uart4_cts */ + 0xD4 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data13.uart4_rts */ + 0x70 (PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */ + 0x74 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */ + >; + }; + + uart4_pins_sleep: pinmux_uart4_pins_sleep { + pinctrl-single,pins = < + 0xD0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_data12.uart4_cts */ + 0xD4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_data13.uart4_rts */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.uart4_rxd */ + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wpn.uart4_txd */ + >; + }; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc2_pins &wlan_pins>; + pinctrl-1 = <&mmc2_pins_sleep &wlan_pins_sleep>; + ti,non-removable; + ti,needs-special-hs-handling; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart4_pins_default>; + pinctrl-1 = <&uart4_pins_sleep>; + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-boneblack-wl1835mod.dts b/arch/arm/boot/dts/am335x-boneblack-wl1835mod.dts --- a/arch/arm/boot/dts/am335x-boneblack-wl1835mod.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-boneblack-wl1835mod.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common-no-capemgr.dtsi" + +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&sgx { + status = "okay"; +}; + +/* EMMC in reset */ +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; + +#include "am335x-boneblack-wl1835mod-cape.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-cape-bone-argus.dts b/arch/arm/boot/dts/am335x-bone-cape-bone-argus.dts --- a/arch/arm/boot/dts/am335x-bone-cape-bone-argus.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-cape-bone-argus.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common-no-capemgr.dtsi" + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&ldo3_reg>; +}; + +#include "am335x-bone-argus.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi --- a/arch/arm/boot/dts/am335x-bone-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -25,14 +25,14 @@ compatible = "gpio-leds"; led@2 { - label = "beaglebone:green:heartbeat"; + label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; led@3 { - label = "beaglebone:green:mmc0"; + label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; @@ -62,117 +62,112 @@ }; &am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&clkout2_pin>; - user_leds_s0: user_leds_s0 { pinctrl-single,pins = < - 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ - 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ - 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ - 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ - 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - clkout2_pin: pinmux_clkout2_pin { - pinctrl-single,pins = < - 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ - 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ - 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ - 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ - 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ - 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ - 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ - 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ - 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ - 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ - 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ - 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ - 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + 0x108 (PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ + 0x10c (PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ >; }; cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < /* Slave 1 reset value */ - 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < /* MDIO */ - 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ >; }; davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < /* MDIO reset value */ - 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) - 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ >; }; emmc_pins: pinmux_emmc_pins { pinctrl-single,pins = < - 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ - 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ - 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ - 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ - 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ - 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ - 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ - 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ - 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ - 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ >; }; }; @@ -308,6 +303,9 @@ */ ti,pmic-shutdown-controller; + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + regulators { dcdc1_reg: regulator@0 { regulator-name = "vdds_dpr"; @@ -359,15 +357,11 @@ phy-mode = "mii"; }; -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "mii"; -}; - &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; + slaves = <1>; status = "okay"; }; @@ -393,3 +387,36 @@ &sham { status = "okay"; }; + +&wkup_m3_ipc { + ti,scale-data-fw = "am335x-bone-scale-data.bin"; +}; + +&rtc { + system-power-controller; +}; + +/* the cape manager */ +/ { + bone_capemgr { + compatible = "ti,bone-capemgr"; + status = "okay"; + + nvmem-cells = <&baseboard_data &cape0_data &cape1_data &cape2_data &cape3_data>; + nvmem-cell-names = "baseboard", "slot0", "slot1", "slot2", "slot3"; + #slots = <4>; + + /* map board revisions to compatible definitions */ + baseboardmaps { + baseboard_beaglebone: board@0 { + board-name = "A335BONE"; + compatible-name = "ti,beaglebone"; + }; + + baseboard_beaglebone_black: board@1 { + board-name = "A335BNLT"; + compatible-name = "ti,beaglebone-black"; + }; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-common-no-capemgr.dtsi b/arch/arm/boot/dts/am335x-bone-common-no-capemgr.dtsi --- a/arch/arm/boot/dts/am335x-bone-common-no-capemgr.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-common-no-capemgr.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,348 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@2 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@3 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@4 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@5 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */ + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x108 (PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */ + 0x10c (PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */ + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; + + baseboard_eeprom: baseboard_eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + + #address-cells = <1>; + #size-cells = <1>; + baseboard_data: baseboard_data@0 { + reg = <0 0x100>; + }; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + /* + * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only + * mode") at poweroff. Most BeagleBone versions do not support RTC-only + * mode and risk hardware damage if this mode is entered. + * + * For details, see linux-omap mailing list May 2015 thread + * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller + * In particular, messages: + * http://www.spinics.net/lists/linux-omap/msg118585.html + * http://www.spinics.net/lists/linux-omap/msg118615.html + * + * You can override this later with + * &tps { /delete-property/ ti,pmic-shutdown-controller; } + * if you want to use RTC-only mode and made sure you are not affected + * by the hardware problems. (Tip: double-check by performing a current + * measurement after shutdown: it should be less than 1 mA.) + */ + ti,pmic-shutdown-controller; + + interrupt-parent = <&intc>; + interrupts = <7>; /* NNMI */ + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1325000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + slaves = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +&wkup_m3_ipc { + ti,scale-data-fw = "am335x-bone-scale-data.bin"; +}; + +&rtc { + system-power-controller; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-common-universal.dtsi b/arch/arm/boot/dts/am335x-bone-common-universal.dtsi --- a/arch/arm/boot/dts/am335x-bone-common-universal.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-common-universal.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,2052 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&am33xx_pinmux { + /************************/ + /* P8 Header */ + /************************/ + + /* P8_01 GND */ + /* P8_02 GND */ + /* P8_03 (ZCZ ball R9 ) emmc */ + /* P8_04 (ZCZ ball T9 ) emmc */ + /* P8_05 (ZCZ ball R8 ) emmc */ + /* P8_06 (ZCZ ball T8 ) emmc */ + + /* P8_07 (ZCZ ball R7 ) */ + P8_07_default_pin: pinmux_P8_07_default_pin { + pinctrl-single,pins = <0x090 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_07_gpio_pin: pinmux_P8_07_gpio_pin { + pinctrl-single,pins = <0x090 0x2F>; }; /* Mode 7, RxActive */ + P8_07_gpio_pu_pin: pinmux_P8_07_gpio_pu_pin { + pinctrl-single,pins = <0x090 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_07_gpio_pd_pin: pinmux_P8_07_gpio_pd_pin { + pinctrl-single,pins = <0x090 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_07_timer_pin: pinmux_P8_07_timer_pin { + pinctrl-single,pins = <0x090 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + + /* P8_08 (ZCZ ball T7 ) */ + P8_08_default_pin: pinmux_P8_08_default_pin { + pinctrl-single,pins = <0x094 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_08_gpio_pin: pinmux_P8_08_gpio_pin { + pinctrl-single,pins = <0x094 0x2F>; }; /* Mode 7, RxActive */ + P8_08_gpio_pu_pin: pinmux_P8_08_gpio_pu_pin { + pinctrl-single,pins = <0x094 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_08_gpio_pd_pin: pinmux_P8_08_gpio_pd_pin { + pinctrl-single,pins = <0x094 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_08_timer_pin: pinmux_P8_08_timer_pin { + pinctrl-single,pins = <0x094 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + + /* P8_09 (ZCZ ball T6 ) */ + P8_09_default_pin: pinmux_P8_09_default_pin { + pinctrl-single,pins = <0x09c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_09_gpio_pin: pinmux_P8_09_gpio_pin { + pinctrl-single,pins = <0x09c 0x2F>; }; /* Mode 7, RxActive */ + P8_09_gpio_pu_pin: pinmux_P8_09_gpio_pu_pin { + pinctrl-single,pins = <0x09c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_09_gpio_pd_pin: pinmux_P8_09_gpio_pd_pin { + pinctrl-single,pins = <0x09c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_09_timer_pin: pinmux_P8_09_timer_pin { + pinctrl-single,pins = <0x09c 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + + /* P8_10 (ZCZ ball U6 ) */ + P8_10_default_pin: pinmux_P8_10_default_pin { + pinctrl-single,pins = <0x098 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_10_gpio_pin: pinmux_P8_10_gpio_pin { + pinctrl-single,pins = <0x098 0x2F>; }; /* Mode 7, RxActive */ + P8_10_gpio_pu_pin: pinmux_P8_10_gpio_pu_pin { + pinctrl-single,pins = <0x098 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_10_gpio_pd_pin: pinmux_P8_10_gpio_pd_pin { + pinctrl-single,pins = <0x098 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_10_timer_pin: pinmux_P8_10_timer_pin { + pinctrl-single,pins = <0x098 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + + /* P8_11 (ZCZ ball R12) */ + P8_11_default_pin: pinmux_P8_11_default_pin { + pinctrl-single,pins = <0x034 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_11_gpio_pin: pinmux_P8_11_gpio_pin { + pinctrl-single,pins = <0x034 0x2F>; }; /* Mode 7, RxActive */ + P8_11_gpio_pu_pin: pinmux_P8_11_gpio_pu_pin { + pinctrl-single,pins = <0x034 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_11_gpio_pd_pin: pinmux_P8_11_gpio_pd_pin { + pinctrl-single,pins = <0x034 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_11_pruout_pin: pinmux_P8_11_pruout_pin { + pinctrl-single,pins = <0x034 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_11_qep_pin: pinmux_P8_11_qep_pin { + pinctrl-single,pins = <0x034 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_12 (ZCZ ball T12) */ + P8_12_default_pin: pinmux_P8_12_default_pin { + pinctrl-single,pins = <0x030 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_12_gpio_pin: pinmux_P8_12_gpio_pin { + pinctrl-single,pins = <0x030 0x2F>; }; /* Mode 7, RxActive */ + P8_12_gpio_pu_pin: pinmux_P8_12_gpio_pu_pin { + pinctrl-single,pins = <0x030 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_12_gpio_pd_pin: pinmux_P8_12_gpio_pd_pin { + pinctrl-single,pins = <0x030 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_12_pruout_pin: pinmux_P8_12_pruout_pin { + pinctrl-single,pins = <0x030 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_12_qep_pin: pinmux_P8_12_qep_pin { + pinctrl-single,pins = <0x030 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_13 (ZCZ ball T10) */ + P8_13_default_pin: pinmux_P8_13_default_pin { + pinctrl-single,pins = <0x024 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_13_gpio_pin: pinmux_P8_13_gpio_pin { + pinctrl-single,pins = <0x024 0x2F>; }; /* Mode 7, RxActive */ + P8_13_gpio_pu_pin: pinmux_P8_13_gpio_pu_pin { + pinctrl-single,pins = <0x024 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_13_gpio_pd_pin: pinmux_P8_13_gpio_pd_pin { + pinctrl-single,pins = <0x024 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_13_pwm_pin: pinmux_P8_13_pwm_pin { + pinctrl-single,pins = <0x024 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_14 (ZCZ ball T11) */ + P8_14_default_pin: pinmux_P8_14_default_pin { + pinctrl-single,pins = <0x028 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_14_gpio_pin: pinmux_P8_14_gpio_pin { + pinctrl-single,pins = <0x028 0x2F>; }; /* Mode 7, RxActive */ + P8_14_gpio_pu_pin: pinmux_P8_14_gpio_pu_pin { + pinctrl-single,pins = <0x028 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_14_gpio_pd_pin: pinmux_P8_14_gpio_pd_pin { + pinctrl-single,pins = <0x028 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_14_pwm_pin: pinmux_P8_14_pwm_pin { + pinctrl-single,pins = <0x028 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_15 (ZCZ ball U13) */ + P8_15_default_pin: pinmux_P8_15_default_pin { + pinctrl-single,pins = <0x03c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_15_gpio_pin: pinmux_P8_15_gpio_pin { + pinctrl-single,pins = <0x03c 0x2F>; }; /* Mode 7, RxActive */ + P8_15_gpio_pu_pin: pinmux_P8_15_gpio_pu_pin { + pinctrl-single,pins = <0x03c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_15_gpio_pd_pin: pinmux_P8_15_gpio_pd_pin { + pinctrl-single,pins = <0x03c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_15_pruin_pin: pinmux_P8_15_pruin_pin { + pinctrl-single,pins = <0x03c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_15_qep_pin: pinmux_P8_15_qep_pin { + pinctrl-single,pins = <0x03c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_16 (ZCZ ball V13) */ + P8_16_default_pin: pinmux_P8_16_default_pin { + pinctrl-single,pins = <0x038 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_16_gpio_pin: pinmux_P8_16_gpio_pin { + pinctrl-single,pins = <0x038 0x2F>; }; /* Mode 7, RxActive */ + P8_16_gpio_pu_pin: pinmux_P8_16_gpio_pu_pin { + pinctrl-single,pins = <0x038 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_16_gpio_pd_pin: pinmux_P8_16_gpio_pd_pin { + pinctrl-single,pins = <0x038 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_16_pruin_pin: pinmux_P8_16_pruin_pin { + pinctrl-single,pins = <0x038 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_16_qep_pin: pinmux_P8_16_qep_pin { + pinctrl-single,pins = <0x038 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_17 (ZCZ ball U12) */ + P8_17_default_pin: pinmux_P8_17_default_pin { + pinctrl-single,pins = <0x02c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_17_gpio_pin: pinmux_P8_17_gpio_pin { + pinctrl-single,pins = <0x02c 0x2F>; }; /* Mode 7, RxActive */ + P8_17_gpio_pu_pin: pinmux_P8_17_gpio_pu_pin { + pinctrl-single,pins = <0x02c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_17_gpio_pd_pin: pinmux_P8_17_gpio_pd_pin { + pinctrl-single,pins = <0x02c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_17_pwm_pin: pinmux_P8_17_pwm_pin { + pinctrl-single,pins = <0x02c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_18 (ZCZ ball V12) */ + P8_18_default_pin: pinmux_P8_18_default_pin { + pinctrl-single,pins = <0x08c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_18_gpio_pin: pinmux_P8_18_gpio_pin { + pinctrl-single,pins = <0x08c 0x2F>; }; /* Mode 7, RxActive */ + P8_18_gpio_pu_pin: pinmux_P8_18_gpio_pu_pin { + pinctrl-single,pins = <0x08c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_18_gpio_pd_pin: pinmux_P8_18_gpio_pd_pin { + pinctrl-single,pins = <0x08c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + + /* P8_19 (ZCZ ball U10) */ + P8_19_default_pin: pinmux_P8_19_default_pin { + pinctrl-single,pins = <0x020 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_19_gpio_pin: pinmux_P8_19_gpio_pin { + pinctrl-single,pins = <0x020 0x2F>; }; /* Mode 7, RxActive */ + P8_19_gpio_pu_pin: pinmux_P8_19_gpio_pu_pin { + pinctrl-single,pins = <0x020 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_19_gpio_pd_pin: pinmux_P8_19_gpio_pd_pin { + pinctrl-single,pins = <0x020 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_19_pwm_pin: pinmux_P8_19_pwm_pin { + pinctrl-single,pins = <0x020 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P8_20 (ZCZ ball V9 ) emmc */ + /* P8_21 (ZCZ ball U9 ) emmc */ + /* P8_22 (ZCZ ball V8 ) emmc */ + /* P8_23 (ZCZ ball U8 ) emmc */ + /* P8_24 (ZCZ ball V7 ) emmc */ + /* P8_25 (ZCZ ball U7 ) emmc */ + + /* P8_26 (ZCZ ball V6 ) */ + P8_26_default_pin: pinmux_P8_26_default_pin { + pinctrl-single,pins = <0x07c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_26_gpio_pin: pinmux_P8_26_gpio_pin { + pinctrl-single,pins = <0x07c 0x2F>; }; /* Mode 7, RxActive */ + P8_26_gpio_pu_pin: pinmux_P8_26_gpio_pu_pin { + pinctrl-single,pins = <0x07c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_26_gpio_pd_pin: pinmux_P8_26_gpio_pd_pin { + pinctrl-single,pins = <0x07c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + + /* P8_27 (ZCZ ball U5 ) hdmi */ + P8_27_default_pin: pinmux_P8_27_default_pin { + pinctrl-single,pins = <0x0e0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_27_gpio_pin: pinmux_P8_27_gpio_pin { + pinctrl-single,pins = <0x0e0 0x2F>; }; /* Mode 7, RxActive */ + P8_27_gpio_pu_pin: pinmux_P8_27_gpio_pu_pin { + pinctrl-single,pins = <0x0e0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_27_gpio_pd_pin: pinmux_P8_27_gpio_pd_pin { + pinctrl-single,pins = <0x0e0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_27_pruout_pin: pinmux_P8_27_pruout_pin { + pinctrl-single,pins = <0x0e0 0x05>; }; /* Mode 5, Pull-Down*/ + P8_27_pruin_pin: pinmux_P8_27_pruin_pin { + pinctrl-single,pins = <0x0e0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_27_hdmi_pin: pinmux_P8_27_hdmi_pin { + pinctrl-single,pins = <0x0e0 0x00>; }; /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + + /* P8_28 (ZCZ ball V5 ) hdmi */ + P8_28_default_pin: pinmux_P8_28_default_pin { + pinctrl-single,pins = <0x0e8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_28_gpio_pin: pinmux_P8_28_gpio_pin { + pinctrl-single,pins = <0x0e8 0x2F>; }; /* Mode 7, RxActive */ + P8_28_gpio_pu_pin: pinmux_P8_28_gpio_pu_pin { + pinctrl-single,pins = <0x0e8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_28_gpio_pd_pin: pinmux_P8_28_gpio_pd_pin { + pinctrl-single,pins = <0x0e8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_28_pruout_pin: pinmux_P8_28_pruout_pin { + pinctrl-single,pins = <0x0e8 0x05>; }; /* Mode 5, Pull-Down */ + P8_28_pruin_pin: pinmux_P8_28_pruin_pin { + pinctrl-single,pins = <0x0e8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_28_hdmi_pin: pinmux_P8_28_hdmi_pin { + pinctrl-single,pins = <0x0e8 0x00>; }; /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + + /* P8_29 (ZCZ ball R5 ) hdmi */ + P8_29_default_pin: pinmux_P8_29_default_pin { + pinctrl-single,pins = <0x0e4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_29_gpio_pin: pinmux_P8_29_gpio_pin { + pinctrl-single,pins = <0x0e4 0x2F>; }; /* Mode 7, RxActive */ + P8_29_gpio_pu_pin: pinmux_P8_29_gpio_pu_pin { + pinctrl-single,pins = <0x0e4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_29_gpio_pd_pin: pinmux_P8_29_gpio_pd_pin { + pinctrl-single,pins = <0x0e4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_29_pruout_pin: pinmux_P8_29_pruout_pin { + pinctrl-single,pins = <0x0e4 0x05>; }; /* Mode 5, Pull-Down*/ + P8_29_pruin_pin: pinmux_P8_29_pruin_pin { + pinctrl-single,pins = <0x0e4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_29_hdmi_pin: pinmux_P8_29_hdmi_pin { + pinctrl-single,pins = <0x0e4 0x00>; }; /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + + /* P8_30 (ZCZ ball R6 ) hdmi */ + P8_30_default_pin: pinmux_P8_30_default_pin { + pinctrl-single,pins = <0x0ec 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_30_gpio_pin: pinmux_P8_30_gpio_pin { + pinctrl-single,pins = <0x0ec 0x2F>; }; /* Mode 7, RxActive */ + P8_30_gpio_pu_pin: pinmux_P8_30_gpio_pu_pin { + pinctrl-single,pins = <0x0ec 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_30_gpio_pd_pin: pinmux_P8_30_gpio_pd_pin { + pinctrl-single,pins = <0x0ec 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_30_pruout_pin: pinmux_P8_30_pruout_pin { + pinctrl-single,pins = <0x0ec 0x05>; }; /* Mode 5, Pull-Down*/ + P8_30_pruin_pin: pinmux_P8_30_pruin_pin { + pinctrl-single,pins = <0x0ec 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_30_hdmi_pin: pinmux_P8_30_hdmi_pin { + pinctrl-single,pins = <0x0ec 0x00>; }; /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */ + + /* P8_31 (ZCZ ball V4 ) hdmi */ + P8_31_default_pin: pinmux_P8_31_default_pin { + pinctrl-single,pins = <0x0d8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_31_gpio_pin: pinmux_P8_31_gpio_pin { + pinctrl-single,pins = <0x0d8 0x2F>; }; /* Mode 7, RxActive */ + P8_31_gpio_pu_pin: pinmux_P8_31_gpio_pu_pin { + pinctrl-single,pins = <0x0d8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_31_gpio_pd_pin: pinmux_P8_31_gpio_pd_pin { + pinctrl-single,pins = <0x0d8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_31_uart_pin: pinmux_P8_31_uart_pin { + pinctrl-single,pins = <0x0d8 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + P8_31_hdmi_pin: pinmux_P8_31_hdmi_pin { + pinctrl-single,pins = <0x0d8 0x08>; }; /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_32 (ZCZ ball T5 ) hdmi */ + P8_32_default_pin: pinmux_P8_32_default_pin { + pinctrl-single,pins = <0x0dc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_32_gpio_pin: pinmux_P8_32_gpio_pin { + pinctrl-single,pins = <0x0dc 0x2F>; }; /* Mode 7, RxActive */ + P8_32_gpio_pu_pin: pinmux_P8_32_gpio_pu_pin { + pinctrl-single,pins = <0x0dc 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_32_gpio_pd_pin: pinmux_P8_32_gpio_pd_pin { + pinctrl-single,pins = <0x0dc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_32_uart_pin: pinmux_P8_32_uart_pin { + pinctrl-single,pins = <0x0dc 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_32_hdmi_pin: pinmux_P8_32_hdmi_pin { + pinctrl-single,pins = <0x0dc 0x08>; }; /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_33 (ZCZ ball V3 ) hdmi */ + P8_33_default_pin: pinmux_P8_33_default_pin { + pinctrl-single,pins = <0x0d4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_33_gpio_pin: pinmux_P8_33_gpio_pin { + pinctrl-single,pins = <0x0d4 0x2F>; }; /* Mode 7, RxActive */ + P8_33_gpio_pu_pin: pinmux_P8_33_gpio_pu_pin { + pinctrl-single,pins = <0x0d4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_33_gpio_pd_pin: pinmux_P8_33_gpio_pd_pin { + pinctrl-single,pins = <0x0d4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_33_hdmi_pin: pinmux_P8_33_hdmi_pin { + pinctrl-single,pins = <0x0d4 0x08>; }; /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_34 (ZCZ ball U4 ) hdmi */ + P8_34_default_pin: pinmux_P8_34_default_pin { + pinctrl-single,pins = <0x0cc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_34_gpio_pin: pinmux_P8_34_gpio_pin { + pinctrl-single,pins = <0x0cc 0x2F>; }; /* Mode 7, RxActive */ + P8_34_gpio_pu_pin: pinmux_P8_34_gpio_pu_pin { + pinctrl-single,pins = <0x0cc 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_34_gpio_pd_pin: pinmux_P8_34_gpio_pd_pin { + pinctrl-single,pins = <0x0cc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_34_pwm_pin: pinmux_P8_34_pwm_pin { + pinctrl-single,pins = <0x0cc 0x22>; }; /* Mode 2, Pull-Down, RxActive */ + P8_34_hdmi_pin: pinmux_P8_34_hdmi_pin { + pinctrl-single,pins = <0x0cc 0x08>; }; /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_35 (ZCZ ball V2 ) hdmi */ + P8_35_default_pin: pinmux_P8_35_default_pin { + pinctrl-single,pins = <0x0d0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_35_gpio_pin: pinmux_P8_35_gpio_pin { + pinctrl-single,pins = <0x0d0 0x2F>; }; /* Mode 7, RxActive */ + P8_35_gpio_pu_pin: pinmux_P8_35_gpio_pu_pin { + pinctrl-single,pins = <0x0d0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_35_gpio_pd_pin: pinmux_P8_35_gpio_pd_pin { + pinctrl-single,pins = <0x0d0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_35_hdmi_pin: pinmux_P8_35_hdmi_pin { + pinctrl-single,pins = <0x0d0 0x08>; }; /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_36 (ZCZ ball U3 ) hdmi */ + P8_36_default_pin: pinmux_P8_36_default_pin { + pinctrl-single,pins = <0x0c8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_36_gpio_pin: pinmux_P8_36_gpio_pin { + pinctrl-single,pins = <0x0c8 0x2F>; }; /* Mode 7, RxActive */ + P8_36_gpio_pu_pin: pinmux_P8_36_gpio_pu_pin { + pinctrl-single,pins = <0x0c8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_36_gpio_pd_pin: pinmux_P8_36_gpio_pd_pin { + pinctrl-single,pins = <0x0c8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_36_pwm_pin: pinmux_P8_36_pwm_pin { + pinctrl-single,pins = <0x0c8 0x22>; }; /* Mode 2, Pull-Down, RxActive */ + P8_36_hdmi_pin: pinmux_P8_36_hdmi_pin { + pinctrl-single,pins = <0x0c8 0x08>; }; /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_37 (ZCZ ball U1 ) hdmi */ + P8_37_default_pin: pinmux_P8_37_default_pin { + pinctrl-single,pins = <0x0c0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_37_gpio_pin: pinmux_P8_37_gpio_pin { + pinctrl-single,pins = <0x0c0 0x2F>; }; /* Mode 7, RxActive */ + P8_37_gpio_pu_pin: pinmux_P8_37_gpio_pu_pin { + pinctrl-single,pins = <0x0c0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_37_gpio_pd_pin: pinmux_P8_37_gpio_pd_pin { + pinctrl-single,pins = <0x0c0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_37_uart_pin: pinmux_P8_37_uart_pin { + pinctrl-single,pins = <0x0c0 0x04>; }; /* Mode 4, Pull-Down*/ + P8_37_pwm_pin: pinmux_P8_37_pwm_pin { + pinctrl-single,pins = <0x0c0 0x02>; }; /* Mode 2, Pull-Down*/ + P8_37_hdmi_pin: pinmux_P8_37_hdmi_pin { + pinctrl-single,pins = <0x0c0 0x08>; }; /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + + /* P8_38 (ZCZ ball U2 ) hdmi */ + P8_38_default_pin: pinmux_P8_38_default_pin { + pinctrl-single,pins = <0x0c4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_38_gpio_pin: pinmux_P8_38_gpio_pin { + pinctrl-single,pins = <0x0c4 0x2F>; }; /* Mode 7, RxActive */ + P8_38_gpio_pu_pin: pinmux_P8_38_gpio_pu_pin { + pinctrl-single,pins = <0x0c4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_38_gpio_pd_pin: pinmux_P8_38_gpio_pd_pin { + pinctrl-single,pins = <0x0c4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_38_uart_pin: pinmux_P8_38_uart_pin { + pinctrl-single,pins = <0x0c4 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + P8_38_pwm_pin: pinmux_P8_38_pwm_pin { + pinctrl-single,pins = <0x0c4 0x22>; }; /* Mode 2, Pull-Down, RxActive */ + P8_38_hdmi_pin: pinmux_P8_38_hdmi_pin { + pinctrl-single,pins = <0x0c4 0x08>; }; /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + + /* P8_39 (ZCZ ball T3 ) hdmi */ + P8_39_default_pin: pinmux_P8_39_default_pin { + pinctrl-single,pins = <0x0b8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_39_gpio_pin: pinmux_P8_39_gpio_pin { + pinctrl-single,pins = <0x0b8 0x2F>; }; /* Mode 7, RxActive */ + P8_39_gpio_pu_pin: pinmux_P8_39_gpio_pu_pin { + pinctrl-single,pins = <0x0b8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_39_gpio_pd_pin: pinmux_P8_39_gpio_pd_pin { + pinctrl-single,pins = <0x0b8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_39_pruout_pin: pinmux_P8_39_pruout_pin { + pinctrl-single,pins = <0x0b8 0x05>; }; /* Mode 5, Pull-Down*/ + P8_39_pruin_pin: pinmux_P8_39_pruin_pin { + pinctrl-single,pins = <0x0b8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_39_hdmi_pin: pinmux_P8_39_hdmi_pin { + pinctrl-single,pins = <0x0b8 0x08>; }; /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_40 (ZCZ ball T4 ) hdmi */ + P8_40_default_pin: pinmux_P8_40_default_pin { + pinctrl-single,pins = <0x0bc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_40_gpio_pin: pinmux_P8_40_gpio_pin { + pinctrl-single,pins = <0x0bc 0x2F>; }; /* Mode 7, RxActive */ + P8_40_gpio_pu_pin: pinmux_P8_40_gpio_pu_pin { + pinctrl-single,pins = <0x0bc 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_40_gpio_pd_pin: pinmux_P8_40_gpio_pd_pin { + pinctrl-single,pins = <0x0bc 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_40_pruout_pin: pinmux_P8_40_pruout_pin { + pinctrl-single,pins = <0x0bc 0x05>; }; /* Mode 5, Pull-Down*/ + P8_40_pruin_pin: pinmux_P8_40_pruin_pin { + pinctrl-single,pins = <0x0bc 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_40_hdmi_pin: pinmux_P8_40_hdmi_pin { + pinctrl-single,pins = <0x0bc 0x08>; }; /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_41 (ZCZ ball T1 ) hdmi */ + P8_41_default_pin: pinmux_P8_41_default_pin { + pinctrl-single,pins = <0x0b0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_41_gpio_pin: pinmux_P8_41_gpio_pin { + pinctrl-single,pins = <0x0b0 0x2F>; }; /* Mode 7, RxActive */ + P8_41_gpio_pu_pin: pinmux_P8_41_gpio_pu_pin { + pinctrl-single,pins = <0x0b0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_41_gpio_pd_pin: pinmux_P8_41_gpio_pd_pin { + pinctrl-single,pins = <0x0b0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_41_pruout_pin: pinmux_P8_41_pruout_pin { + pinctrl-single,pins = <0x0b0 0x05>; }; /* Mode 5, Pull-Down*/ + P8_41_pruin_pin: pinmux_P8_41_pruin_pin { + pinctrl-single,pins = <0x0b0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_41_hdmi_pin: pinmux_P8_41_hdmi_pin { + pinctrl-single,pins = <0x0b0 0x08>; }; /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_42 (ZCZ ball T2 ) hdmi */ + P8_42_default_pin: pinmux_P8_42_default_pin { + pinctrl-single,pins = <0x0b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_42_gpio_pin: pinmux_P8_42_gpio_pin { + pinctrl-single,pins = <0x0b4 0x2F>; }; /* Mode 7, RxActive */ + P8_42_gpio_pu_pin: pinmux_P8_42_gpio_pu_pin { + pinctrl-single,pins = <0x0b4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_42_gpio_pd_pin: pinmux_P8_42_gpio_pd_pin { + pinctrl-single,pins = <0x0b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_42_pruout_pin: pinmux_P8_42_pruout_pin { + pinctrl-single,pins = <0x0b4 0x05>; }; /* Mode 5, Pull-Down*/ + P8_42_pruin_pin: pinmux_P8_42_pruin_pin { + pinctrl-single,pins = <0x0b4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_42_hdmi_pin: pinmux_P8_42_hdmi_pin { + pinctrl-single,pins = <0x0b4 0x08>; }; /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_43 (ZCZ ball R3 ) hdmi */ + P8_43_default_pin: pinmux_P8_43_default_pin { + pinctrl-single,pins = <0x0a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_43_gpio_pin: pinmux_P8_43_gpio_pin { + pinctrl-single,pins = <0x0a8 0x2F>; }; /* Mode 7, RxActive */ + P8_43_gpio_pu_pin: pinmux_P8_43_gpio_pu_pin { + pinctrl-single,pins = <0x0a8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_43_gpio_pd_pin: pinmux_P8_43_gpio_pd_pin { + pinctrl-single,pins = <0x0a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_43_pruout_pin: pinmux_P8_43_pruout_pin { + pinctrl-single,pins = <0x0a8 0x05>; }; /* Mode 5, Pull-Down*/ + P8_43_pruin_pin: pinmux_P8_43_pruin_pin { + pinctrl-single,pins = <0x0a8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_43_pwm_pin: pinmux_P8_43_pwm_pin { + pinctrl-single,pins = <0x0a8 0x03>; }; /* Mode 3, Pull-Down */ + P8_43_hdmi_pin: pinmux_P8_43_hdmi_pin { + pinctrl-single,pins = <0x0a8 0x08>; }; /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_44 (ZCZ ball R4 ) hdmi */ + P8_44_default_pin: pinmux_P8_44_default_pin { + pinctrl-single,pins = <0x0ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_44_gpio_pin: pinmux_P8_44_gpio_pin { + pinctrl-single,pins = <0x0ac 0x2F>; }; /* Mode 7, RxActive */ + P8_44_gpio_pu_pin: pinmux_P8_44_gpio_pu_pin { + pinctrl-single,pins = <0x0ac 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_44_gpio_pd_pin: pinmux_P8_44_gpio_pd_pin { + pinctrl-single,pins = <0x0ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_44_pruout_pin: pinmux_P8_44_pruout_pin { + pinctrl-single,pins = <0x0ac 0x05>; }; /* Mode 5, Pull-Down*/ + P8_44_pruin_pin: pinmux_P8_44_pruin_pin { + pinctrl-single,pins = <0x0ac 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_44_pwm_pin: pinmux_P8_44_pwm_pin { + pinctrl-single,pins = <0x0ac 0x23>; }; /* Mode 3, Pull-Down, RxActive */ + P8_44_hdmi_pin: pinmux_P8_44_hdmi_pin { + pinctrl-single,pins = <0x0ac 0x08>; }; /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_45 (ZCZ ball R1 ) hdmi */ + P8_45_default_pin: pinmux_P8_45_default_pin { + pinctrl-single,pins = <0x0a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_45_gpio_pin: pinmux_P8_45_gpio_pin { + pinctrl-single,pins = <0x0a0 0x2F>; }; /* Mode 7, RxActive */ + P8_45_gpio_pu_pin: pinmux_P8_45_gpio_pu_pin { + pinctrl-single,pins = <0x0a0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_45_gpio_pd_pin: pinmux_P8_45_gpio_pd_pin { + pinctrl-single,pins = <0x0a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_45_pruout_pin: pinmux_P8_45_pruout_pin { + pinctrl-single,pins = <0x0a0 0x05>; }; /* Mode 5, Pull-Down*/ + P8_45_pruin_pin: pinmux_P8_45_pruin_pin { + pinctrl-single,pins = <0x0a0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_45_pwm_pin: pinmux_P8_45_pwm_pin { + pinctrl-single,pins = <0x0a0 0x03>; }; /* Mode 3, Pull-Down*/ + P8_45_hdmi_pin: pinmux_P8_45_hdmi_pin { + pinctrl-single,pins = <0x0a0 0x08>; }; /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /* P8_46 (ZCZ ball R2 ) hdmi */ + P8_46_default_pin: pinmux_P8_46_default_pin { + pinctrl-single,pins = <0x0a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_46_gpio_pin: pinmux_P8_46_gpio_pin { + pinctrl-single,pins = <0x0a4 0x2F>; }; /* Mode 7, RxActive */ + P8_46_gpio_pu_pin: pinmux_P8_46_gpio_pu_pin { + pinctrl-single,pins = <0x0a4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P8_46_gpio_pd_pin: pinmux_P8_46_gpio_pd_pin { + pinctrl-single,pins = <0x0a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P8_46_pruout_pin: pinmux_P8_46_pruout_pin { + pinctrl-single,pins = <0x0a4 0x05>; }; /* Mode 5, Pull-Down*/ + P8_46_pruin_pin: pinmux_P8_46_pruin_pin { + pinctrl-single,pins = <0x0a4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P8_46_pwm_pin: pinmux_P8_46_pwm_pin { + pinctrl-single,pins = <0x0a4 0x03>; }; /* Mode 3, Pull-Down*/ + P8_46_hdmi_pin: pinmux_P8_46_hdmi_pin { + pinctrl-single,pins = <0x0a4 0x08>; }; /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */ + + /************************/ + /* P9 Header */ + /************************/ + + /* P9_01 GND */ + /* P9_02 GND */ + /* P9_03 3.3V */ + /* P9_04 3.3V */ + /* P9_05 VDD_5V */ + /* P9_06 VDD_5V */ + /* P9_07 SYS_5V */ + /* P9_08 SYS_5V */ + /* P9_09 PWR_BUT */ + /* P9_10 (ZCZ ball A10) RESETn */ + + /* P9_11 (ZCZ ball T17) */ + P9_11_default_pin: pinmux_P9_11_default_pin { + pinctrl-single,pins = <0x070 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_11_gpio_pin: pinmux_P9_11_gpio_pin { + pinctrl-single,pins = <0x070 0x2F>; }; /* Mode 7, RxActive */ + P9_11_gpio_pu_pin: pinmux_P9_11_gpio_pu_pin { + pinctrl-single,pins = <0x070 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_11_gpio_pd_pin: pinmux_P9_11_gpio_pd_pin { + pinctrl-single,pins = <0x070 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_11_uart_pin: pinmux_P9_11_uart_pin { + pinctrl-single,pins = <0x070 0x36>; }; /* Mode 6, Pull-Up, RxActive */ + + /* P9_12 (ZCZ ball U18) */ + P9_12_default_pin: pinmux_P9_12_default_pin { + pinctrl-single,pins = <0x078 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_12_gpio_pin: pinmux_P9_12_gpio_pin { + pinctrl-single,pins = <0x078 0x2F>; }; /* Mode 7, RxActive */ + P9_12_gpio_pu_pin: pinmux_P9_12_gpio_pu_pin { + pinctrl-single,pins = <0x078 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_12_gpio_pd_pin: pinmux_P9_12_gpio_pd_pin { + pinctrl-single,pins = <0x078 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + + /* P9_13 (ZCZ ball U17) */ + P9_13_default_pin: pinmux_P9_13_default_pin { + pinctrl-single,pins = <0x074 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_13_gpio_pin: pinmux_P9_13_gpio_pin { + pinctrl-single,pins = <0x074 0x2F>; }; /* Mode 7, RxActive */ + P9_13_gpio_pu_pin: pinmux_P9_13_gpio_pu_pin { + pinctrl-single,pins = <0x074 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_13_gpio_pd_pin: pinmux_P9_13_gpio_pd_pin { + pinctrl-single,pins = <0x074 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_13_uart_pin: pinmux_P9_13_uart_pin { + pinctrl-single,pins = <0x074 0x36>; }; /* Mode 6, Pull-Up, RxActive */ + + /* P9_14 (ZCZ ball U14) */ + P9_14_default_pin: pinmux_P9_14_default_pin { + pinctrl-single,pins = <0x048 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_14_gpio_pin: pinmux_P9_14_gpio_pin { + pinctrl-single,pins = <0x048 0x2F>; }; /* Mode 7, RxActive */ + P9_14_gpio_pu_pin: pinmux_P9_14_gpio_pu_pin { + pinctrl-single,pins = <0x048 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_14_gpio_pd_pin: pinmux_P9_14_gpio_pd_pin { + pinctrl-single,pins = <0x048 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_14_pwm_pin: pinmux_P9_14_pwm_pin { + pinctrl-single,pins = <0x048 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_15 (ZCZ ball R13) */ + P9_15_default_pin: pinmux_P9_15_default_pin { + pinctrl-single,pins = <0x040 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_15_gpio_pin: pinmux_P9_15_gpio_pin { + pinctrl-single,pins = <0x040 0x2F>; }; /* Mode 7, RxActive */ + P9_15_gpio_pu_pin: pinmux_P9_15_gpio_pu_pin { + pinctrl-single,pins = <0x040 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_15_gpio_pd_pin: pinmux_P9_15_gpio_pd_pin { + pinctrl-single,pins = <0x040 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_15_pwm_pin: pinmux_P9_15_pwm_pin { + pinctrl-single,pins = <0x040 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_16 (ZCZ ball T14) */ + P9_16_default_pin: pinmux_P9_16_default_pin { + pinctrl-single,pins = <0x04c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_16_gpio_pin: pinmux_P9_16_gpio_pin { + pinctrl-single,pins = <0x04c 0x2F>; }; /* Mode 7, RxActive */ + P9_16_gpio_pu_pin: pinmux_P9_16_gpio_pu_pin { + pinctrl-single,pins = <0x04c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_16_gpio_pd_pin: pinmux_P9_16_gpio_pd_pin { + pinctrl-single,pins = <0x04c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_16_pwm_pin: pinmux_P9_16_pwm_pin { + pinctrl-single,pins = <0x04c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_17 (ZCZ ball A16) */ + P9_17_default_pin: pinmux_P9_17_default_pin { + pinctrl-single,pins = <0x15c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_17_gpio_pin: pinmux_P9_17_gpio_pin { + pinctrl-single,pins = <0x15c 0x2F>; }; /* Mode 7, RxActive */ + P9_17_gpio_pu_pin: pinmux_P9_17_gpio_pu_pin { + pinctrl-single,pins = <0x15c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_17_gpio_pd_pin: pinmux_P9_17_gpio_pd_pin { + pinctrl-single,pins = <0x15c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_17_spi_pin: pinmux_P9_17_spi_pin { + pinctrl-single,pins = <0x15c 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_17_i2c_pin: pinmux_P9_17_i2c_pin { + pinctrl-single,pins = <0x15c 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_17_pwm_pin: pinmux_P9_17_pwm_pin { + pinctrl-single,pins = <0x15c 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + + /* P9_18 (ZCZ ball B16) */ + P9_18_default_pin: pinmux_P9_18_default_pin { + pinctrl-single,pins = <0x158 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_18_gpio_pin: pinmux_P9_18_gpio_pin { + pinctrl-single,pins = <0x158 0x2F>; }; /* Mode 7, RxActive */ + P9_18_gpio_pu_pin: pinmux_P9_18_gpio_pu_pin { + pinctrl-single,pins = <0x158 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_18_gpio_pd_pin: pinmux_P9_18_gpio_pd_pin { + pinctrl-single,pins = <0x158 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_18_spi_pin: pinmux_P9_18_spi_pin { + pinctrl-single,pins = <0x158 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_18_i2c_pin: pinmux_P9_18_i2c_pin { + pinctrl-single,pins = <0x158 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_18_pwm_pin: pinmux_P9_18_pwm_pin { + pinctrl-single,pins = <0x158 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + + /* P9_19 (ZCZ ball D17) */ + P9_19_default_pin: pinmux_P9_19_default_pin { + pinctrl-single,pins = <0x17c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_19_gpio_pin: pinmux_P9_19_gpio_pin { + pinctrl-single,pins = <0x17c 0x2F>; }; /* Mode 7, RxActive */ + P9_19_gpio_pu_pin: pinmux_P9_19_gpio_pu_pin { + pinctrl-single,pins = <0x17c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_19_gpio_pd_pin: pinmux_P9_19_gpio_pd_pin { + pinctrl-single,pins = <0x17c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_19_can_pin: pinmux_P9_19_can_pin { + pinctrl-single,pins = <0x17c 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_19_i2c_pin: pinmux_P9_19_i2c_pin { + pinctrl-single,pins = <0x17c 0x73>; }; /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) */ + + /* P9_20 (ZCZ ball D18) */ + P9_20_default_pin: pinmux_P9_20_default_pin { + pinctrl-single,pins = <0x178 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_20_gpio_pin: pinmux_P9_20_gpio_pin { + pinctrl-single,pins = <0x178 0x2F>; }; /* Mode 7, RxActive */ + P9_20_gpio_pu_pin: pinmux_P9_20_gpio_pu_pin { + pinctrl-single,pins = <0x178 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_20_gpio_pd_pin: pinmux_P9_20_gpio_pd_pin { + pinctrl-single,pins = <0x178 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_20_can_pin: pinmux_P9_20_can_pin { + pinctrl-single,pins = <0x178 0x12>; }; /* Mode 2, Pull-Up, RxActive */ + P9_20_i2c_pin: pinmux_P9_20_i2c_pin { + pinctrl-single,pins = <0x178 0x73>; }; /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) */ + + /* P9_21 (ZCZ ball B17) */ + P9_21_default_pin: pinmux_P9_21_default_pin { + pinctrl-single,pins = <0x154 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_21_gpio_pin: pinmux_P9_21_gpio_pin { + pinctrl-single,pins = <0x154 0x2F>; }; /* Mode 7, RxActive */ + P9_21_gpio_pu_pin: pinmux_P9_21_gpio_pu_pin { + pinctrl-single,pins = <0x154 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_21_gpio_pd_pin: pinmux_P9_21_gpio_pd_pin { + pinctrl-single,pins = <0x154 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_21_spi_pin: pinmux_P9_21_spi_pin { + pinctrl-single,pins = <0x154 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_21_uart_pin: pinmux_P9_21_uart_pin { + pinctrl-single,pins = <0x154 0x31>; }; /* Mode 1, Pull-Up, RxActive */ + P9_21_i2c_pin: pinmux_P9_21_i2c_pin { + pinctrl-single,pins = <0x154 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_21_pwm_pin: pinmux_P9_21_pwm_pin { + pinctrl-single,pins = <0x154 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + + /* P9_22 (ZCZ ball A17) */ + P9_22_default_pin: pinmux_P9_22_default_pin { + pinctrl-single,pins = <0x150 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_22_gpio_pin: pinmux_P9_22_gpio_pin { + pinctrl-single,pins = <0x150 0x2F>; }; /* Mode 7, RxActive */ + P9_22_gpio_pu_pin: pinmux_P9_22_gpio_pu_pin { + pinctrl-single,pins = <0x150 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_22_gpio_pd_pin: pinmux_P9_22_gpio_pd_pin { + pinctrl-single,pins = <0x150 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_22_spi_pin: pinmux_P9_22_spi_pin { + pinctrl-single,pins = <0x150 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_22_uart_pin: pinmux_P9_22_uart_pin { + pinctrl-single,pins = <0x150 0x31>; }; /* Mode 1, Pull-Up, RxActive */ + P9_22_i2c_pin: pinmux_P9_22_i2c_pin { + pinctrl-single,pins = <0x150 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_22_pwm_pin: pinmux_P9_22_pwm_pin { + pinctrl-single,pins = <0x150 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + + /* P9_23 (ZCZ ball V14) */ + P9_23_default_pin: pinmux_P9_23_default_pin { + pinctrl-single,pins = <0x044 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_23_gpio_pin: pinmux_P9_23_gpio_pin { + pinctrl-single,pins = <0x044 0x2F>; }; /* Mode 7, RxActive */ + P9_23_gpio_pu_pin: pinmux_P9_23_gpio_pu_pin { + pinctrl-single,pins = <0x044 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_23_gpio_pd_pin: pinmux_P9_23_gpio_pd_pin { + pinctrl-single,pins = <0x044 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_23_pwm_pin: pinmux_P9_23_pwm_pin { + pinctrl-single,pins = <0x044 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_24 (ZCZ ball D15) */ + P9_24_default_pin: pinmux_P9_24_default_pin { + pinctrl-single,pins = <0x184 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_24_gpio_pin: pinmux_P9_24_gpio_pin { + pinctrl-single,pins = <0x184 0x2F>; }; /* Mode 7, RxActive */ + P9_24_gpio_pu_pin: pinmux_P9_24_gpio_pu_pin { + pinctrl-single,pins = <0x184 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_24_gpio_pd_pin: pinmux_P9_24_gpio_pd_pin { + pinctrl-single,pins = <0x184 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_24_uart_pin: pinmux_P9_24_uart_pin { + pinctrl-single,pins = <0x184 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_24_can_pin: pinmux_P9_24_can_pin { + pinctrl-single,pins = <0x184 0x32>; }; /* Mode 2, Pull-Up, RxActive */ + P9_24_i2c_pin: pinmux_P9_24_i2c_pin { + pinctrl-single,pins = <0x184 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + P9_24_pruin_pin: pinmux_P9_24_pruin_pin { + pinctrl-single,pins = <0x184 0x36>; }; /* Mode 6, Pull-Up, RxActive */ + + /* P9_25 (ZCZ ball A14) Audio */ + P9_25_default_pin: pinmux_P9_25_default_pin { + pinctrl-single,pins = <0x1ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_25_gpio_pin: pinmux_P9_25_gpio_pin { + pinctrl-single,pins = <0x1ac 0x2F>; }; /* Mode 7, RxActive */ + P9_25_gpio_pu_pin: pinmux_P9_25_gpio_pu_pin { + pinctrl-single,pins = <0x1ac 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_25_gpio_pd_pin: pinmux_P9_25_gpio_pd_pin { + pinctrl-single,pins = <0x1ac 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_25_qep_pin: pinmux_P9_25_qep_pin { + pinctrl-single,pins = <0x1ac 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_25_pruout_pin: pinmux_P9_25_pruout_pin { + pinctrl-single,pins = <0x1ac 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_25_pruin_pin: pinmux_P9_25_pruin_pin { + pinctrl-single,pins = <0x1ac 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P9_25_audio_pin: pinmux_P9_25_audio_pin { + pinctrl-single,pins = <0x1ac (PIN_INPUT_PULLUP | MUX_MODE0)>; }; /* mcasp0_ahclkx.mcasp0_ahclkx */ + + /* P9_26 (ZCZ ball D16) */ + P9_26_default_pin: pinmux_P9_26_default_pin { + pinctrl-single,pins = <0x180 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_26_gpio_pin: pinmux_P9_26_gpio_pin { + pinctrl-single,pins = <0x180 0x2F>; }; /* Mode 7, RxActive */ + P9_26_gpio_pu_pin: pinmux_P9_26_gpio_pu_pin { + pinctrl-single,pins = <0x180 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_26_gpio_pd_pin: pinmux_P9_26_gpio_pd_pin { + pinctrl-single,pins = <0x180 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_26_uart_pin: pinmux_P9_26_uart_pin { + pinctrl-single,pins = <0x180 0x30>; }; /* Mode 0, Pull-Up, RxActive */ + P9_26_can_pin: pinmux_P9_26_can_pin { + pinctrl-single,pins = <0x180 0x12>; }; /* Mode 2, Pull-Up, RxActive */ + P9_26_i2c_pin: pinmux_P9_26_i2c_pin { + pinctrl-single,pins = <0x180 0x33>; }; /* Mode 3, Pull-Up, RxActive */ + P9_26_pruin_pin: pinmux_P9_26_pruin_pin { + pinctrl-single,pins = <0x180 0x36>; }; /* Mode 6, Pull-Up, RxActive */ + + /* P9_27 (ZCZ ball C13) */ + P9_27_default_pin: pinmux_P9_27_default_pin { + pinctrl-single,pins = <0x1a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_27_gpio_pin: pinmux_P9_27_gpio_pin { + pinctrl-single,pins = <0x1a4 0x2F>; }; /* Mode 7, RxActive */ + P9_27_gpio_pu_pin: pinmux_P9_27_gpio_pu_pin { + pinctrl-single,pins = <0x1a4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_27_gpio_pd_pin: pinmux_P9_27_gpio_pd_pin { + pinctrl-single,pins = <0x1a4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_27_qep_pin: pinmux_P9_27_qep_pin { + pinctrl-single,pins = <0x1a4 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_27_pruout_pin: pinmux_P9_27_pruout_pin { + pinctrl-single,pins = <0x1a4 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_27_pruin_pin: pinmux_P9_27_pruin_pin { + pinctrl-single,pins = <0x1a4 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_28 (ZCZ ball C12) Audio */ + P9_28_default_pin: pinmux_P9_28_default_pin { + pinctrl-single,pins = <0x19c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_28_gpio_pin: pinmux_P9_28_gpio_pin { + pinctrl-single,pins = <0x19c 0x2F>; }; /* Mode 7, RxActive */ + P9_28_gpio_pu_pin: pinmux_P9_28_gpio_pu_pin { + pinctrl-single,pins = <0x19c 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_28_gpio_pd_pin: pinmux_P9_28_gpio_pd_pin { + pinctrl-single,pins = <0x19c 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_28_pwm_pin: pinmux_P9_28_pwm_pin { + pinctrl-single,pins = <0x19c 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_28_spi_pin: pinmux_P9_28_spi_pin { + pinctrl-single,pins = <0x19c 0x23>; }; /* Mode 3, Pull-Down, RxActive */ + P9_28_pwm2_pin: pinmux_P9_28_pwm2_pin { + pinctrl-single,pins = <0x19c 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + P9_28_pruout_pin: pinmux_P9_28_pruout_pin { + pinctrl-single,pins = <0x19c 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_28_pruin_pin: pinmux_P9_28_pruin_pin { + pinctrl-single,pins = <0x19c 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P9_28_audio_pin: pinmux_P9_28_audio_pin { + pinctrl-single,pins = <0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)>; }; /* mcasp0_ahclkr.mcasp0_axr2 */ + + /* P9_29 (ZCZ ball B13) Audio */ + P9_29_default_pin: pinmux_P9_29_default_pin { + pinctrl-single,pins = <0x194 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_29_gpio_pin: pinmux_P9_29_gpio_pin { + pinctrl-single,pins = <0x194 0x2F>; }; /* Mode 7, RxActive */ + P9_29_gpio_pu_pin: pinmux_P9_29_gpio_pu_pin { + pinctrl-single,pins = <0x194 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_29_gpio_pd_pin: pinmux_P9_29_gpio_pd_pin { + pinctrl-single,pins = <0x194 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_29_pwm_pin: pinmux_P9_29_pwm_pin { + pinctrl-single,pins = <0x194 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_29_spi_pin: pinmux_P9_29_spi_pin { + pinctrl-single,pins = <0x194 0x23>; }; /* Mode 3, Pull-Down, RxActive */ + P9_29_pruout_pin: pinmux_P9_29_pruout_pin { + pinctrl-single,pins = <0x194 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_29_pruin_pin: pinmux_P9_29_pruin_pin { + pinctrl-single,pins = <0x194 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P9_29_audio_pin: pinmux_P9_29_audio_pin { + pinctrl-single,pins = <0x194 (PIN_OUTPUT_PULLUP | MUX_MODE0)>; }; /* mcasp0_fsx.mcasp0_fsx */ + + /* P9_30 (ZCZ ball D12) */ + P9_30_default_pin: pinmux_P9_30_default_pin { + pinctrl-single,pins = <0x198 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_30_gpio_pin: pinmux_P9_30_gpio_pin { + pinctrl-single,pins = <0x198 0x2F>; }; /* Mode 7, RxActive */ + P9_30_gpio_pu_pin: pinmux_P9_30_gpio_pu_pin { + pinctrl-single,pins = <0x198 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_30_gpio_pd_pin: pinmux_P9_30_gpio_pd_pin { + pinctrl-single,pins = <0x198 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_30_pwm_pin: pinmux_P9_30_pwm_pin { + pinctrl-single,pins = <0x198 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_30_spi_pin: pinmux_P9_30_spi_pin { + pinctrl-single,pins = <0x198 0x23>; }; /* Mode 3, Pull-Down, RxActive */ + P9_30_pruout_pin: pinmux_P9_30_pruout_pin { + pinctrl-single,pins = <0x198 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_30_pruin_pin: pinmux_P9_30_pruin_pin { + pinctrl-single,pins = <0x198 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_31 (ZCZ ball A13) Audio */ + P9_31_default_pin: pinmux_P9_31_default_pin { + pinctrl-single,pins = <0x190 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_31_gpio_pin: pinmux_P9_31_gpio_pin { + pinctrl-single,pins = <0x190 0x2F>; }; /* Mode 7, RxActive */ + P9_31_gpio_pu_pin: pinmux_P9_31_gpio_pu_pin { + pinctrl-single,pins = <0x190 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_31_gpio_pd_pin: pinmux_P9_31_gpio_pd_pin { + pinctrl-single,pins = <0x190 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_31_pwm_pin: pinmux_P9_31_pwm_pin { + pinctrl-single,pins = <0x190 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_31_spi_pin: pinmux_P9_31_spi_pin { + pinctrl-single,pins = <0x190 0x23>; }; /* Mode 3, Pull-Down, RxActive */ + P9_31_pruout_pin: pinmux_P9_31_pruout_pin { + pinctrl-single,pins = <0x190 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_31_pruin_pin: pinmux_P9_31_pruin_pin { + pinctrl-single,pins = <0x190 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + P9_31_audio_pin: pinmux_P9_31_audio_pin { + pinctrl-single,pins = <0x190 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)>; }; /* mcasp0_aclkx.mcasp0_aclkx */ + + /* P9_32 VADC */ + /* P9_33 (ZCZ ball C8 ) AIN4 */ + /* P9_34 AGND */ + /* P9_35 (ZCZ ball A8 ) AIN6 */ + /* P9_36 (ZCZ ball B8 ) AIN5 */ + /* P9_37 (ZCZ ball B7 ) AIN2 */ + /* P9_38 (ZCZ ball A7 ) AIN3 */ + /* P9_39 (ZCZ ball B6 ) AIN0 */ + /* P9_40 (ZCZ ball C7 ) AIN1 */ + + /* P9_41 (ZCZ ball D14) */ + P9_41_default_pin: pinmux_P9_41_default_pin { + pinctrl-single,pins = <0x1b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_41_gpio_pin: pinmux_P9_41_gpio_pin { + pinctrl-single,pins = <0x1b4 0x2F>; }; /* Mode 7, RxActive */ + P9_41_gpio_pu_pin: pinmux_P9_41_gpio_pu_pin { + pinctrl-single,pins = <0x1b4 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_41_gpio_pd_pin: pinmux_P9_41_gpio_pd_pin { + pinctrl-single,pins = <0x1b4 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_41_timer_pin: pinmux_P9_41_timer_pin { + pinctrl-single,pins = <0x1b4 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + P9_41_pruin_pin: pinmux_P9_41_pruin_pin { + pinctrl-single,pins = <0x1b4 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + + /* P9_41.1 */ + /* P9_91 (ZCZ ball D13) */ + P9_91_default_pin: pinmux_P9_91_default_pin { + pinctrl-single,pins = <0x1a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_91_gpio_pin: pinmux_P9_91_gpio_pin { + pinctrl-single,pins = <0x1a8 0x2F>; }; /* Mode 7, RxActive */ + P9_91_gpio_pu_pin: pinmux_P9_91_gpio_pu_pin { + pinctrl-single,pins = <0x1a8 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_91_gpio_pd_pin: pinmux_P9_91_gpio_pd_pin { + pinctrl-single,pins = <0x1a8 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_91_qep_pin: pinmux_P9_91_qep_pin { + pinctrl-single,pins = <0x1a8 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_91_pruout_pin: pinmux_P9_91_pruout_pin { + pinctrl-single,pins = <0x1a8 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_91_pruin_pin: pinmux_P9_91_pruin_pin { + pinctrl-single,pins = <0x1a8 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_42 (ZCZ ball C18) */ + P9_42_default_pin: pinmux_P9_42_default_pin { + pinctrl-single,pins = <0x164 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_42_gpio_pin: pinmux_P9_42_gpio_pin { + pinctrl-single,pins = <0x164 0x2F>; }; /* Mode 7, RxActive */ + P9_42_gpio_pu_pin: pinmux_P9_42_gpio_pu_pin { + pinctrl-single,pins = <0x164 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_42_gpio_pd_pin: pinmux_P9_42_gpio_pd_pin { + pinctrl-single,pins = <0x164 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_42_pwm_pin: pinmux_P9_42_pwm_pin { + pinctrl-single,pins = <0x164 0x20>; }; /* Mode 0, Pull-Down, RxActive */ + P9_42_uart_pin: pinmux_P9_42_uart_pin { + pinctrl-single,pins = <0x164 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_42_spics_pin: pinmux_P9_42_spics_pin { + pinctrl-single,pins = <0x164 0x22>; }; /* Mode 2, Pull-Down, RxActive */ + P9_42_spiclk_pin: pinmux_P9_42_spiclk_pin { + pinctrl-single,pins = <0x164 0x24>; }; /* Mode 4, Pull-Down, RxActive */ + + /* P9_42.1 */ + /* P9_92 (ZCZ ball B12) */ + P9_92_default_pin: pinmux_P9_92_default_pin { + pinctrl-single,pins = <0x1a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_92_gpio_pin: pinmux_P9_92_gpio_pin { + pinctrl-single,pins = <0x1a0 0x2F>; }; /* Mode 7, RxActive */ + P9_92_gpio_pu_pin: pinmux_P9_92_gpio_pu_pin { + pinctrl-single,pins = <0x1a0 0x37>; }; /* Mode 7, Pull-Up, RxActive */ + P9_92_gpio_pd_pin: pinmux_P9_92_gpio_pd_pin { + pinctrl-single,pins = <0x1a0 0x27>; }; /* Mode 7, Pull-Down, RxActive */ + P9_92_qep_pin: pinmux_P9_92_qep_pin { + pinctrl-single,pins = <0x1a0 0x21>; }; /* Mode 1, Pull-Down, RxActive */ + P9_92_pruout_pin: pinmux_P9_92_pruout_pin { + pinctrl-single,pins = <0x1a0 0x25>; }; /* Mode 5, Pull-Down, RxActive */ + P9_92_pruin_pin: pinmux_P9_92_pruin_pin { + pinctrl-single,pins = <0x1a0 0x26>; }; /* Mode 6, Pull-Down, RxActive */ + + /* P9_43 GND */ + /* P9_44 GND */ + /* P9_45 GND */ + /* P9_46 GND */ +}; + +/**********************************************************************/ +/* Pin Multiplex Helpers */ +/* */ +/* These provide userspace runtime pin configuration for the */ +/* BeagleBone cape expansion headers */ +/**********************************************************************/ + +&ocp { + /************************/ + /* P8 Header */ + /************************/ + + P8_07_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; + pinctrl-0 = <&P8_07_default_pin>; + pinctrl-1 = <&P8_07_gpio_pin>; + pinctrl-2 = <&P8_07_gpio_pu_pin>; + pinctrl-3 = <&P8_07_gpio_pd_pin>; + pinctrl-4 = <&P8_07_timer_pin>; + }; + + P8_08_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; + pinctrl-0 = <&P8_08_default_pin>; + pinctrl-1 = <&P8_08_gpio_pin>; + pinctrl-2 = <&P8_08_gpio_pu_pin>; + pinctrl-3 = <&P8_08_gpio_pd_pin>; + pinctrl-4 = <&P8_08_timer_pin>; + }; + + P8_09_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; + pinctrl-0 = <&P8_09_default_pin>; + pinctrl-1 = <&P8_09_gpio_pin>; + pinctrl-2 = <&P8_09_gpio_pu_pin>; + pinctrl-3 = <&P8_09_gpio_pd_pin>; + pinctrl-4 = <&P8_09_timer_pin>; + }; + + P8_10_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer"; + pinctrl-0 = <&P8_10_default_pin>; + pinctrl-1 = <&P8_10_gpio_pin>; + pinctrl-2 = <&P8_10_gpio_pu_pin>; + pinctrl-3 = <&P8_10_gpio_pd_pin>; + pinctrl-4 = <&P8_10_timer_pin>; + }; + + P8_11_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "qep"; + pinctrl-0 = <&P8_11_default_pin>; + pinctrl-1 = <&P8_11_gpio_pin>; + pinctrl-2 = <&P8_11_gpio_pu_pin>; + pinctrl-3 = <&P8_11_gpio_pd_pin>; + pinctrl-4 = <&P8_11_pruout_pin>; + pinctrl-5 = <&P8_11_qep_pin>; + }; + + P8_12_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "qep"; + pinctrl-0 = <&P8_12_default_pin>; + pinctrl-1 = <&P8_12_gpio_pin>; + pinctrl-2 = <&P8_12_gpio_pu_pin>; + pinctrl-3 = <&P8_12_gpio_pd_pin>; + pinctrl-4 = <&P8_12_pruout_pin>; + pinctrl-5 = <&P8_12_qep_pin>; + }; + + P8_13_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P8_13_default_pin>; + pinctrl-1 = <&P8_13_gpio_pin>; + pinctrl-2 = <&P8_13_gpio_pu_pin>; + pinctrl-3 = <&P8_13_gpio_pd_pin>; + pinctrl-4 = <&P8_13_pwm_pin>; + }; + + P8_14_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P8_14_default_pin>; + pinctrl-1 = <&P8_14_gpio_pin>; + pinctrl-2 = <&P8_14_gpio_pu_pin>; + pinctrl-3 = <&P8_14_gpio_pd_pin>; + pinctrl-4 = <&P8_14_pwm_pin>; + }; + + P8_15_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruin", "qep"; + pinctrl-0 = <&P8_15_default_pin>; + pinctrl-1 = <&P8_15_gpio_pin>; + pinctrl-2 = <&P8_15_gpio_pu_pin>; + pinctrl-3 = <&P8_15_gpio_pd_pin>; + pinctrl-4 = <&P8_15_pruin_pin>; + pinctrl-5 = <&P8_15_qep_pin>; + }; + + P8_16_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruin", "qep"; + pinctrl-0 = <&P8_16_default_pin>; + pinctrl-1 = <&P8_16_gpio_pin>; + pinctrl-2 = <&P8_16_gpio_pu_pin>; + pinctrl-3 = <&P8_16_gpio_pd_pin>; + pinctrl-4 = <&P8_16_pruin_pin>; + pinctrl-5 = <&P8_16_qep_pin>; + }; + + P8_17_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P8_17_default_pin>; + pinctrl-1 = <&P8_17_gpio_pin>; + pinctrl-2 = <&P8_17_gpio_pu_pin>; + pinctrl-3 = <&P8_17_gpio_pd_pin>; + pinctrl-4 = <&P8_17_pwm_pin>; + }; + + P8_18_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&P8_18_default_pin>; + pinctrl-1 = <&P8_18_gpio_pin>; + pinctrl-2 = <&P8_18_gpio_pu_pin>; + pinctrl-3 = <&P8_18_gpio_pd_pin>; + }; + + P8_19_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P8_19_default_pin>; + pinctrl-1 = <&P8_19_gpio_pin>; + pinctrl-2 = <&P8_19_gpio_pu_pin>; + pinctrl-3 = <&P8_19_gpio_pd_pin>; + pinctrl-4 = <&P8_19_pwm_pin>; + }; + + P8_26_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&P8_26_default_pin>; + pinctrl-1 = <&P8_26_gpio_pin>; + pinctrl-2 = <&P8_26_gpio_pu_pin>; + pinctrl-3 = <&P8_26_gpio_pd_pin>; + }; + + P8_27_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_27_default_pin>; + pinctrl-1 = <&P8_27_gpio_pin>; + pinctrl-2 = <&P8_27_gpio_pu_pin>; + pinctrl-3 = <&P8_27_gpio_pd_pin>; + pinctrl-4 = <&P8_27_pruout_pin>; + pinctrl-5 = <&P8_27_pruin_pin>; + pinctrl-6 = <&P8_27_hdmi_pin>; + }; + + P8_28_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_28_default_pin>; + pinctrl-1 = <&P8_28_gpio_pin>; + pinctrl-2 = <&P8_28_gpio_pu_pin>; + pinctrl-3 = <&P8_28_gpio_pd_pin>; + pinctrl-4 = <&P8_28_pruout_pin>; + pinctrl-5 = <&P8_28_pruin_pin>; + pinctrl-6 = <&P8_28_hdmi_pin>; + }; + + P8_29_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_29_default_pin>; + pinctrl-1 = <&P8_29_gpio_pin>; + pinctrl-2 = <&P8_29_gpio_pu_pin>; + pinctrl-3 = <&P8_29_gpio_pd_pin>; + pinctrl-4 = <&P8_29_pruout_pin>; + pinctrl-5 = <&P8_29_pruin_pin>; + pinctrl-6 = <&P8_29_hdmi_pin>; + }; + + P8_30_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_30_default_pin>; + pinctrl-1 = <&P8_30_gpio_pin>; + pinctrl-2 = <&P8_30_gpio_pu_pin>; + pinctrl-3 = <&P8_30_gpio_pd_pin>; + pinctrl-4 = <&P8_30_pruout_pin>; + pinctrl-5 = <&P8_30_pruin_pin>; + pinctrl-6 = <&P8_30_hdmi_pin>; + }; + + P8_31_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart", "hdmi"; + pinctrl-0 = <&P8_31_default_pin>; + pinctrl-1 = <&P8_31_gpio_pin>; + pinctrl-2 = <&P8_31_gpio_pu_pin>; + pinctrl-3 = <&P8_31_gpio_pd_pin>; + pinctrl-4 = <&P8_31_uart_pin>; + pinctrl-5 = <&P8_31_hdmi_pin>; + }; + + P8_32_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi"; + pinctrl-0 = <&P8_32_default_pin>; + pinctrl-1 = <&P8_32_gpio_pin>; + pinctrl-2 = <&P8_32_gpio_pu_pin>; + pinctrl-3 = <&P8_32_gpio_pd_pin>; + pinctrl-4 = <&P8_32_hdmi_pin>; + }; + + P8_33_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi"; + pinctrl-0 = <&P8_33_default_pin>; + pinctrl-1 = <&P8_33_gpio_pin>; + pinctrl-2 = <&P8_33_gpio_pu_pin>; + pinctrl-3 = <&P8_33_gpio_pd_pin>; + pinctrl-4 = <&P8_33_hdmi_pin>; + }; + + P8_34_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","pwm", "hdmi"; + pinctrl-0 = <&P8_34_default_pin>; + pinctrl-1 = <&P8_34_gpio_pin>; + pinctrl-2 = <&P8_34_gpio_pu_pin>; + pinctrl-3 = <&P8_34_gpio_pd_pin>; + pinctrl-4 = <&P8_34_pwm_pin>; + pinctrl-5 = <&P8_34_hdmi_pin>; + }; + + P8_35_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "hdmi"; + pinctrl-0 = <&P8_35_default_pin>; + pinctrl-1 = <&P8_35_gpio_pin>; + pinctrl-2 = <&P8_35_gpio_pu_pin>; + pinctrl-3 = <&P8_35_gpio_pd_pin>; + pinctrl-4 = <&P8_35_hdmi_pin>; + }; + + P8_36_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","pwm", "hdmi"; + pinctrl-0 = <&P8_36_default_pin>; + pinctrl-1 = <&P8_36_gpio_pin>; + pinctrl-2 = <&P8_36_gpio_pu_pin>; + pinctrl-3 = <&P8_36_gpio_pd_pin>; + pinctrl-4 = <&P8_36_pwm_pin>; + pinctrl-5 = <&P8_36_hdmi_pin>; + }; + + P8_37_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart","pwm", "hdmi"; + pinctrl-0 = <&P8_37_default_pin>; + pinctrl-1 = <&P8_37_gpio_pin>; + pinctrl-2 = <&P8_37_gpio_pu_pin>; + pinctrl-3 = <&P8_37_gpio_pd_pin>; + pinctrl-4 = <&P8_37_uart_pin>; + pinctrl-5 = <&P8_37_pwm_pin>; + pinctrl-6 = <&P8_37_hdmi_pin>; + }; + + P8_38_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd","uart","pwm", "hdmi"; + pinctrl-0 = <&P8_38_default_pin>; + pinctrl-1 = <&P8_38_gpio_pin>; + pinctrl-2 = <&P8_38_gpio_pu_pin>; + pinctrl-3 = <&P8_38_gpio_pd_pin>; + pinctrl-4 = <&P8_38_uart_pin>; + pinctrl-5 = <&P8_38_pwm_pin>; + pinctrl-6 = <&P8_38_hdmi_pin>; + }; + + P8_39_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_39_default_pin>; + pinctrl-1 = <&P8_39_gpio_pin>; + pinctrl-2 = <&P8_39_gpio_pu_pin>; + pinctrl-3 = <&P8_39_gpio_pd_pin>; + pinctrl-4 = <&P8_39_pruout_pin>; + pinctrl-5 = <&P8_39_pruin_pin>; + pinctrl-6 = <&P8_39_hdmi_pin>; + }; + + P8_40_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_40_default_pin>; + pinctrl-1 = <&P8_40_gpio_pin>; + pinctrl-2 = <&P8_40_gpio_pu_pin>; + pinctrl-3 = <&P8_40_gpio_pd_pin>; + pinctrl-4 = <&P8_40_pruout_pin>; + pinctrl-5 = <&P8_40_pruin_pin>; + pinctrl-6 = <&P8_40_hdmi_pin>; + }; + + P8_41_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_41_default_pin>; + pinctrl-1 = <&P8_41_gpio_pin>; + pinctrl-2 = <&P8_41_gpio_pu_pin>; + pinctrl-3 = <&P8_41_gpio_pd_pin>; + pinctrl-4 = <&P8_41_pruout_pin>; + pinctrl-5 = <&P8_41_pruin_pin>; + pinctrl-6 = <&P8_41_hdmi_pin>; + }; + + P8_42_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin", "hdmi"; + pinctrl-0 = <&P8_42_default_pin>; + pinctrl-1 = <&P8_42_gpio_pin>; + pinctrl-2 = <&P8_42_gpio_pu_pin>; + pinctrl-3 = <&P8_42_gpio_pd_pin>; + pinctrl-4 = <&P8_42_pruout_pin>; + pinctrl-5 = <&P8_42_pruin_pin>; + pinctrl-6 = <&P8_42_hdmi_pin>; + }; + + P8_43_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm", "hdmi"; + pinctrl-0 = <&P8_43_default_pin>; + pinctrl-1 = <&P8_43_gpio_pin>; + pinctrl-2 = <&P8_43_gpio_pu_pin>; + pinctrl-3 = <&P8_43_gpio_pd_pin>; + pinctrl-4 = <&P8_43_pruout_pin>; + pinctrl-5 = <&P8_43_pruin_pin>; + pinctrl-6 = <&P8_43_pwm_pin>; + pinctrl-7 = <&P8_43_hdmi_pin>; + }; + + P8_44_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm", "hdmi"; + pinctrl-0 = <&P8_44_default_pin>; + pinctrl-1 = <&P8_44_gpio_pin>; + pinctrl-2 = <&P8_44_gpio_pu_pin>; + pinctrl-3 = <&P8_44_gpio_pd_pin>; + pinctrl-4 = <&P8_44_pruout_pin>; + pinctrl-5 = <&P8_44_pruin_pin>; + pinctrl-6 = <&P8_44_pwm_pin>; + pinctrl-7 = <&P8_44_hdmi_pin>; + }; + + P8_45_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm", "hdmi"; + pinctrl-0 = <&P8_45_default_pin>; + pinctrl-1 = <&P8_45_gpio_pin>; + pinctrl-2 = <&P8_45_gpio_pu_pin>; + pinctrl-3 = <&P8_45_gpio_pd_pin>; + pinctrl-4 = <&P8_45_pruout_pin>; + pinctrl-5 = <&P8_45_pruin_pin>; + pinctrl-6 = <&P8_45_pwm_pin>; + pinctrl-7 = <&P8_45_hdmi_pin>; + }; + + P8_46_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pruout", "pruin","pwm", "hdmi"; + pinctrl-0 = <&P8_46_default_pin>; + pinctrl-1 = <&P8_46_gpio_pin>; + pinctrl-2 = <&P8_46_gpio_pu_pin>; + pinctrl-3 = <&P8_46_gpio_pd_pin>; + pinctrl-4 = <&P8_46_pruout_pin>; + pinctrl-5 = <&P8_46_pruin_pin>; + pinctrl-6 = <&P8_46_pwm_pin>; + pinctrl-7 = <&P8_46_hdmi_pin>; + }; + + /************************/ + /* P9 Header */ + /************************/ + + P9_11_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart"; + pinctrl-0 = <&P9_11_default_pin>; + pinctrl-1 = <&P9_11_gpio_pin>; + pinctrl-2 = <&P9_11_gpio_pu_pin>; + pinctrl-3 = <&P9_11_gpio_pd_pin>; + pinctrl-4 = <&P9_11_uart_pin>; + }; + + P9_12_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&P9_12_default_pin>; + pinctrl-1 = <&P9_12_gpio_pin>; + pinctrl-2 = <&P9_12_gpio_pu_pin>; + pinctrl-3 = <&P9_12_gpio_pd_pin>; + }; + + P9_13_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart"; + pinctrl-0 = <&P9_13_default_pin>; + pinctrl-1 = <&P9_13_gpio_pin>; + pinctrl-2 = <&P9_13_gpio_pu_pin>; + pinctrl-3 = <&P9_13_gpio_pd_pin>; + pinctrl-4 = <&P9_13_uart_pin>; + }; + + P9_14_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P9_14_default_pin>; + pinctrl-1 = <&P9_14_gpio_pin>; + pinctrl-2 = <&P9_14_gpio_pu_pin>; + pinctrl-3 = <&P9_14_gpio_pd_pin>; + pinctrl-4 = <&P9_14_pwm_pin>; + }; + + P9_15_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P9_15_default_pin>; + pinctrl-1 = <&P9_15_gpio_pin>; + pinctrl-2 = <&P9_15_gpio_pu_pin>; + pinctrl-3 = <&P9_15_gpio_pd_pin>; + pinctrl-4 = <&P9_15_pwm_pin>; + }; + + P9_16_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P9_16_default_pin>; + pinctrl-1 = <&P9_16_gpio_pin>; + pinctrl-2 = <&P9_16_gpio_pu_pin>; + pinctrl-3 = <&P9_16_gpio_pd_pin>; + pinctrl-4 = <&P9_16_pwm_pin>; + }; + + P9_17_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "i2c", "pwm"; + pinctrl-0 = <&P9_17_default_pin>; + pinctrl-1 = <&P9_17_gpio_pin>; + pinctrl-2 = <&P9_17_gpio_pu_pin>; + pinctrl-3 = <&P9_17_gpio_pd_pin>; + pinctrl-4 = <&P9_17_spi_pin>; + pinctrl-5 = <&P9_17_i2c_pin>; + pinctrl-6 = <&P9_17_pwm_pin>; + }; + + P9_18_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "i2c", "pwm"; + pinctrl-0 = <&P9_18_default_pin>; + pinctrl-1 = <&P9_18_gpio_pin>; + pinctrl-2 = <&P9_18_gpio_pu_pin>; + pinctrl-3 = <&P9_18_gpio_pd_pin>; + pinctrl-4 = <&P9_18_spi_pin>; + pinctrl-5 = <&P9_18_i2c_pin>; + pinctrl-6 = <&P9_18_pwm_pin>; + }; + + P9_19_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "can", "i2c"; + pinctrl-0 = <&P9_19_default_pin>; + pinctrl-1 = <&P9_19_gpio_pin>; + pinctrl-2 = <&P9_19_gpio_pu_pin>; + pinctrl-3 = <&P9_19_gpio_pd_pin>; + pinctrl-4 = <&P9_19_can_pin>; + pinctrl-5 = <&P9_19_i2c_pin>; + }; + + P9_20_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "can", "i2c"; + pinctrl-0 = <&P9_20_default_pin>; + pinctrl-1 = <&P9_20_gpio_pin>; + pinctrl-2 = <&P9_20_gpio_pu_pin>; + pinctrl-3 = <&P9_20_gpio_pd_pin>; + pinctrl-4 = <&P9_20_can_pin>; + pinctrl-5 = <&P9_20_i2c_pin>; + }; + + P9_21_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "uart", "i2c", "pwm"; + pinctrl-0 = <&P9_21_default_pin>; + pinctrl-1 = <&P9_21_gpio_pin>; + pinctrl-2 = <&P9_21_gpio_pu_pin>; + pinctrl-3 = <&P9_21_gpio_pd_pin>; + pinctrl-4 = <&P9_21_spi_pin>; + pinctrl-5 = <&P9_21_uart_pin>; + pinctrl-6 = <&P9_21_i2c_pin>; + pinctrl-7 = <&P9_21_pwm_pin>; + }; + + P9_22_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "spi", "uart", "i2c", "pwm"; + pinctrl-0 = <&P9_22_default_pin>; + pinctrl-1 = <&P9_22_gpio_pin>; + pinctrl-2 = <&P9_22_gpio_pu_pin>; + pinctrl-3 = <&P9_22_gpio_pd_pin>; + pinctrl-4 = <&P9_22_spi_pin>; + pinctrl-5 = <&P9_22_uart_pin>; + pinctrl-6 = <&P9_22_i2c_pin>; + pinctrl-7 = <&P9_22_pwm_pin>; + }; + + P9_23_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm"; + pinctrl-0 = <&P9_23_default_pin>; + pinctrl-1 = <&P9_23_gpio_pin>; + pinctrl-2 = <&P9_23_gpio_pu_pin>; + pinctrl-3 = <&P9_23_gpio_pd_pin>; + pinctrl-4 = <&P9_23_pwm_pin>; + }; + + P9_24_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "can", "i2c", "pruin"; + pinctrl-0 = <&P9_24_default_pin>; + pinctrl-1 = <&P9_24_gpio_pin>; + pinctrl-2 = <&P9_24_gpio_pu_pin>; + pinctrl-3 = <&P9_24_gpio_pd_pin>; + pinctrl-4 = <&P9_24_uart_pin>; + pinctrl-5 = <&P9_24_can_pin>; + pinctrl-6 = <&P9_24_i2c_pin>; + pinctrl-7 = <&P9_24_pruin_pin>; + }; + + P9_25_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin", "audio"; + pinctrl-0 = <&P9_25_default_pin>; + pinctrl-1 = <&P9_25_gpio_pin>; + pinctrl-2 = <&P9_25_gpio_pu_pin>; + pinctrl-3 = <&P9_25_gpio_pd_pin>; + pinctrl-4 = <&P9_25_qep_pin>; + pinctrl-5 = <&P9_25_pruout_pin>; + pinctrl-6 = <&P9_25_pruin_pin>; + pinctrl-7 = <&P9_25_audio_pin>; + }; + + P9_26_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "uart", "can", "i2c", "pruin"; + pinctrl-0 = <&P9_26_default_pin>; + pinctrl-1 = <&P9_26_gpio_pin>; + pinctrl-2 = <&P9_26_gpio_pu_pin>; + pinctrl-3 = <&P9_26_gpio_pd_pin>; + pinctrl-4 = <&P9_26_uart_pin>; + pinctrl-5 = <&P9_26_can_pin>; + pinctrl-6 = <&P9_26_i2c_pin>; + pinctrl-7 = <&P9_26_pruin_pin>; + }; + + P9_27_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; + pinctrl-0 = <&P9_27_default_pin>; + pinctrl-1 = <&P9_27_gpio_pin>; + pinctrl-2 = <&P9_27_gpio_pu_pin>; + pinctrl-3 = <&P9_27_gpio_pd_pin>; + pinctrl-4 = <&P9_27_qep_pin>; + pinctrl-5 = <&P9_27_pruout_pin>; + pinctrl-6 = <&P9_27_pruin_pin>; + }; + + P9_28_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pwm2", "pruout", "pruin", "audio"; + pinctrl-0 = <&P9_28_default_pin>; + pinctrl-1 = <&P9_28_gpio_pin>; + pinctrl-2 = <&P9_28_gpio_pu_pin>; + pinctrl-3 = <&P9_28_gpio_pd_pin>; + pinctrl-4 = <&P9_28_pwm_pin>; + pinctrl-5 = <&P9_28_spi_pin>; + pinctrl-6 = <&P9_28_pwm2_pin>; + pinctrl-7 = <&P9_28_pruout_pin>; + pinctrl-8 = <&P9_28_pruin_pin>; + pinctrl-9 = <&P9_28_audio_pin>; + }; + + P9_29_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin", "audio"; + pinctrl-0 = <&P9_29_default_pin>; + pinctrl-1 = <&P9_29_gpio_pin>; + pinctrl-2 = <&P9_29_gpio_pu_pin>; + pinctrl-3 = <&P9_29_gpio_pd_pin>; + pinctrl-4 = <&P9_29_pwm_pin>; + pinctrl-5 = <&P9_29_spi_pin>; + pinctrl-6 = <&P9_29_pruout_pin>; + pinctrl-7 = <&P9_29_pruin_pin>; + pinctrl-8 = <&P9_29_audio_pin>; + }; + + P9_30_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin"; + pinctrl-0 = <&P9_30_default_pin>; + pinctrl-1 = <&P9_30_gpio_pin>; + pinctrl-2 = <&P9_30_gpio_pu_pin>; + pinctrl-3 = <&P9_30_gpio_pd_pin>; + pinctrl-4 = <&P9_30_pwm_pin>; + pinctrl-5 = <&P9_30_spi_pin>; + pinctrl-6 = <&P9_30_pruout_pin>; + pinctrl-7 = <&P9_30_pruin_pin>; + }; + + P9_31_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "spi", "pruout", "pruin", "audio"; + pinctrl-0 = <&P9_31_default_pin>; + pinctrl-1 = <&P9_31_gpio_pin>; + pinctrl-2 = <&P9_31_gpio_pu_pin>; + pinctrl-3 = <&P9_31_gpio_pd_pin>; + pinctrl-4 = <&P9_31_pwm_pin>; + pinctrl-5 = <&P9_31_spi_pin>; + pinctrl-6 = <&P9_31_pruout_pin>; + pinctrl-7 = <&P9_31_pruin_pin>; + pinctrl-8 = <&P9_31_audio_pin>; + }; + + P9_41_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "timer", "pruin"; + pinctrl-0 = <&P9_41_default_pin>; + pinctrl-1 = <&P9_41_gpio_pin>; + pinctrl-2 = <&P9_41_gpio_pu_pin>; + pinctrl-3 = <&P9_41_gpio_pd_pin>; + pinctrl-4 = <&P9_41_timer_pin>; + pinctrl-5 = <&P9_41_pruin_pin>; + }; + + P9_91_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; + pinctrl-0 = <&P9_91_default_pin>; + pinctrl-1 = <&P9_91_gpio_pin>; + pinctrl-2 = <&P9_91_gpio_pu_pin>; + pinctrl-3 = <&P9_91_gpio_pd_pin>; + pinctrl-4 = <&P9_91_qep_pin>; + pinctrl-5 = <&P9_91_pruout_pin>; + pinctrl-6 = <&P9_91_pruin_pin>; + }; + + P9_42_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "pwm", "uart", "spics", "spiclk"; + pinctrl-0 = <&P9_42_default_pin>; + pinctrl-1 = <&P9_42_gpio_pin>; + pinctrl-2 = <&P9_42_gpio_pu_pin>; + pinctrl-3 = <&P9_42_gpio_pd_pin>; + pinctrl-4 = <&P9_42_pwm_pin>; + pinctrl-5 = <&P9_42_uart_pin>; + pinctrl-6 = <&P9_42_spics_pin>; + pinctrl-7 = <&P9_42_spiclk_pin>; + }; + + P9_92_pinmux { + compatible = "bone-pinmux-helper"; + status = "okay"; + pinctrl-names = "default", "gpio", "gpio_pu", "gpio_pd", "qep", "pruout", "pruin"; + pinctrl-0 = <&P9_92_default_pin>; + pinctrl-1 = <&P9_92_gpio_pin>; + pinctrl-2 = <&P9_92_gpio_pu_pin>; + pinctrl-3 = <&P9_92_gpio_pd_pin>; + pinctrl-4 = <&P9_92_qep_pin>; + pinctrl-5 = <&P9_92_pruout_pin>; + pinctrl-6 = <&P9_92_pruin_pin>; + }; + + cape-universal { + compatible = "gpio-of-helper"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <>; + + P8_07 { + gpio-name = "P8_07"; + gpio = <&gpio2 2 0>; + input; + dir-changeable; + }; + P8_08 { + gpio-name = "P8_08"; + gpio = <&gpio2 3 0>; + input; + dir-changeable; + }; + P8_09 { + gpio-name = "P8_09"; + gpio = <&gpio2 5 0>; + input; + dir-changeable; + }; + P8_10 { + gpio-name = "P8_10"; + gpio = <&gpio2 4 0>; + input; + dir-changeable; + }; + P8_11 { + gpio-name = "P8_11"; + gpio = <&gpio1 13 0>; + input; + dir-changeable; + }; + P8_12 { + gpio-name = "P8_12"; + gpio = <&gpio1 12 0>; + input; + dir-changeable; + }; + P8_13 { + gpio-name = "P8_13"; + gpio = <&gpio0 23 0>; + input; + dir-changeable; + }; + P8_14 { + gpio-name = "P8_14"; + gpio = <&gpio0 26 0>; + input; + dir-changeable; + }; + P8_15 { + gpio-name = "P8_15"; + gpio = <&gpio1 15 0>; + input; + dir-changeable; + }; + P8_16 { + gpio-name = "P8_16"; + gpio = <&gpio1 14 0>; + input; + dir-changeable; + }; + P8_17 { + gpio-name = "P8_17"; + gpio = <&gpio0 27 0>; + input; + dir-changeable; + }; + P8_18 { + gpio-name = "P8_18"; + gpio = <&gpio2 1 0>; + input; + dir-changeable; + }; + P8_19 { + gpio-name = "P8_19"; + gpio = <&gpio0 22 0>; + input; + dir-changeable; + }; + + P8_26 { + gpio-name = "P8_26"; + gpio = <&gpio1 29 0>; + input; + dir-changeable; + }; + P8_27 { + gpio-name = "P8_27"; + gpio = <&gpio2 22 0>; + input; + dir-changeable; + }; + P8_28 { + gpio-name = "P8_28"; + gpio = <&gpio2 24 0>; + input; + dir-changeable; + }; + P8_29 { + gpio-name = "P8_29"; + gpio = <&gpio2 23 0>; + input; + dir-changeable; + }; + P8_30 { + gpio-name = "P8_30"; + gpio = <&gpio2 25 0>; + input; + dir-changeable; + }; + P8_31 { + gpio-name = "P8_31"; + gpio = <&gpio0 10 0>; + input; + dir-changeable; + }; + P8_32 { + gpio-name = "P8_32"; + gpio = <&gpio0 11 0>; + input; + dir-changeable; + }; + P8_33 { + gpio-name = "P8_33"; + gpio = <&gpio0 9 0>; + input; + dir-changeable; + }; + P8_34 { + gpio-name = "P8_34"; + gpio = <&gpio2 17 0>; + input; + dir-changeable; + }; + P8_35 { + gpio-name = "P8_35"; + gpio = <&gpio0 8 0>; + input; + dir-changeable; + }; + P8_36 { + gpio-name = "P8_36"; + gpio = <&gpio2 16 0>; + input; + dir-changeable; + }; + P8_37 { + gpio-name = "P8_37"; + gpio = <&gpio2 14 0>; + input; + dir-changeable; + }; + P8_38 { + gpio-name = "P8_38"; + gpio = <&gpio2 15 0>; + input; + dir-changeable; + }; + P8_39 { + gpio-name = "P8_39"; + gpio = <&gpio2 12 0>; + input; + dir-changeable; + }; + P8_40 { + gpio-name = "P8_40"; + gpio = <&gpio2 13 0>; + input; + dir-changeable; + }; + P8_41 { + gpio-name = "P8_41"; + gpio = <&gpio2 10 0>; + input; + dir-changeable; + }; + P8_42 { + gpio-name = "P8_42"; + gpio = <&gpio2 11 0>; + input; + dir-changeable; + }; + P8_43 { + gpio-name = "P8_43"; + gpio = <&gpio2 8 0>; + input; + dir-changeable; + }; + P8_44 { + gpio-name = "P8_44"; + gpio = <&gpio2 9 0>; + input; + dir-changeable; + }; + P8_45 { + gpio-name = "P8_45"; + gpio = <&gpio2 6 0>; + input; + dir-changeable; + }; + P8_46 { + gpio-name = "P8_46"; + gpio = <&gpio2 7 0>; + input; + dir-changeable; + }; + + + P9_11 { + gpio-name = "P9_11"; + gpio = <&gpio0 30 0>; + input; + dir-changeable; + }; + P9_12 { + gpio-name = "P9_12"; + gpio = <&gpio1 28 0>; + input; + dir-changeable; + }; + P9_13 { + gpio-name = "P9_13"; + gpio = <&gpio0 31 0>; + input; + dir-changeable; + }; + P9_14 { + gpio-name = "P9_14"; + gpio = <&gpio1 18 0>; + input; + dir-changeable; + }; + P9_15 { + gpio-name = "P9_15"; + gpio = <&gpio1 16 0>; + input; + dir-changeable; + }; + P9_16 { + gpio-name = "P9_16"; + gpio = <&gpio1 19 0>; + input; + dir-changeable; + }; + P9_17 { + gpio-name = "P9_17"; + gpio = <&gpio0 5 0>; + input; + dir-changeable; + }; + P9_18 { + gpio-name = "P9_18"; + gpio = <&gpio0 4 0>; + input; + dir-changeable; + }; + P9_19 { + gpio-name = "P9_19"; + gpio = <&gpio0 13 0>; + input; + dir-changeable; + }; + P9_20 { + gpio-name = "P9_20"; + gpio = <&gpio0 12 0>; + input; + dir-changeable; + }; + P9_21 { + gpio-name = "P9_21"; + gpio = <&gpio0 3 0>; + input; + dir-changeable; + }; + P9_22 { + gpio-name = "P9_22"; + gpio = <&gpio0 2 0>; + input; + dir-changeable; + }; + P9_23 { + gpio-name = "P9_23"; + gpio = <&gpio1 17 0>; + input; + dir-changeable; + }; + P9_24 { + gpio-name = "P9_24"; + gpio = <&gpio0 15 0>; + input; + dir-changeable; + }; + P9_25 { + gpio-name = "P9_25"; + gpio = <&gpio3 21 0>; + input; + dir-changeable; + }; + P9_26 { + gpio-name = "P9_26"; + gpio = <&gpio0 14 0>; + input; + dir-changeable; + }; + P9_27 { + gpio-name = "P9_27"; + gpio = <&gpio3 19 0>; + input; + dir-changeable; + }; + P9_28 { + gpio-name = "P9_28"; + gpio = <&gpio3 17 0>; + input; + dir-changeable; + }; + P9_29 { + gpio-name = "P9_29"; + gpio = <&gpio3 15 0>; + input; + dir-changeable; + }; + P9_30 { + gpio-name = "P9_30"; + gpio = <&gpio3 16 0>; + input; + dir-changeable; + }; + P9_31 { + gpio-name = "P9_31"; + gpio = <&gpio3 14 0>; + input; + dir-changeable; + }; + P9_41 { + gpio-name = "P9_41"; + gpio = <&gpio0 20 0>; + input; + dir-changeable; + }; + P9_91 { + gpio-name = "P9_91"; + gpio = <&gpio3 20 0>; + input; + dir-changeable; + }; + P9_42 { + gpio-name = "P9_42"; + gpio = <&gpio0 7 0>; + input; + dir-changeable; + }; + P9_92 { + gpio-name = "P9_92"; + gpio = <&gpio3 18 0>; + input; + dir-changeable; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts --- a/arch/arm/boot/dts/am335x-bone.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-bone.dts 2016-05-11 13:31:53.189225170 -0400 @@ -9,6 +9,7 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" / { model = "TI AM335x BeagleBone"; @@ -24,3 +25,7 @@ &mmc1 { vmmc-supply = <&ldo3_reg>; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-emmc-in-reset.dtsi b/arch/arm/boot/dts/am335x-bone-emmc-in-reset.dtsi --- a/arch/arm/boot/dts/am335x-bone-emmc-in-reset.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-emmc-in-reset.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* standard */ + +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bonegreen.dts b/arch/arm/boot/dts/am335x-bonegreen.dts --- a/arch/arm/boot/dts/am335x-bonegreen.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-bonegreen.dts 2016-05-11 13:31:53.189225170 -0400 @@ -8,7 +8,9 @@ /dts-v1/; #include "am33xx.dtsi" +#include "am33xx-es2.dtsi" #include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" / { model = "TI AM335x BeagleBone Green"; @@ -33,21 +35,6 @@ status = "okay"; }; -&am33xx_pinmux { - uart2_pins: uart2_pins { - pinctrl-single,pins = < - 0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */ - 0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */ - >; - }; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; +&sgx { status = "okay"; }; - -&rtc { - system-power-controller; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bonegreen-overlay.dts b/arch/arm/boot/dts/am335x-bonegreen-overlay.dts --- a/arch/arm/boot/dts/am335x-bonegreen-overlay.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bonegreen-overlay.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" + +/ { + model = "TI AM335x BeagleBone Green"; + compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&sgx { + status = "okay"; +}; + +/* EMMC in reset */ +&gpio1 { + emmc_rst { + gpio-hog; + gpios = <20 0>; + output-high; + line-name = "EMMC ResetN"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts --- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-bonegreen-wl1835.dtsi" + +/ { + model = "TI AM335x BeagleBone Green Wireless"; + compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; +}; + +&sgx { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&mmc3 { + status = "okay"; +}; + +&mac { + status = "disabled"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bonegreen-wl1835.dtsi b/arch/arm/boot/dts/am335x-bonegreen-wl1835.dtsi --- a/arch/arm/boot/dts/am335x-bonegreen-wl1835.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bonegreen-wl1835.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,173 @@ + +#include + +/ { + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* WL_EN */ + gpio = <&gpio0 26 0>; + enable-active-high; + }; + + tibt { + compatible = "tibt"; + nshutdown_gpio = <60>; + dev_name = "/dev/ttyS3"; + flow_cntrl = <1>; + baud_rate = <3000000>; + }; + + btwilink { + compatible = "btwilink"; + }; + + wilink8_pcm: wilink8_pcm { + compatible = "ti,wilink8_bt"; + status = "okay"; + }; + + sound{ + compatible = "ti,wilink8-bt-audio"; + ti,model = "WILINK8_BT"; + ti,audio-codec = <&wilink8_pcm>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <24000000>; + }; +}; + +&am33xx_pinmux { + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + 0x78 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad12.gpio1_28 BT_EN*/ + >; + }; + + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + 0x8c ( PIN_INPUT_PULLUP | MUX_MODE3 ) /* gpio2_1 gpmc_clk.mmc2_clk */ + 0x88 ( PIN_INPUT_PULLUP | MUX_MODE3) /* gpio2_0 gpmc_csn3.mmc2_cmd */ + 0x30 ( PIN_INPUT_PULLUP | MUX_MODE3 ) /* gpio1_12 gpmc_ad12.mmc2_dat0 */ + 0x34 ( PIN_INPUT_PULLUP | MUX_MODE3 ) /* gpio1_13 gpmc_ad13.mmc2_dat1 */ + 0x38 ( PIN_INPUT_PULLUP | MUX_MODE3 ) /* gpio1_14 gpmc_ad14.mmc2_dat2 */ + 0x3c ( PIN_INPUT_PULLUP | MUX_MODE3 ) /* gpio1_15 gpmc_ad15.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + pinctrl-single,pins = < + 0x8c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio2_1 gpmc_clk.mmc2_clk */ + 0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio2_0 gpmc_csn3.mmc2_cmd */ + 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1_12 gpmc_ad12.mmc2_dat0 */ + 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1_13 gpmc_ad13.mmc2_dat1 */ + 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1_14 gpmc_ad14.mmc2_dat2 */ + 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpio1_15 gpmc_ad15.mmc2_dat3 */ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x28 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN*/ + 0x2C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ*/ + 0x7C (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpio1_29 Cape_Buffer_EN*/ + >; + }; + + /* wl18xx card enable/irq GPIOs. */ + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x28 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_ad10.gpio0_26 WL_EN*/ + 0x2C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ad11.gpio0_27 WL_IRQ*/ + 0x7C (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpio1_29 Cape_Buffer_EN*/ + >; + }; + + uart3_pins_default: pinmux_uart3_pins_default { + pinctrl-single,pins = < + 0x134 ( PIN_INPUT_PULLUP | MUX_MODE1 ) /* (L17) gmii1_rxd3.uart3_rxd */ + 0x138 ( PIN_OUTPUT_PULLDOWN | MUX_MODE1 ) /* (L16) gmii1_rxd2.uart3_txd */ + 0x148 ( PIN_INPUT | MUX_MODE3 ) /* (M17) mdio_data.uart3_ctsn */ + 0x14c ( PIN_OUTPUT_PULLDOWN | MUX_MODE3 ) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + uart3_pins_sleep: pinmux_uart3_pins_sleep { + pinctrl-single,pins = < + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L17) gmii1_rxd3.uart3_rxd */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L16) gmii1_rxd2.uart3_txd */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M17) mdio_data.uart3_ctsn */ + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M18) mdio_clk.uart3_rtsn */ + >; + }; + + bt_audio_pins: bt_audio_pins { + pinctrl-single,pins = < + 0x190 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx - COM_AUD_CLK */ + 0x194 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx - COM_AUD_FSYNC */ + 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0 - COM_AUD_IN */ + 0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* MCASP0_AHCLKR -> MCASP0_AXR2 (I2S_DATA_OUT) -out */ + >; + }; + + bt_audio_pins_sleep: audio_pins_sleep { + pinctrl-single,pins = < + 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x19c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins &wlan_pins>; + pinctrl-1 = <&mmc3_pins_sleep &wlan_pins_sleep>; + ti,non-removable; + ti,needs-special-hs-handling; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart3_pins_default>; + pinctrl-1 = <&uart3_pins_sleep>; + status = "okay"; +}; + +&mcasp0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&bt_audio_pins>; + pinctrl-1 = <&bt_audio_pins_sleep>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <5>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-jtag.dtsi b/arch/arm/boot/dts/am335x-bone-jtag.dtsi --- a/arch/arm/boot/dts/am335x-bone-jtag.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-jtag.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,20 @@ +/* + * Device Tree Source for bone jtag + * + * Copyright (C) 2015 Robert Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ + >; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-can0.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-can0.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-can0.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-can0.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "am335x-peripheral-can0.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_19_pinmux { + * mode = "can"; + * }; + * P9_20_pinmux { + * mode = "can"; + * }; + *}; + * + *&dcan0 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + /* P9_20: uart1_ctsn.d_can0_tx */ + BONE_P9_20 (PIN_OUTPUT_PULLUP | MUX_MODE2) + /* P9_19: uart1_rtsn.d_can0_rx */ + BONE_P9_19 (PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; +}; + +&dcan0 { + pinctrl-0 = <&dcan0_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-can1.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-can1.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-can1.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-can1.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "am335x-peripheral-can1.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_24_pinmux { + * mode = "can"; + * }; + * P9_26_pinmux { + * mode = "can"; + * }; + *}; + * + *&dcan1 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + /* P9_26: uart1_rxd.d_can1_tx */ + BONE_P9_26 (PIN_OUTPUT_PULLUP | MUX_MODE2) + /* P9_24: uart1_txd.d_can1_rx */ + BONE_P9_24 (PIN_INPUT_PULLUP | MUX_MODE2) + >; + }; +}; + +&dcan1 { + pinctrl-0 = <&dcan1_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-emmc.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-emmc.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-emmc.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-emmc.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Testing */ +/* lsblk */ + +#include +#include "am335x-peripheral-emmc.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P8_21_pinmux { + * state = "disabled"; + * }; + * P8_20_pinmux { + * state = "disabled"; + * }; + * P8_25_pinmux { + * state = "disabled"; + * }; + * P8_24_pinmux { + * state = "disabled"; + * }; + * P8_05_pinmux { + * state = "disabled"; + * }; + * P8_06_pinmux { + * state = "disabled"; + * }; + * P8_23_pinmux { + * state = "disabled"; + * }; + * P8_22_pinmux { + * state = "disabled"; + * }; + * P8_03_pinmux { + * state = "disabled"; + * }; + * P8_04_pinmux { + * state = "disabled"; + * }; + *}; + * + *&mmc2 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + /* P8_21: gpmc_csn1.mmc1_clk */ + BONE_P8_21 (PIN_INPUT_PULLUP | MUX_MODE2) + /* P8_20: gpmc_csn2.mmc1_cmd */ + BONE_P8_20 (PIN_INPUT_PULLUP | MUX_MODE2) + /* P8_25: gpmc_ad0.mmc1_dat0 */ + BONE_P8_25 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_24: gpmc_ad1.mmc1_dat1 */ + BONE_P8_24 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_05: gpmc_ad2.mmc1_dat2 */ + BONE_P8_05 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_06: gpmc_ad3.mmc1_dat3 */ + BONE_P8_06 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_23: gpmc_ad4.mmc1_dat4 */ + BONE_P8_23 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_22: gpmc_ad5.mmc1_dat5 */ + BONE_P8_22 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_03: gpmc_ad6.mmc1_dat6 */ + BONE_P8_03 (PIN_INPUT_PULLUP | MUX_MODE1) + /* P8_04: gpmc_ad7.mmc1_dat7 */ + BONE_P8_04 (PIN_INPUT_PULLUP | MUX_MODE1) + >; + }; +}; + +&mmc2 { + pinctrl-0 = <&emmc_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-i2c2.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-i2c2.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-i2c2.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-i2c2.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "am335x-peripheral-i2c2.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_19_pinmux { + * mode = "i2c"; + * }; + * P9_20_pinmux { + * mode = "i2c"; + * }; + *}; + * + *&dcan0 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + /* P9_20: uart1_ctsn.i2c2_sda */ + BONE_P9_20 (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) + /* P9_19: uart1_rtsn.i2c2_scl */ + BONE_P9_19 (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) + >; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-panel-1024x600-24bit.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-panel-1024x600-24bit.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-panel-1024x600-24bit.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-panel-1024x600-24bit.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "am335x-peripheral-panel-1024x600-24bit.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P8_27_pinmux { + * state = "disabled"; + * }; + * P8_28_pinmux { + * state = "disabled"; + * }; + * P8_29_pinmux { + * state = "disabled"; + * }; + * P8_30_pinmux { + * state = "disabled"; + * }; + * P8_31_pinmux { + * state = "disabled"; + * }; + * P8_32_pinmux { + * state = "disabled"; + * }; + * P8_33_pinmux { + * state = "disabled"; + * }; + * P8_34_pinmux { + * state = "disabled"; + * }; + * P8_35_pinmux { + * state = "disabled"; + * }; + * P8_36_pinmux { + * state = "disabled"; + * }; + * P8_37_pinmux { + * state = "disabled"; + * }; + * P8_38_pinmux { + * state = "disabled"; + * }; + * P8_39_pinmux { + * state = "disabled"; + * }; + * P8_40_pinmux { + * state = "disabled"; + * }; + * P8_41_pinmux { + * state = "disabled"; + * }; + * P8_42_pinmux { + * state = "disabled"; + * }; + * P8_43_pinmux { + * state = "disabled"; + * }; + * P8_44_pinmux { + * state = "disabled"; + * }; + * P8_45_pinmux { + * state = "disabled"; + * }; + * P8_46_pinmux { + * state = "disabled"; + * }; + *}; + */ + +/* standard */ + +&am33xx_pinmux { + lcd_24bit_pins: pinmux_lcd_24bit_pins { + pinctrl-single,pins = < + + /* P8_45: lcd_data0.lcd_data0 */ + BONE_P8_45 (PIN_OUTPUT | MUX_MODE0) + /* P8_46: lcd_data1.lcd_data1 */ + BONE_P8_46 (PIN_OUTPUT | MUX_MODE0) + /* P8_43: lcd_data2.lcd_data2 */ + BONE_P8_43 (PIN_OUTPUT | MUX_MODE0) + /* P8_44: lcd_data3.lcd_data3 */ + BONE_P8_44 (PIN_OUTPUT | MUX_MODE0) + /* P8_41: lcd_data4.lcd_data4 */ + BONE_P8_41 (PIN_OUTPUT | MUX_MODE0) + /* P8_42: lcd_data5.lcd_data5 */ + BONE_P8_42 (PIN_OUTPUT | MUX_MODE0) + /* P8_39: lcd_data6.lcd_data6 */ + BONE_P8_39 (PIN_OUTPUT | MUX_MODE0) + /* P8_40: lcd_data7.lcd_data7 */ + BONE_P8_40 (PIN_OUTPUT | MUX_MODE0) + /* P8_37: lcd_data8.lcd_data8 */ + BONE_P8_37 (PIN_OUTPUT | MUX_MODE0) + /* P8_38: lcd_data9.lcd_data9 */ + BONE_P8_38 (PIN_OUTPUT | MUX_MODE0) + /* P8_36: lcd_data10.lcd_data10 */ + BONE_P8_36 (PIN_OUTPUT | MUX_MODE0) + /* P8_34: lcd_data11.lcd_data11 */ + BONE_P8_34 (PIN_OUTPUT | MUX_MODE0) + /* P8_35: lcd_data12.lcd_data12 */ + BONE_P8_35 (PIN_OUTPUT | MUX_MODE0) + /* P8_33: lcd_data13.lcd_data13 */ + BONE_P8_33 (PIN_OUTPUT | MUX_MODE0) + /* P8_31: lcd_data14.lcd_data14 */ + BONE_P8_31 (PIN_OUTPUT | MUX_MODE0) + /* P8_32: lcd_data15.lcd_data15 */ + BONE_P8_32 (PIN_OUTPUT | MUX_MODE0) + + /* gpmc_ad15.lcd_data16 */ + BONE_P8_15 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad14.lcd_data17 */ + BONE_P8_16 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad13.lcd_data18 */ + BONE_P8_11 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad12.lcd_data19 */ + BONE_P8_12 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad11.lcd_data20 */ + BONE_P8_17 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad10.lcd_data21 */ + BONE_P8_14 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad9.lcd_data22 */ + BONE_P8_13 (PIN_OUTPUT | MUX_MODE1) + /* gpmc_ad8.lcd_data23 */ + BONE_P8_19 (PIN_OUTPUT | MUX_MODE1) + + /* P8_27: lcd_vsync.lcd_vsync */ + BONE_P8_27 (PIN_OUTPUT | MUX_MODE0) + /* P8_29: lcd_hsync.lcd_hsync */ + BONE_P8_29 (PIN_OUTPUT | MUX_MODE0) + /* P8_28: lcd_pclk.lcd_pclk*/ + BONE_P8_28 (PIN_OUTPUT | MUX_MODE0) + /* P8_30: lcd_ac_bias_en.lcd_ac_bias_en */ + BONE_P8_30 (PIN_OUTPUT | MUX_MODE0) + >; + }; +}; + +/ { + panel { + pinctrl-0 = <&lcd_24bit_pins>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS1.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS1.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS1.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS1.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Testing */ +/* sudo /sbin/getty -L ttyS1 115200 vt102 */ + +#include +#include "am335x-peripheral-ttyS1.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_24_pinmux { + * mode = "uart"; + * }; + * P9_26_pinmux { + * mode = "uart"; + * }; + *}; + * + *&uart1 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* P9_24: uart1_txd.uart1_txd */ + BONE_P9_24 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) + /* P9_26: uart1_rxd.uart1_rxd */ + BONE_P9_26 (PIN_INPUT_PULLUP | MUX_MODE0) + >; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS2.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS2.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS2.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS2.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Testing */ +/* sudo /sbin/getty -L ttyS2 115200 vt102 */ + +#include +#include "am335x-peripheral-ttyS2.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_21_pinmux { + * mode = "uart"; + * }; + * P9_22_pinmux { + * mode = "uart"; + * }; + *}; + * + *&uart2 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + /* P9_21: spi0_d0.uart2_txd */ + BONE_P9_21 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) + /* P9_22: spi0_sclk.uart2_rxd */ + BONE_P9_22 (PIN_INPUT_PULLUP | MUX_MODE1) + >; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS4.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS4.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS4.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS4.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Testing */ +/* sudo /sbin/getty -L ttyS4 115200 vt102 */ + +#include +#include "am335x-peripheral-ttyS4.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P9_11_pinmux { + * mode = "uart"; + * }; + * P9_13_pinmux { + * mode = "uart"; + * }; + *}; + * + *&uart4 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + /* P9_11: gpmc_wait0.uart4_rxd_mux2 */ + BONE_P9_11 (PIN_INPUT_PULLUP | MUX_MODE6) + /* P9_13: gpmc_wpn.uart4_txd_mux2 */ + BONE_P9_13 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) + >; + }; +}; + +&uart4 { + pinctrl-0 = <&uart4_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS5.dtsi b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS5.dtsi --- a/arch/arm/boot/dts/am335x-bone-pinmux-ttyS5.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-bone-pinmux-ttyS5.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* Testing */ +/* sudo /sbin/getty -L ttyS5 115200 vt102 */ + +#include +#include "am335x-peripheral-ttyS5.dtsi" + +/* cape universal */ + +/* + *&ocp { + * P8_37_pinmux { + * mode = "uart"; + * }; + * P8_38_pinmux { + * mode = "uart"; + * }; + *}; + * + *&uart5 { + * pinctrl-0 = <>; + *}; + * + */ + +/* standard */ + +&am33xx_pinmux { + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + /* P8_38: lcd_data9.uart5_rxd */ + BONE_P8_38 (PIN_INPUT_PULLUP | MUX_MODE4) + /* P8_37: lcd_data8.uart5_txd */ + BONE_P8_37 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) + >; + }; +}; + +&uart5 { + pinctrl-0 = <&uart5_pins>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-cape-bbb-exp-c.dtsi b/arch/arm/boot/dts/am335x-cape-bbb-exp-c.dtsi --- a/arch/arm/boot/dts/am335x-cape-bbb-exp-c.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-cape-bbb-exp-c.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include "am335x-peripheral-can0.dtsi" +#include "am335x-bone-pinmux-can0.dtsi" + +#include "am335x-peripheral-ttyS1.dtsi" +#include "am335x-bone-pinmux-ttyS1.dtsi" + +#include "am335x-peripheral-ttyS2.dtsi" +#include "am335x-bone-pinmux-ttyS2.dtsi" + +#include "am335x-peripheral-ttyS4.dtsi" +#include "am335x-bone-pinmux-ttyS4.dtsi" + +&am33xx_pinmux { + user_leds_s1: user_leds_s1 { + pinctrl-single,pins = < + 0x98 0x7 /* gpmc_wen.gpio2_4, OUTPUT | MODE7 */ + 0x9c 0x7 /* gpmc_ben0_cle.gpio2_5, OUTPUT | MODE7 */ + >; + }; + + bb_lcd_pwm_backlight_pins: pinmux_bb_lcd_pwm_backlight_pins { + pinctrl-single,pins = < + BONE_P9_14 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + >; + }; + + keymap3_pins: pinmux_keymap3_pins { + pinctrl-single,pins = < + 0x040 0x2f /* KEY_UP gpmc_a0.gpio1_16, INPUT | PULLDIS | MODE7 */ + 0x04c 0x2f /* KEY_DOWN gpmc_a3.gpio1_19, INPUT | PULLDIS | MODE7 */ + 0x078 0x2f /* KEY_RIGHT gpmc_ben1.gpio1_28, INPUT | PULLDIS | MODE7 */ + 0x164 0x2f /* KEY_LEFT ecap0_in_pwm0_out.gpio0_7, INPUT | PULLDIS | MODE7 */ + 0x1a4 0x2f /* KEY_ENTER mcasp0_fxr.gpio3_19, INPUT | PULLDIS | MODE7 */ + >; + }; + + edt_ft5306_ts_pins: pinmux_edt_ft5306_ts_pins { + pinctrl-single,pins = < + /* CAP_TSC gpmc_a1.gpio1_17, INPUT | MODE7 */ + BONE_P9_23 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + /* spi0_d1.i2c1_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ + BONE_P9_18 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) + /* spi0_cs0.i2c1_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ + BONE_P9_17 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) + >; + }; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,pins = < + 0x190 0x20 /* mcasp0_aclkx.mcasp0_aclkx, INPUT | MODE0 */ + 0x194 0x20 /* mcasp0_fsx.mcasp0_fsx, INPUT | MODE0 */ + 0x198 0x20 /* mcasp0_axr0.mcasp0_axr0, INPUT | MODE0 */ + 0x19c 0x22 /* mcasp0_ahclkr.mcasp0_axr2, INPUT | MODE2 */ + >; + }; +}; + +&epwmss1 { + status = "okay"; +}; + + +&ehrpwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&bb_lcd_pwm_backlight_pins>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + edt-ft5306@38 { + status = "okay"; + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + pinctrl-names = "default"; + pinctrl-0 = <&edt_ft5306_ts_pins>; + + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <17 0>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; + + tlv320aic3x: tlv320aic3x@1b { + compatible = "ti,tlv320aic3x"; + reg = <0x1b>; + status = "okay"; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + num-serializer = <16>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +/ { + backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&ehrpwm1 0 50000 0>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&keymap3_pins>; + + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + linux,code = <105>; + label = "left"; + gpios = <&gpio0 7 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@2 { + debounce_interval = <50>; + linux,code = <106>; + label = "right"; + gpios = <&gpio1 28 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@3 { + debounce_interval = <50>; + linux,code = <103>; + label = "up"; + gpios = <&gpio1 16 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@4 { + debounce_interval = <50>; + linux,code = <108>; + label = "down"; + gpios = <&gpio1 19 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@5 { + debounce_interval = <50>; + linux,code = <28>; + label = "enter"; + gpios = <&gpio3 19 0x1>; + gpio-key,wakeup; + }; + }; + + gpio-leds-cape-lcd { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pinctrl-0 = <&user_leds_s1>; + + lcd-led0 { + label = "lcd:green:usr0"; + gpios = <&gpio2 4 0>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + lcd-led1 { + label = "lcd:green:usr1"; + gpios = <&gpio2 5 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "DA830 EVM"; + ti,audio-codec = <&tlv320aic3x>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack"; + }; +}; + +#include "am335x-peripheral-panel-1024x600-24bit.dtsi" +#include "am335x-bone-pinmux-panel-1024x600-24bit.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-cape-bbb-exp-r.dtsi b/arch/arm/boot/dts/am335x-cape-bbb-exp-r.dtsi --- a/arch/arm/boot/dts/am335x-cape-bbb-exp-r.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-cape-bbb-exp-r.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#include "am335x-peripheral-can0.dtsi" +#include "am335x-bone-pinmux-can0.dtsi" + +#include "am335x-peripheral-ttyS1.dtsi" +#include "am335x-bone-pinmux-ttyS1.dtsi" + +#include "am335x-peripheral-ttyS2.dtsi" +#include "am335x-bone-pinmux-ttyS2.dtsi" + +#include "am335x-peripheral-ttyS4.dtsi" +#include "am335x-bone-pinmux-ttyS4.dtsi" + +&am33xx_pinmux { + user_leds_s1: user_leds_s1 { + pinctrl-single,pins = < + 0x98 0x7 /* gpmc_wen.gpio2_4, OUTPUT | MODE7 */ + 0x9c 0x7 /* gpmc_ben0_cle.gpio2_5, OUTPUT | MODE7 */ + >; + }; + + bb_lcd_pwm_backlight_pins: pinmux_bb_lcd_pwm_backlight_pins { + pinctrl-single,pins = < + BONE_P9_14 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_a2.ehrpwm1a */ + >; + }; + + keymap3_pins: pinmux_keymap3_pins { + pinctrl-single,pins = < + 0x040 0x2f /* KEY_UP gpmc_a0.gpio1_16, INPUT | PULLDIS | MODE7 */ + 0x04c 0x2f /* KEY_DOWN gpmc_a3.gpio1_19, INPUT | PULLDIS | MODE7 */ + 0x078 0x2f /* KEY_RIGHT gpmc_ben1.gpio1_28, INPUT | PULLDIS | MODE7 */ + 0x164 0x2f /* KEY_LEFT ecap0_in_pwm0_out.gpio0_7, INPUT | PULLDIS | MODE7 */ + 0x1a4 0x2f /* KEY_ENTER mcasp0_fxr.gpio3_19, INPUT | PULLDIS | MODE7 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + /* spi0_d1.i2c1_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ + BONE_P9_18 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) + /* spi0_cs0.i2c1_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */ + BONE_P9_17 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) + >; + }; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,pins = < + 0x190 0x20 /* mcasp0_aclkx.mcasp0_aclkx, INPUT | MODE0 */ + 0x194 0x20 /* mcasp0_fsx.mcasp0_fsx, INPUT | MODE0 */ + 0x198 0x20 /* mcasp0_axr0.mcasp0_axr0, INPUT | MODE0 */ + 0x19c 0x22 /* mcasp0_ahclkr.mcasp0_axr2, INPUT | MODE2 */ + >; + }; +}; + +&epwmss1 { + status = "okay"; +}; + + +&ehrpwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&bb_lcd_pwm_backlight_pins>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + tlv320aic3x: tlv320aic3x@1b { + compatible = "ti,tlv320aic3x"; + reg = <0x1b>; + status = "okay"; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + num-serializer = <16>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + +/ { + backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&ehrpwm1 0 50000 0>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&keymap3_pins>; + + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + linux,code = <105>; + label = "left"; + gpios = <&gpio0 7 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@2 { + debounce_interval = <50>; + linux,code = <106>; + label = "right"; + gpios = <&gpio1 28 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@3 { + debounce_interval = <50>; + linux,code = <103>; + label = "up"; + gpios = <&gpio1 16 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@4 { + debounce_interval = <50>; + linux,code = <108>; + label = "down"; + gpios = <&gpio1 19 0x1>; + gpio-key,wakeup; + autorepeat; + }; + button@5 { + debounce_interval = <50>; + linux,code = <28>; + label = "enter"; + gpios = <&gpio3 19 0x1>; + gpio-key,wakeup; + }; + }; + + gpio-leds-cape-lcd { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pinctrl-0 = <&user_leds_s1>; + + lcd-led0 { + label = "lcd:green:usr0"; + gpios = <&gpio2 4 0>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + lcd-led1 { + label = "lcd:green:usr1"; + gpios = <&gpio2 5 0>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + }; + + sound { + compatible = "ti,da830-evm-audio"; + ti,model = "DA830 EVM"; + ti,audio-codec = <&tlv320aic3x>; + ti,mcasp-controller = <&mcasp0>; + ti,codec-clock-rate = <12000000>; + ti,audio-routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack"; + }; +}; + +#include "am335x-peripheral-panel-1024x600-24bit.dtsi" +#include "am335x-bone-pinmux-panel-1024x600-24bit.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-cape-rtc-ds1307.dtsi b/arch/arm/boot/dts/am335x-cape-rtc-ds1307.dtsi --- a/arch/arm/boot/dts/am335x-cape-rtc-ds1307.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-cape-rtc-ds1307.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +&am33xx_pinmux { + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + BONE_P9_20 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_ctsn.i2c2_sda */ + BONE_P9_19 0x73 /* (SLEWCTRL_SLOW | PIN_INPUT_PULLUP | MUX_MODE3) uart1_rtsn.i2c2_scl */ + >; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <100000>; + + rtc@68 { + compatible = "maxim,ds1307"; + reg = <0x68>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi --- a/arch/arm/boot/dts/am335x-chilisom.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi 2016-05-11 13:31:53.189225170 -0400 @@ -7,6 +7,7 @@ * published by the Free Software Foundation. */ #include "am33xx.dtsi" +#include / { model = "Grinn AM335x ChiliSOM"; @@ -208,7 +209,12 @@ pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -227,12 +233,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts --- a/arch/arm/boot/dts/am335x-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-evm.dts 2016-05-11 13:31:53.189225170 -0400 @@ -519,7 +519,12 @@ pinctrl-0 = <&nandflash_pins_s0>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -538,12 +543,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ @@ -743,8 +745,8 @@ &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; @@ -766,11 +768,6 @@ }; }; -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - &sham { status = "okay"; }; @@ -784,3 +781,15 @@ pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; + +&wkup_m3_ipc { + ti,scale-data-fw = "am335x-evm-scale-data.bin"; +}; + +&rtc { + system-power-controller; +}; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts --- a/arch/arm/boot/dts/am335x-evmsk.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-evmsk.dts 2016-05-11 13:31:53.193225201 -0400 @@ -200,7 +200,13 @@ &am33xx_pinmux { pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; + pinctrl-0 = <&gpio_keys_s0 &clkout2_pin &ddr3_vtt_toggle>; + + ddr3_vtt_toggle: ddr3_vtt_toggle { + pinctrl-single,pins = < + 0x164 (PIN_OUTPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */ + >; + }; lcd_pins_default: lcd_pins_default { pinctrl-single,pins = < @@ -535,6 +541,12 @@ }; }; +&wkup_m3_ipc { + ti,needs-vtt-toggle; + ti,vtt-gpio-pin = <7>; + ti,scale-data-fw = "am335x-evm-scale-data.bin"; +}; + #include "tps65910.dtsi" &tps { @@ -713,3 +725,7 @@ &lcdc { status = "okay"; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts --- a/arch/arm/boot/dts/am335x-icev2.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-icev2.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "TI AM3359 ICE-V2"; + compatible = "ti,am3359-icev2", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Tricolor status LEDs */ + leds@1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led@0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led@1 { + label = "status0:green:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "status0:yellow:usr"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "status1:red:mmc0"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led@4 { + label = "status1:green:usr"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + user_leds: user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + >; + }; + + mmc0_pins_default: mmc0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ + >; + }; + + i2c0_pins_default: i2c0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; + + spi0_pins_default: spi0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + + status = "okay"; + clock-frequency = <400000>; + + tps: power-controller@2d { + reg = <0x2d>; + }; + + tpic2810: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <1 2 3 4 5 6 7>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1326000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; +}; + +&gpio0 { + /* Do not idle the GPIO used for holding the VTT regulator */ + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi --- a/arch/arm/boot/dts/am335x-igep0033.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -11,6 +11,7 @@ /dts-v1/; #include "am33xx.dtsi" +#include / { cpus { @@ -129,7 +130,12 @@ ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; @@ -147,12 +153,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts --- a/arch/arm/boot/dts/am335x-lxm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-lxm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -364,3 +364,6 @@ status = "okay"; }; +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts --- a/arch/arm/boot/dts/am335x-nano.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-nano.dts 2016-05-11 13:31:53.193225201 -0400 @@ -438,3 +438,7 @@ }; }; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-olimex-som.dts b/arch/arm/boot/dts/am335x-olimex-som.dts --- a/arch/arm/boot/dts/am335x-olimex-som.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-olimex-som.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-som-common.dtsi" + +/ { + model = "Olimex AM335x SOM"; + compatible = "olimex,am335x-olimex-som", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&am33xx_pinmux { + lcd_pins_default: lcd_pins_default { + pinctrl-single,pins = < + 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */ + 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */ + 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */ + 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */ + 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */ + 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */ + 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */ + 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */ + 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */ + 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */ + 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */ + 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */ + 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */ + 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */ + 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */ + 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */ + 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */ + 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */ + 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */ + 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */ + 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */ + 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */ + 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */ + 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */ + 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */ + 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */ + 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */ + 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */ + >; + }; + + lcd_pins_sleep: lcd_pins_sleep { + pinctrl-single,pins = < + 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data16 */ + 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data17 */ + 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data18 */ + 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data19 */ + 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data20 */ + 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data21 */ + 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data22 */ + 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data23 */ + 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ + 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ + 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ + 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ + 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ + 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ + 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ + 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ + 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ + 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ + 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ + 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ + 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ + 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ + 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ + 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ + /* lcd_vsync.lcd_vsync,OUTPUT | MODE0 */ + 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ + 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ + /* lcd_ac_bias_en.lcd_ac_bias_en */ + 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + +}; + +&lcdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcd_pins_default>; + pinctrl-1 = <&lcd_pins_sleep>; + status = "okay"; + /* display-timings { + 480x272 { + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; + clock-frequency = <9000000>; + hsync-active = <0>; + vsync-active = <0>; + }; + };*/ + + display-timings { + native-mode = <&vga1024x768>; + lcd4: 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <40>; + vback-porch = <8>; + vfront-porch = <7>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + }; + lcd7: 800x480 { + clock-frequency = <33300000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <40>; + vback-porch = <23>; + vfront-porch = <20>; + hsync-len = <6>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + }; + lcd10: 1024x600 { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hback-porch = <140>; + vback-porch = <20>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + }; + + vga800x600: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hfront-porch = <40>; + hback-porch = <88>; + vfront-porch = <1>; + vback-porch = <23>; + hsync-len = <128>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + }; + vga1024x768: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vactive = <768>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts --- a/arch/arm/boot/dts/am335x-pepper.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-pepper.dts 2016-05-11 13:31:53.193225201 -0400 @@ -339,13 +339,6 @@ ti,non-removable; }; -&edma { - /* Map eDMA MMC2 Events from Crossbar */ - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - - &mmc3 { /* Wifi & Bluetooth on MMC #3 */ status = "okay"; @@ -354,8 +347,8 @@ vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; ti,non-removable; - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; }; @@ -661,3 +654,7 @@ >; }; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-can0.dtsi b/arch/arm/boot/dts/am335x-peripheral-can0.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-can0.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-can0.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&dcan0 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-can1.dtsi b/arch/arm/boot/dts/am335x-peripheral-can1.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-can1.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-can1.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&dcan1 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-emmc.dtsi b/arch/arm/boot/dts/am335x-peripheral-emmc.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-emmc.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-emmc.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + + bus-width = <8>; + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-i2c2.dtsi b/arch/arm/boot/dts/am335x-peripheral-i2c2.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-i2c2.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-i2c2.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&i2c2 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-panel-1024x600-24bit.dtsi b/arch/arm/boot/dts/am335x-peripheral-panel-1024x600-24bit.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-panel-1024x600-24bit.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-panel-1024x600-24bit.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&lcdc { + status = "okay"; +}; + +/ { + panel { + status = "okay"; + compatible = "ti,tilcdc,panel"; + pinctrl-names = "default"; + + panel-info { + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <0>; + raster-order = <1>; + fifo-th = <0>; + }; + display-timings { + native-mode = <&timing0>; + timing0: 1024x600 { + clock-frequency = <36000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <1>; + hback-porch = <45>; + hsync-len = <30>; + vback-porch = <22>; + vfront-porch = <12>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-ttyS1.dtsi b/arch/arm/boot/dts/am335x-peripheral-ttyS1.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-ttyS1.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-ttyS1.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&uart1 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-ttyS2.dtsi b/arch/arm/boot/dts/am335x-peripheral-ttyS2.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-ttyS2.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-ttyS2.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&uart2 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-ttyS4.dtsi b/arch/arm/boot/dts/am335x-peripheral-ttyS4.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-ttyS4.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-ttyS4.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&uart4 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-peripheral-ttyS5.dtsi b/arch/arm/boot/dts/am335x-peripheral-ttyS5.dtsi --- a/arch/arm/boot/dts/am335x-peripheral-ttyS5.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-peripheral-ttyS5.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&uart5 { + pinctrl-names = "default"; + + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -8,6 +8,7 @@ */ #include "am33xx.dtsi" +#include / { model = "Phytec AM335x phyCORE"; @@ -165,7 +166,12 @@ pinctrl-0 = <&nandflash_pins>; ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */ nandflash: nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-nand = "true"; @@ -184,13 +190,10 @@ gpmc,access-ns = <30>; gpmc,rd-cycle-ns = <30>; gpmc,wr-cycle-ns = <30>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <50>; gpmc,cycle2cycle-diffcsen; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <30>; gpmc,wr-data-mux-bus-ns = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-sancloud-bbe.dts b/arch/arm/boot/dts/am335x-sancloud-bbe.dts --- a/arch/arm/boot/dts/am335x-sancloud-bbe.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-sancloud-bbe.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am33xx-es2.dtsi" +#include "am335x-bone-common.dtsi" +#include "am33xx-overlay-edma-fix.dtsi" +#include + +/ { + model = "SanCloud BeagleBone Enhanced"; + compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + +&ldo3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&mmc1 { + vmmc-supply = <&vmmcsd_fixed>; +}; + +&mmc2 { + vmmc-supply = <&vmmcsd_fixed>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + status = "okay"; + ti,vcc-aux-disable-is-sleep; +}; + +&sgx { + status = "okay"; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_ctrl>; + + nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */ + AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */ + AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */ + AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ + >; + }; + nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ + 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + usb_hub_ctrl: usb_hub_ctrl { + pinctrl-single,pins = < + 0x144 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ + >; + }; + + mpu6050_pins: pinmux_mpu6050_pins { + pinctrl-single,pins = < + 0x168 (PIN_INPUT | MUX_MODE7) /* spi0_sclk.gpio0_2 */ + >; + }; + + lps3331ap_pins: pinmux_lps3331ap_pins { + pinctrl-single,pins = < + 0x6C (PIN_INPUT | MUX_MODE7) /* conf_gpmc_a11.gpio1_27 */ + >; + }; +}; + +&lcdc { + status = "okay"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&hdmi_0>; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii-txid"; +}; + +&i2c0 { + tda19988: tda19988 { + compatible = "nxp,tda998x"; + reg = <0x70>; + + pinctrl-names = "default", "off"; + pinctrl-0 = <&nxp_hdmi_bonelt_pins>; + pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; + + ports { + port@0 { + hdmi_0: endpoint@0 { + remote-endpoint = <&lcdc_0>; + }; + }; + }; + }; + + lps331ap: lps331ap@5C { + compatible = "st,lps331ap"; + reg = <0x5C>; + interrupts = <0>, <1>; + }; + + mpu6050: mpu6050@68 { + compatible = "inv,mpu6050"; + reg = <0x68>; + orientation = <0xff 0 0 0 1 0 0 0 0xff>; + interrupts = <2 1>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am335x-som-common.dtsi b/arch/arm/boot/dts/am335x-som-common.dtsi --- a/arch/arm/boot/dts/am335x-som-common.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am335x-som-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,465 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_fixed>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + ocp { + uart0: serial@44e09000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; + }; + uart1: serial@48022000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + + }; + uart4: serial@481a8000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; + }; + + epwmss0: epwmss@48300000 { + status = "okay"; + + ecap0: ecap@48300100 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ecap0_pins_default>; + pinctrl-1 = <&ecap0_pins_sleep>; + }; + }; + + musb: usb@47400000 { + status = "okay"; + + control@44e10000 { + status = "okay"; + }; + + usb-phy@47401300 { + status = "okay"; + }; + + usb-phy@47401b00 { + status = "okay"; + }; + + usb@47401000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb@47401800 { + status = "okay"; + dr_mode = "host"; + }; + + dma-controller@07402000 { + status = "okay"; + }; + }; + + i2c0: i2c@44e0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + clock-frequency = <100000>; + + tps: tps@24 { + reg = <0x24>; + }; + }; + }; + + vmmcsd_fixed: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + dcdc2_fixed: fixedregulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ + compatible = "regulator-fixed"; + regulator-name = "dcdc2_fixed"; + + regulator-min-microvolt = <1378000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds_s0>; + + compatible = "gpio-leds"; + + led@1 { + label = "led1:green:heartbeat"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led@2 { + label = "led2:red:heartbeat"; + gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led@3 { + label = "led3:yello:heartbeat"; + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led@4 { + label = "bkl"; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 500000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <50>; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&clkout2_pin>; + + user_leds_s0: user_leds_s0 { + pinctrl-single,pins = < + 0x1b0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr0.gpio0_19 */ + 0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr0.gpio3_20 */ + 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_axr1.gpio3_21 */ + 0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_fsr.gpio3[19], INPUT_PULLDOWN | MODE7 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x168 (PIN_INPUT_PULLUP | MUX_MODE1) + 0x16c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) + >; + }; + + + + clkout2_pin: pinmux_clkout2_pin { + pinctrl-single,pins = < + 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* xdma_event_intr1.clkout2 */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ + 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */ + 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */ + 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */ + 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */ + 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */ + 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */ + 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */ + 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */ + 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */ + + 0x040 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a0.gmii2_txen, OUTPUT_PULLDOWN | MODE1 */ + 0x044 (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a1.gmii2_rxdv, INPUT_PULLDOWN | MODE1 */ + 0x048 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a2.gmii2_txd3, OUTPUT_PULLDOWN | MODE1 */ + 0x04c (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a3.gmii2_txd2, OUTPUT_PULLDOWN | MODE1 */ + 0x050 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a4.gmii2_txd1, OUTPUT_PULLDOWN | MODE1 */ + 0x054 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* gpmc_a5.gmii2_txd0, OUTPUT_PULLDOWN | MODE1 */ + 0x058 (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a6.gmii2_txclk, INPUT_PULLDOWN | MODE1 */ + 0x05c (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a7.gmii2_rxclk, INPUT_PULLDOWN | MODE1 */ + 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a8.gmii2_rxd3, INPUT_PULLDOWN | MODE1 */ + 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a9.gmii2_rxd2, INPUT_PULLDOWN | MODE1 */ + 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a10.gmii2_rxd1, INPUT_PULLDOWN | MODE1 */ + 0x06c (PIN_INPUT_PULLDOWN | MUX_MODE1 ) /* gpmc_a11.gmii2_rxd0, INPUT_PULLDOWN | MODE1 */ + 0x070 (PIN_INPUT_PULLUP | MUX_MODE1 ) /* gpmc_wait0.gmii2_crs, INPUT_PULLUP | MODE1 */ + 0x074 (PIN_INPUT_PULLUP | MUX_MODE1 ) /* gpmc_wpn.gmii2_rxer, INPUT_PULLUP | MODE1 */ + 0x078 (PIN_INPUT_PULLUP | MUX_MODE1 ) /* gpmc_ben1.gmii2_col, INPUT_PULLUP | MODE1 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) + + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x078 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins_default: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ + 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ + 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ + 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ + 0x1A0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3_18 */ + 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ + >; + }; + + mmc1_pins_sleep: pinmux_mmc1_pins_sleep { + pinctrl-single,pins = < + 0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + ecap0_pins_default: backlight_pins { + pinctrl-single,pins = < + 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ + >; + }; + + ecap0_pins_sleep: ecap0_pins_sleep { + pinctrl-single,pins = < + 0x164 (PULL_DISABLE | MUX_MODE7) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ + >; + }; + dcan0_default: dcan0_default_pins { + pinctrl-single,pins = < + 0x178 0x0a /* uart1_ctsn.dcan0_tx_mux2, OUTPUT | MODE2 */ + 0x17c 0x2a /* uart1_rtsn.dcan0_rx_mux2, INPUT | MODE2 */ + >; + }; + }; + +&tps { + compatible = "ti,tps65217"; + regulators { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + reg = <1>; + /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + reg = <2>; + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + reg = <5>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + reg = <6>; + regulator-always-on; + }; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "mii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "mii"; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + slaves = <2>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + status = "okay"; + bus-width = <0x4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_sleep>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cd-inverted; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_default>; + status = "okay"; +}; + +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x00 0x11 0x22 0x33>; + }; + + adc { + ti,adc-channels = <0 1 2 3>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi --- a/arch/arm/boot/dts/am33xx.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am33xx.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -80,6 +80,7 @@ mpu { compatible = "ti,omap3-mpu"; ti,hwmods = "mpu"; + sram = <&ocmcram>; }; }; @@ -90,7 +91,7 @@ * for the moment, just use a fake OCP bus entry to represent * the whole bus hierarchy. */ - ocp { + ocp: ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -161,6 +162,14 @@ mboxes = <&mailbox &mbox_wkupm3>; }; + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + scm_clockdomains: clockdomains { }; }; @@ -174,12 +183,50 @@ }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = <12 13 14>; - #dma-cells = <1>; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; + }; + + emif: emif@4c000000 { + compatible = "ti,emif-am3352"; + reg = <0x4C000000 0x1000>; + sram = <&ocmcram>; }; gpio0: gpio@44e07000 { @@ -233,7 +280,7 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; - dmas = <&edma 26>, <&edma 27>; + dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; @@ -244,7 +291,7 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; - dmas = <&edma 28>, <&edma 29>; + dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; @@ -255,7 +302,7 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; - dmas = <&edma 30>, <&edma 31>; + dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; @@ -322,8 +369,8 @@ ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma_xbar 24 0 0 + &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; interrupt-parent = <&intc>; @@ -335,8 +382,8 @@ compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0 + &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; interrupt-parent = <&intc>; @@ -399,9 +446,18 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; + mbox_pru0: mbox_pru0 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + }; + mbox_pru1: mbox_pru1 { + ti,mbox-tx = <4 0 0>; + ti,mbox-rx = <5 0 0>; + }; }; timer1: timer@44e31000 { @@ -474,10 +530,10 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 - &edma 17 - &edma 18 - &edma 19>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -490,10 +546,10 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -643,15 +699,24 @@ reg = <0x48300100 0x80>; interrupts = <31>; interrupt-names = "ecap0"; - ti,hwmods = "ecap0"; status = "disabled"; }; - ehrpwm0: ehrpwm@48300200 { + eqep0: eqep@0x48300180 { + compatible = "ti,am33xx-eqep"; + reg = <0x48300180 0x80>; + interrupt-parent = <&intc>; + interrupts = <79>; + ti,hwmods = "eqep0"; + status = "disabled"; + }; + + ehrpwm0: pwm@48300200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -673,15 +738,25 @@ reg = <0x48302100 0x80>; interrupts = <47>; interrupt-names = "ecap1"; - ti,hwmods = "ecap1"; status = "disabled"; }; - ehrpwm1: ehrpwm@48302200 { + + eqep1: eqep@0x48302180 { + compatible = "ti,am33xx-eqep"; + reg = <0x48302180 0x80>; + interrupt-parent = <&intc>; + interrupts = <88>; + ti,hwmods = "eqep1"; + status = "disabled"; + }; + + ehrpwm1: pwm@48302200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -703,15 +778,24 @@ reg = <0x48304100 0x80>; interrupts = <61>; interrupt-names = "ecap2"; - ti,hwmods = "ecap2"; status = "disabled"; }; - ehrpwm2: ehrpwm@48304200 { + eqep2: eqep@0x48304180 { + compatible = "ti,am33xx-eqep"; + reg = <0x48304180 0x80>; + interrupt-parent = <&intc>; + interrupts = <89>; + ti,hwmods = "eqep2"; + status = "disabled"; + }; + + ehrpwm2: pwm@48304200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -776,7 +860,69 @@ ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; - reg = <0x40300000 0x10000>; /* 64k */ + reg = <0x40300000 0x2000>; /* 8k */ + map-exec; + }; + + ocmcram_nocache: ocmcram_nocache@40302000 { + compatible = "mmio-sram"; + reg = <0x40302000 0xe000>; /* 64k - 8k */ + }; + + pruss: pruss@4a300000 { + compatible = "ti,am3352-pruss"; + ti,hwmods = "pruss"; + reg = <0x4a300000 0x2000>, + <0x4a302000 0x2000>, + <0x4a310000 0x3000>, + <0x4a320000 0x2000>, + <0x4a326000 0x2000>, + <0x4a32e000 0x31c>, + <0x4a332000 0x58>; + reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg", + "iep", "mii_rt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_intc: intc@4a320000 { + compatible = "ti,am3352-pruss-intc"; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru0: pru0@4a334000 { + compatible = "ti,am3352-pru"; + reg = <0x4a334000 0x2000>, + <0x4a322000 0x400>, + <0x4a322400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru0>; + }; + + pru1: pru1@4a338000 { + compatible = "ti,am3352-pru"; + reg = <0x4a338000 0x2000>, + <0x4a324000 0x400>, + <0x4a324400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru1>; + }; + + pruss_mdio: mdio@4a332400 { + compatible = "ti,davinci_mdio"; + reg = <0x4a332400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; elm: elm@48080000 { @@ -819,10 +965,16 @@ ti,no-idle-on-init; reg = <0x50000000 0x2000>; interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; gpmc,num-cs = <7>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; @@ -831,7 +983,7 @@ ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; }; @@ -840,8 +992,8 @@ ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; - dmas = <&edma 6>, - <&edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -854,8 +1006,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; @@ -868,8 +1020,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; @@ -879,6 +1031,20 @@ reg = <0x48310000 0x2000>; interrupts = <111>; }; + + /* + * The SGX is disabled by default because it is an optional + * module and only some AM335x variants contain this module, + * such as AM3358 and AM3357. The status should be overwritten + * as "OK" at the corresponding board.dts. + */ + sgx: sgx@0x56000000 { + compatible = "ti,am3352-sgx530", "img,sgx530"; + ti,hwmods = "gfx"; + reg = <0x56000000 0x1000000>; + interrupts = <37>; + status = "disabled"; + }; }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am33xx-es2.dtsi b/arch/arm/boot/dts/am33xx-es2.dtsi --- a/arch/arm/boot/dts/am33xx-es2.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am33xx-es2.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,34 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + cpus { + cpu@0 { + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 1000000 1325000 + 800000 1300000 + 600000 1112000 + 300000 969000 + >; + voltage-tolerance = <2>; /* 2 percentage */ + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am33xx-overlay-edma-fix.dtsi b/arch/arm/boot/dts/am33xx-overlay-edma-fix.dtsi --- a/arch/arm/boot/dts/am33xx-overlay-edma-fix.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am33xx-overlay-edma-fix.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,25 @@ +/* + * Device Tree Source for AM33xx Overlay EDMA fixes + * + * Copyright (C) 2015 Robert Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&mcasp0 { + status = "okay"; +}; + +&mcasp1 { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi --- a/arch/arm/boot/dts/am4372.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am4372.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -47,6 +47,15 @@ }; }; + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap4-mpu"; + ti,hwmods = "mpu"; + sram = <&ocmcram>; + }; + }; + gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; @@ -98,6 +107,7 @@ #size-cells = <1>; ranges; ti,hwmods = "l3_main"; + ti,no-idle; reg = <0x44000000 0x400000 0x44800000 0x400000>; interrupts = , @@ -171,6 +181,14 @@ mboxes = <&mailbox &mbox_wkupm3>; }; + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <64>; + dma-masters = <&edma>; + }; + scm_clockdomains: clockdomains { }; }; @@ -180,17 +198,51 @@ compatible = "ti,emif-am4372"; reg = <0x4c000000 0x1000000>; ti,hwmods = "emif"; + ti,no-idle; + sram = <&ocmcram>; }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x10>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = , - , - ; - #dma-cells = <1>; + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <58 59>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; }; uart0: serial@44e09000 { @@ -249,9 +301,18 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; mbox_wkupm3: wkup_m3 { + ti,mbox-send-noirq; ti,mbox-tx = <0 0 0>; ti,mbox-rx = <0 0 3>; }; + mbox_pru1_0: mbox_pru1_0 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + }; + mbox_pru1_1: mbox_pru1_1 { + ti,mbox-tx = <4 0 0>; + ti,mbox-rx = <5 0 0>; + }; }; timer1: timer@44e31000 { @@ -360,6 +421,7 @@ ti,hwmods = "rtc"; clocks = <&clk_32768_ck>; clock-names = "int-clk"; + system-power-controller; status = "disabled"; }; @@ -495,8 +557,8 @@ ti,hwmods = "mmc1"; ti,dual-volt; ti,needs-special-reset; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma 24 0>, + <&edma 25 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -507,8 +569,8 @@ reg = <0x481d8000 0x1000>; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0>, + <&edma 3 0>; dma-names = "tx", "rx"; interrupts = ; status = "disabled"; @@ -633,15 +695,15 @@ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; status = "disabled"; }; - ehrpwm0: ehrpwm@48300200 { + ehrpwm0: pwm@48300200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; - ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -659,15 +721,15 @@ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48302100 0x80>; - ti,hwmods = "ecap1"; status = "disabled"; }; - ehrpwm1: ehrpwm@48302200 { + ehrpwm1: pwm@48302200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; - ti,hwmods = "ehrpwm1"; + clocks = <&ehrpwm1_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -685,15 +747,15 @@ compatible = "ti,am4372-ecap","ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48304100 0x80>; - ti,hwmods = "ecap2"; status = "disabled"; }; - ehrpwm2: ehrpwm@48304200 { + ehrpwm2: pwm@48304200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; - ti,hwmods = "ehrpwm2"; + clocks = <&ehrpwm2_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -707,11 +769,12 @@ ti,hwmods = "epwmss3"; status = "disabled"; - ehrpwm3: ehrpwm@48306200 { + ehrpwm3: pwm@48306200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; - ti,hwmods = "ehrpwm3"; + clocks = <&ehrpwm3_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -725,11 +788,12 @@ ti,hwmods = "epwmss4"; status = "disabled"; - ehrpwm4: ehrpwm@48308200 { + ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; - ti,hwmods = "ehrpwm4"; + clocks = <&ehrpwm4_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -743,11 +807,12 @@ ti,hwmods = "epwmss5"; status = "disabled"; - ehrpwm5: ehrpwm@4830a200 { + ehrpwm5: pwm@4830a200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4830a200 0x80>; - ti,hwmods = "ehrpwm5"; + clocks = <&ehrpwm5_tbclk>; + clock-names = "tbclk"; status = "disabled"; }; }; @@ -776,7 +841,7 @@ compatible = "ti,omap5-sham"; ti,hwmods = "sham"; reg = <0x53100000 0x300>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; interrupts = ; }; @@ -786,8 +851,8 @@ ti,hwmods = "aes"; reg = <0x53501000 0xa0>; interrupts = ; - dmas = <&edma 6 - &edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -796,11 +861,80 @@ ti,hwmods = "des"; reg = <0x53701000 0xa0>; interrupts = ; - dmas = <&edma 34 - &edma 33>; + dmas = <&edma 34 0>, + <&edma 33 0>; dma-names = "tx", "rx"; }; + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = ; + }; + + pruss1: pruss@54400000 { + compatible = "ti,am4372-pruss"; + ti,hwmods = "pruss"; + reg = <0x54400000 0x2000>, + <0x54402000 0x2000>, + <0x54410000 0x8000>, + <0x54420000 0x2000>, + <0x54426000 0x2000>, + <0x5442e000 0x31c>, + <0x54432000 0x58>; + reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg", + "iep", "mii_rt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss1_intc: intc@54420000 { + compatible = "ti,am4372-pruss-intc"; + interrupts = ; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host8", + "host9"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru1_0: pru0@54434000 { + compatible = "ti,am4372-pru"; + reg = <0x54434000 0x3000>, + <0x54422000 0x400>, + <0x54422400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru1_0>; + }; + + pru1_1: pru1@54438000 { + compatible = "ti,am4372-pru"; + reg = <0x54438000 0x3000>, + <0x54424000 0x400>, + <0x54424400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru1_1>; + }; + + pruss1_mdio: mdio@54432400 { + compatible = "ti,davinci_mdio"; + reg = <0x54432400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + mcasp0: mcasp@48038000 { compatible = "ti,am33xx-mcasp-audio"; ti,hwmods = "mcasp0"; @@ -810,8 +944,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; @@ -824,8 +958,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; @@ -842,6 +976,8 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; clocks = <&l3s_gclk>; clock-names = "fck"; reg = <0x50000000 0x2000>; @@ -850,21 +986,13 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; - am43xx_control_usb2phy1: control-phy@44e10620 { - compatible = "ti,control-phy-usb2-am437"; - reg = <0x44e10620 0x4>; - reg-names = "power"; - }; - - am43xx_control_usb2phy2: control-phy@0x44e10628 { - compatible = "ti,control-phy-usb2-am437"; - reg = <0x44e10628 0x4>; - reg-names = "power"; - }; - ocp2scp0: ocp2scp@483a8000 { compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; @@ -875,7 +1003,7 @@ usb2_phy1: phy@483a8000 { compatible = "ti,am437x-usb2"; reg = <0x483a8000 0x8000>; - ctrl-module = <&am43xx_control_usb2phy1>; + syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, <&usb_otg_ss0_refclk960m>; clock-names = "wkupclk", "refclk"; @@ -894,7 +1022,7 @@ usb2_phy2: phy@483e8000 { compatible = "ti,am437x-usb2"; reg = <0x483e8000 0x8000>; - ctrl-module = <&am43xx_control_usb2phy2>; + syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, <&usb_otg_ss1_refclk960m>; clock-names = "wkupclk", "refclk"; @@ -963,7 +1091,9 @@ qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; - reg = <0x47900000 0x100>; + reg = <0x47900000 0x100>, + <0x30000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; @@ -1014,7 +1144,13 @@ ocmcram: ocmcram@40300000 { compatible = "mmio-sram"; - reg = <0x40300000 0x40000>; /* 256k */ + reg = <0x40300000 0x10000>; /* 64k */ + map-exec; + }; + + ocmcram_nocache: ocmcram_nocache@40310000 { + compatible = "mmio-sram"; + reg = <0x40310000 0x30000>; /* 192k */ }; dcan0: can@481cc000 { @@ -1054,6 +1190,20 @@ ti,hwmods = "vpfe1"; status = "disabled"; }; + + /* + * The SGX is disabled by default because it is an optional + * module and only some AM437x variants contain this module, + * such as AM4378 and AM4379. The status should be overwritten + * as "OK" at the corresponding board.dts. + */ + sgx: sgx@0x56000000 { + compatible = "ti,am4376-sgx530", "img,sgx530"; + ti,hwmods = "gfx"; + reg = <0x56000000 0x1000000>; + interrupts = ; + status = "disabled"; + }; }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts --- a/arch/arm/boot/dts/am437x-gp-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am437x-gp-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -51,7 +51,7 @@ enable-active-high; }; - backlight { + lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; @@ -145,13 +145,26 @@ system-clock-frequency = <12000000>; }; }; + + audio_mstrclk: mclk_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + }; &am43xx_pinmux { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&wlan_pins_default>; + pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default>; pinctrl-1 = <&wlan_pins_sleep>; + ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + pinctrl-single,pins = < + 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ + >; + }; + i2c0_pins: i2c0_pins { pinctrl-single,pins = < 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ @@ -537,7 +550,14 @@ regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; + dcdc5: regulator-dcdc5 { compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; @@ -545,6 +565,9 @@ regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; dcdc6: regulator-dcdc6 { @@ -554,6 +577,9 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo1: regulator-ldo1 { @@ -569,7 +595,7 @@ compatible = "ovti,ov2659"; reg = <0x30>; - clocks = <&refclk 0>; + clocks = <&audio_mstrclk>; clock-names = "xvclk"; port { @@ -612,7 +638,7 @@ compatible = "ovti,ov2659"; reg = <0x30>; - clocks = <&refclk 0>; + clocks = <&audio_mstrclk>; clock-names = "xvclk"; port { @@ -734,8 +760,8 @@ status = "okay"; /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 30 - &edma 31>; + dmas = <&edma_xbar 30 0 1>, + <&edma_xbar 31 0 2>; dma-names = "tx", "rx"; vmmc-supply = <&vmmcwl_fixed>; bus-width = <4>; @@ -756,11 +782,6 @@ }; }; -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 30 - 2 31>; -}; - &uart3 { status = "okay"; pinctrl-names = "default"; @@ -772,7 +793,7 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; @@ -817,9 +838,14 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -838,11 +864,9 @@ gpmc,access-ns = <30>; gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; - gpmc,wait-pin = <0>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ @@ -979,3 +1003,13 @@ clock-names = "ext-clk", "int-clk"; status = "okay"; }; + +&wkup_m3_ipc { + ti,set-io-isolation; + ti,scale-data-fw = "am43x-evm-scale-data.bin"; +}; + + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am437x-gp-evm-hdmi.dts b/arch/arm/boot/dts/am437x-gp-evm-hdmi.dts --- a/arch/arm/boot/dts/am437x-gp-evm-hdmi.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am437x-gp-evm-hdmi.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* AM437x GP EVM with HDMI output */ + +#include "am437x-gp-evm.dts" +#include + +/ { + aliases { + display0 = &hdmi; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "b"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + sound@1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-frequency = <24000000>; + system-clock-direction = "out"; + }; + + simple-audio-card,codec { + sound-dai = <&sii9022>; + system-clock-frequency = <12000000>; + }; + }; +}; + +&lcd_bl { + status = "disabled"; +}; + +&sound0 { + status = "disabled"; +}; + +&i2c1 { + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + i2s-fifo-routing = < + (ENABLE_BIT|CONNECT_SD0) + 0 + 0 + 0 + >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dss { + port { + dpi_out: endpoint@0 { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; + +/* Override SelLCDorHDMI from am437x-gp-evm.dts to select HDMI */ +&gpio5 { + p8 { + output-low; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts --- a/arch/arm/boot/dts/am437x-idk-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am437x-idk-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -117,6 +117,58 @@ compatible = "fixed-clock"; clock-frequency = <32768>; }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; }; &am43xx_pinmux { @@ -178,6 +230,24 @@ >; }; + spi1_pins_default: spi1_pins_default { + pinctrl-single,pins = < + 0x108 (PIN_INPUT | MUX_MODE2) /* mii1_col.spi1_sclk */ + 0x110 (PIN_INPUT | MUX_MODE2) /* mii1_rx_er.spi1_d1 */ + 0x144 (PIN_OUTPUT | MUX_MODE2) /* rmii1_ref_clk.spi1_cs0 */ + 0x10c (PIN_OUTPUT | MUX_MODE7) /* mii1_crs.gpio3_1 */ + >; + }; + + spi1_pins_sleep: spi1_pins_sleep { + pinctrl-single,pins = < + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + ecap0_pins_default: backlight_pins_default { pinctrl-single,pins = < 0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */ @@ -290,6 +360,33 @@ pinctrl-0 = <&i2c2_pins_default>; pinctrl-1 = <&i2c2_pins_sleep>; clock-frequency = <100000>; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; }; &epwmss0 { @@ -310,6 +407,10 @@ status = "okay"; }; +&gpio3 { + status = "okay"; +}; + &gpio4 { status = "okay"; }; @@ -413,3 +514,7 @@ &cpu { cpu0-supply = <&tps>; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts --- a/arch/arm/boot/dts/am437x-sk-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am437x-sk-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -15,6 +15,7 @@ #include #include #include +#include / { model = "TI AM437x SK EVM"; @@ -152,6 +153,15 @@ }; }; }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &am43xx_pinmux { @@ -252,6 +262,12 @@ >; }; + clkout1_pin: pinmux_clkout1_pin { + pinctrl-single,pins = < + 0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */ + >; + }; + cpsw_default: cpsw_default { pinctrl-single,pins = < /* Slave 1 */ @@ -412,6 +428,62 @@ 0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ >; }; + + mmc3_pins_default: pinmux_mmc3_pins_default { + pinctrl-single,pins = < + 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* (AD21) cam1_data2.mmc2_clk */ + 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* (AE22) cam1_data3.mmc2_cmd */ + 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* (AD22) cam1_data4.mmc2_dat0 */ + 0x1fc (PIN_INPUT_PULLUP | MUX_MODE3) /* (AE23) cam1_data5.mmc2_dat1 */ + 0x200 (PIN_INPUT_PULLUP | MUX_MODE3) /* (AD23) cam1_data6.mmc2_dat2 */ + 0x204 (PIN_INPUT_PULLUP | MUX_MODE3) /* (AE24) cam1_data7.mmc2_dat3 */ + >; + }; + + mmc3_pins_sleep: pinmux_mmc3_pins_sleep { + pinctrl-single,pins = < + 0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD21) cam1_data2.mmc2_clk */ + 0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE22) cam1_data3.mmc2_cmd */ + 0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD22) cam1_data4.mmc2_dat0 */ + 0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE23) cam1_data5.mmc2_dat1 */ + 0x200 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AD23) cam1_data6.mmc2_dat2 */ + 0x204 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* (AE24) cam1_data7.mmc2_dat3 */ + >; + }; + + wlan_pins_default: pinmux_wlan_pins_default { + pinctrl-single,pins = < + 0x1d0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ + 0x1e4 (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ + >; + }; + + wlan_pins_sleep: pinmux_wlan_pins_sleep { + pinctrl-single,pins = < + 0x1d0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data8.gpio4_8 WL_EN */ + 0x1e4 (PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* cam1_wen.gpio4_13 WL_IRQ */ + >; + }; + + uart1_bt_pins_default: pinmux_uart1_bt_pins_default { + pinctrl-single,pins = < + 0x180 (PIN_INPUT | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ + 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + 0x1cc (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* cam1_data9.gpiop BT_EN */ + >; + }; + + uart1_bt_pins_sleep: pinmux_uart1_bt_pins_sleep { + pinctrl-single,pins = < + 0x180 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.uart1_rxd */ + 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.uart1_txd */ + 0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */ + 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */ + 0x1cc (PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_data9.gpio4_7 BT_EN */ + >; + }; }; &i2c0 { @@ -454,6 +526,12 @@ regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; dcdc4: regulator-dcdc4 { @@ -465,6 +543,30 @@ regulator-always-on; }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + ldo1: regulator-ldo1 { compatible = "ti,tps65218-ldo1"; regulator-name = "v1_8d"; @@ -494,6 +596,25 @@ pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&clkout1_pin>; + + clocks = <&clkout1_mux_ck>; + clock-names = "xvclk"; + assigned-clocks = <&clkout1_mux_ck>; + assigned-clock-parents = <&clkout1_osc_div_ck>; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe0_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; + edt-ft5306@38 { status = "okay"; compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; @@ -552,6 +673,10 @@ status = "okay"; }; +&gpio4 { + status = "okay"; +}; + &gpio5 { status = "okay"; }; @@ -566,12 +691,54 @@ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; +&uart1 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart1_bt_pins_default>; + pinctrl-1 = <&uart1_bt_pins_sleep>; +}; + +&mmc3 { + status = "okay"; + /* these are on the crossbar and are outlined in the + * xbar-event-map element + */ + dmas = <&edma 30 + &edma 31>; + dma-names = "tx", "rx"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_sleep>; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&wlan_pins_default>; + pinctrl-1 = <&wlan_pins_sleep>; + reg = <2>; + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&edma { + ti,edma-xbar-event-map = /bits/ 16 <1 30 + 2 31>; +}; + &usb2_phy1 { status = "okay"; }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&usb1_pins>; @@ -726,7 +893,7 @@ /* Camera port */ port { vpfe0_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; @@ -734,3 +901,11 @@ }; }; }; + +&wkup_m3_ipc { + ti,scale-data-fw = "am43x-evm-scale-data.bin"; +}; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts --- a/arch/arm/boot/dts/am43x-epos-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am43x-epos-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -18,7 +18,7 @@ / { model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; + compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; aliases { display0 = &lcd0; @@ -138,6 +138,12 @@ system-clock-frequency = <12000000>; }; }; + + audio_mstrclk: mclk_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &am43xx_pinmux { @@ -515,6 +521,21 @@ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ }; + + ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&audio_mstrclk>; + clock-names = "xvclk"; + + port { + ov2659_1: endpoint { + remote-endpoint = <&vpfe1_ep>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; }; &i2c2 { @@ -561,9 +582,14 @@ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -582,11 +608,9 @@ gpmc,access-ns = <30>; /* tCEA + 4*/ gpmc,rd-cycle-ns = <40>; gpmc,wr-cycle-ns = <40>; - gpmc,wait-pin = <0>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ @@ -673,7 +697,7 @@ }; &usb1 { - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; @@ -766,7 +790,7 @@ port { vpfe1_ep: endpoint { - /* remote-endpoint = <&sensor>; add once we have it */ + remote-endpoint = <&ov2659_1>; ti,am437x-vpfe-interface = <0>; bus-width = <8>; hsync-active = <0>; @@ -793,7 +817,15 @@ rx-num-evt = <32>; }; +&wkup_m3_ipc { + ti,scale-data-fw = "am43x-evm-scale-data.bin"; +}; + &synctimer_32kclk { assigned-clocks = <&mux_synctimer32k_ck>; assigned-clock-parents = <&clkdiv32k_ick>; }; + +&sgx { + status = "okay"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi --- a/arch/arm/boot/dts/am43xx-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -104,6 +104,14 @@ clock-div = <1>; }; + rng_fck: rng_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + ehrpwm0_tbclk: ehrpwm0_tbclk { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -771,4 +779,58 @@ ti,bit-shift = <8>; reg = <0x8a68>; }; + + clkout1_osc_div_ck: clkout1_osc_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <20>; + ti,max-div = <4>; + reg = <0x4100>; + }; + + clkout1_src2_mux_ck: clkout1_src2_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>; + reg = <0x4100>; + }; + + clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4100>; + }; + + clkout1_src2_post_div_ck: clkout1_src2_post_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4100>; + }; + + clkout1_mux_ck: clkout1_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, + <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; + ti,bit-shift = <16>; + reg = <0x4100>; + }; + + clkout1_ck: clkout1_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout1_mux_ck>; + ti,bit-shift = <23>; + reg = <0x4100>; + }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts --- a/arch/arm/boot/dts/am571x-idk.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am571x-idk.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include +#include +#include "am57xx-idk-common.dtsi" + +/ { + model = "TI AM5718 IDK"; + compatible = "ti,am5718-idk", "ti,am5718", "ti,dra722", + "ti,dra72", "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + + leds@1 { + compatible = "gpio-leds"; + led@0 { + label = "status0:red:cpu0"; + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led@1 { + label = "status0:green:usr"; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "status0:blue:heartbeat"; + gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led@3 { + label = "status1:red:usr"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@4 { + label = "status1:green:usr"; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "status1:blue:mmc0"; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; + +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + timers = <&timer3>; + watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + timers = <&timer11>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + timers = <&timer5>; +}; + +&ov2659_1 { + remote-endpoint = <&vin1b>; +}; + +&vin1b { + status = "okay"; + + endpoint@2 { + slave-mode; + remote-endpoint = <&ov2659_1>; + }; +}; + +&vip1 { + status = "okay"; +}; + +&sn65hvs882 { + load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am571x-idk-lcd-osd.dts b/arch/arm/boot/dts/am571x-idk-lcd-osd.dts --- a/arch/arm/boot/dts/am571x-idk-lcd-osd.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am571x-idk-lcd-osd.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am571x-idk.dts" +#include "am57xx-idk-lcd-osd.dtsi" + +/ { + model = "TI AM571x IDK-LCD-OSD-Display"; +}; + +&touchscreen { + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts --- a/arch/arm/boot/dts/am572x-idk.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am572x-idk.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,442 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "dra74x.dtsi" +#include +#include +#include "am57xx-idk-common.dtsi" + +/ { + model = "TI AM5728 IDK"; + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", + "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + leds@1 { + compatible = "gpio-leds"; + led@0 { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led@1 { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + led@3 { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + led@4 { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: mmc1_pins_hs { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2_pins_hs { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&dra7_iodelay_core { + + mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { + pinctrl-single,pins = < + 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ + 0x620 (A_DELAY(1271) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ + 0x624 (A_DELAY(229) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x630 (A_DELAY(850) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(20) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x63C (A_DELAY(468) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x648 (A_DELAY(466) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ + 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x654 (A_DELAY(399) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { + pinctrl-single,pins = < + 0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf { + pinctrl-single,pins = < + 0x18c (A_DELAY(270) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(170) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(758) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(81) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(286) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(123) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(346) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(55) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(422) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(642) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(128) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(395) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(623) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(54) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + >; + }; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>; + vmmc-supply = <&v3_3d>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ + max-frequency = <192000000>; +}; + +&mmc2 { + status = "okay"; + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>; + vmmc-supply = <&v3_3d>; + bus-width = <8>; + ti,non-removable; + max-frequency = <96000000>; + /* + * eMMC on AM572x IDK cannot support HS200 mode because + * the IO voltage is tied to 3.3V + */ + /delete-property/ mmc-hs200-1_8v; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; + +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu0_dsp2 { + status = "okay"; +}; + +&mmu1_dsp2 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + timers = <&timer3>; + watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + timers = <&timer11>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + timers = <&timer5>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + timers = <&timer6>; +}; + +&ov2659_1 { + remote-endpoint = <&vin4b>; +}; + +&vin4b { + status = "okay"; + + endpoint@3 { + slave-mode; + remote-endpoint = <&ov2659_1>; + }; +}; + +&vip2 { + status = "okay"; +}; + +&pcie1 { + gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; +}; + +&sn65hvs882 { + load-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am572x-idk-lcd-osd.dts b/arch/arm/boot/dts/am572x-idk-lcd-osd.dts --- a/arch/arm/boot/dts/am572x-idk-lcd-osd.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am572x-idk-lcd-osd.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am572x-idk.dts" +#include "am57xx-idk-lcd-osd.dtsi" + +/ { + model = "TI AM572x IDK-LCD-OSD-Display"; +}; + +&touchscreen { + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,691 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include +#include + +/ { + model = "TI AM5728 BeagleBoard-X15"; + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + rtc2 = &rtc; + display0 = &hdmi0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd_fixed"; + vin-supply = <&vdd_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ide-disk"; + default-state = "off"; + }; + }; + + gpio_fan: gpio_fan { + /* Based on 5v 500mA AFB02505HHB */ + compatible = "gpio-fan"; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <13000 1>; + #cooling-cells = <2>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "BeagleBoard-X15"; + simple-audio-card,widgets = + "Line", "Line Out", + "Line", "Line In"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC2L", "Line In", + "MIC2R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp3>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3104>; + clocks = <&clkout2_clk>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD / VDDSHV8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHYA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + tlv320aic3104: tlv320aic3104@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3104"; + reg = <0x18>; + + assigned-clocks = <&clkoutmux2_clk_mux>; + assigned-clock-parents = <&sys_clk2_dclk_div>; + + adc-settle-ms = <40>; + AVDD-supply = <&vdd_3v3>; + IOVDD-supply = <&vdd_3v3>; + DRVDD-supply = <&vdd_3v3>; + DVDD-supply = <&aic_dvdd>; + + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, + <&dra7_pmx_core 0x424>; + interrupt-names = "irq", "wakeup"; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; +}; + +&mac { + status = "okay"; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + /* + * Stand alone usage is peripheral only. + * However, with some resistor modifications + * this port can be used via expansion connectors + * as "host" or "dual-role". If so, provide + * the necessary dr_mode override in the expansion + * board's DT. + */ + dr_mode = "peripheral"; +}; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo4_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&sys_clkin2>; + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox3 { + status = "okay"; + mbox_pru1_0: mbox_pru1_0 { + status = "okay"; + }; + mbox_pru1_1: mbox_pru1_1 { + status = "okay"; + }; +}; + +&mailbox4 { + status = "okay"; + mbox_pru2_0: mbox_pru2_0 { + status = "okay"; + }; + mbox_pru2_1: mbox_pru2_1 { + status = "okay"; + }; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; + +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu0_dsp2 { + status = "okay"; +}; + +&mmu1_dsp2 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + timers = <&timer3>; + watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + timers = <&timer11>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + timers = <&timer5>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + timers = <&timer6>; +}; + +&pruss1 { + status = "okay"; + pru1_0: pru0@4b234000 { + mboxes = <&mailbox3 &mbox_pru1_0>; + status = "okay"; + }; + + pru1_1: pru1@4b238000 { + mboxes = <&mailbox3 &mbox_pru1_1>; + status = "okay"; + }; +}; + +&pruss2 { + status = "okay"; + pru2_0: pru0@4b2b4000 { + mboxes = <&mailbox4 &mbox_pru2_0>; + status = "okay"; + }; + + pru2_1: pru1@4b2b8000 { + mboxes = <&mailbox4 &mbox_pru2_1>; + status = "okay"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts 2016-05-11 13:31:53.193225201 -0400 @@ -1,827 +1,149 @@ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include "dra74x.dtsi" -#include -#include +#include "am57xx-beagle-x15-common.dtsi" +#include "am57xx-commercial-grade.dtsi" / { model = "TI AM5728 BeagleBoard-X15"; - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; - - led@0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led@1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led@2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led@3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "ide-disk"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&extcon_usb1_pins>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound@0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; }; &dra7_pmx_core { - leds_pins_default: leds_pins_default { - pinctrl-single,pins = < - 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ - 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ - 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ - 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ - >; - }; - - i2c1_pins_default: i2c1_pins_default { - pinctrl-single,pins = < - 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - i2c3_pins_default: i2c3_pins_default { - pinctrl-single,pins = < - 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - 0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ - 0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ - >; - }; mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < - 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - cpsw_pins_default: cpsw_pins_default { - pinctrl-single,pins = < - /* Slave 1 */ - 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ - 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ - 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ - 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ - 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ - 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ - 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ - 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ - 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ - 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ - 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ - 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ - - /* Slave 2 */ - 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ - 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ - 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ - 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ - 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ - 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ - 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ - 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ - 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ - 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ - 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ - 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ - >; - - }; - - cpsw_pins_sleep: cpsw_pins_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - 0x250 (PIN_INPUT | MUX_MODE15) - 0x254 (PIN_INPUT | MUX_MODE15) - 0x258 (PIN_INPUT | MUX_MODE15) - 0x25c (PIN_INPUT | MUX_MODE15) - 0x260 (PIN_INPUT | MUX_MODE15) - 0x264 (PIN_INPUT | MUX_MODE15) - 0x268 (PIN_INPUT | MUX_MODE15) - 0x26c (PIN_INPUT | MUX_MODE15) - 0x270 (PIN_INPUT | MUX_MODE15) - 0x274 (PIN_INPUT | MUX_MODE15) - 0x278 (PIN_INPUT | MUX_MODE15) - 0x27c (PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - 0x198 (PIN_INPUT | MUX_MODE15) - 0x19c (PIN_INPUT | MUX_MODE15) - 0x1a0 (PIN_INPUT | MUX_MODE15) - 0x1a4 (PIN_INPUT | MUX_MODE15) - 0x1a8 (PIN_INPUT | MUX_MODE15) - 0x1ac (PIN_INPUT | MUX_MODE15) - 0x1b0 (PIN_INPUT | MUX_MODE15) - 0x1b4 (PIN_INPUT | MUX_MODE15) - 0x1b8 (PIN_INPUT | MUX_MODE15) - 0x1bc (PIN_INPUT | MUX_MODE15) - 0x1c0 (PIN_INPUT | MUX_MODE15) - 0x1c4 (PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci_mdio_pins_default { - pinctrl-single,pins = < - /* MDIO */ - 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */ - 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { - pinctrl-single,pins = < - 0x23c (PIN_INPUT | MUX_MODE15) - 0x240 (PIN_INPUT | MUX_MODE15) - >; - }; - - tps659038_pins_default: tps659038_pins_default { - pinctrl-single,pins = < - 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - tmp102_pins_default: tmp102_pins_default { - pinctrl-single,pins = < - 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ - >; - }; - - mcp79410_pins_default: mcp79410_pins_default { - pinctrl-single,pins = < - 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - extcon_usb1_pins: extcon_usb1_pins { - pinctrl-single,pins = < - 0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */ + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat3.dat3 */ >; }; - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - 0x3b0 (PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ - 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - 0x370 (PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ - >; - }; - - clkout2_pins_default: clkout2_pins_default { - pinctrl-single,pins = < - 0x294 (PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */ - >; - }; - - clkout2_pins_sleep: clkout2_pins_sleep { - pinctrl-single,pins = < - 0x294 (PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */ - >; - }; - - mcasp3_pins_default: mcasp3_pins_default { - pinctrl-single,pins = < - 0x324 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - 0x328 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ + mmc1_pins_hs: pinmux_mmc1_hs_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat3.dat3 */ >; }; - mcasp3_pins_sleep: mcasp3_pins_sleep { + mmc2_pins_default: mmc2_pins_default { pinctrl-single,pins = < - 0x324 (PIN_INPUT | MUX_MODE15) - 0x328 (PIN_INPUT | MUX_MODE15) - 0x32c (PIN_INPUT | MUX_MODE15) - 0x330 (PIN_INPUT | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1030000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - ti,enable-id-detection; - id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tmp102_pins_default>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&clkout2_pins_default>; - pinctrl-1 = <&clkout2_pins_sleep>; - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - pinctrl-names = "default"; - pinctrl-0 = <&mcp79410_pins_default>; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; + DRA7XX_CORE_IOPAD(0x349c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&dra7_iodelay_core { + mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf { + pinctrl-single,pins = < + 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */ + 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */ + 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */ + 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */ + 0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */ + 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1ec (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A26_IN */ + 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */ + 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + >; + }; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; &mmc1 { - status = "okay"; - - pinctrl-names = "default"; + pinctrl-names = "default", "hs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + max-frequency = <96000000>; + /delete-property/ sd-uhs-sdr104; + /delete-property/ sd-uhs-sdr50; + /delete-property/ sd-uhs-ddr50; + /delete-property/ sd-uhs-sdr25; + /delete-property/ sd-uhs-sdr12; }; &mmc2 { - status = "okay"; - - pinctrl-names = "default"; + pinctrl-names = "default", "hs", "ddr_1_8v"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>; - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1 { - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; + max-frequency = <96000000>; + /delete-property/ mmc-hs200-1_8v; }; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts --- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am57xx-beagle-x15-common.dtsi" +#include "am57xx-commercial-grade.dtsi" + +/ { + model = "TI AM5728 BeagleBoard-X15 rev B1"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + vmmc-supply = <&vdd_3v3>; + vmmc-aux-supply = <&ldo1_reg>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/am57xx-commercial-grade.dtsi --- a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-commercial-grade.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,23 @@ +&cpu_alert0 { + temperature = <80000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <90000>; /* milliCelsius */ +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-evm-common.dtsi b/arch/arm/boot/dts/am57xx-evm-common.dtsi --- a/arch/arm/boot/dts/am57xx-evm-common.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-evm-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,213 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/ { + compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + USER1 { + label = "Up"; + linux,code = ; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + USER2 { + label = "Down"; + linux,code = ; + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + }; + + USER3 { + label = "Left"; + linux,code = ; + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + + USER4 { + label = "Right"; + linux,code = ; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + + USER5 { + label = "Home"; + linux,code = ; + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + }; + }; + + aliases { + display0 = &lcd0; + display1 = &hdmi0; + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + + label = "lcd"; + + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <16>; + hsync-len = <30>; + vback-porch = <10>; + vfront-porch = <22>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ehrpwm1 0 50000 0>; + + /* Anything lower than 241 is no longer visible */ + brightness-levels = <0 243 245 247 249 251 252 253 255>; + + default-brightness-level = <8>; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + mt9t11x@3C { + compatible = "aptina,mt9t111"; + reg = <0x3C>; + + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + oscen-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + bufen-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + camen-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + + port { + cam: endpoint { + remote-endpoint = <&vin3a>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + input-clock-freq = <32000000>; + pixel-clock-freq = <96000000>; + }; + }; + }; +}; + +&vip2 { + status = "okay"; +}; + +&vin3a { + status = "okay"; + endpoint { + slave-mode; + remote-endpoint = <&cam>; + }; +}; + +&pcie1 { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pixcir_ts@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + interrupt-parent = <&gpio2>; + interrupts = <4 0>; + + attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&mmc3 { + status = "okay"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-evm.dts b/arch/arm/boot/dts/am57xx-evm.dts --- a/arch/arm/boot/dts/am57xx-evm.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am57xx-beagle-x15.dts" +#include "am57xx-evm-common.dtsi" +#include "am57xx-commercial-grade.dtsi" + +/ { + model = "TI AM5728 EVM"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-evm-reva3.dts b/arch/arm/boot/dts/am57xx-evm-reva3.dts --- a/arch/arm/boot/dts/am57xx-evm-reva3.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-evm-reva3.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am57xx-beagle-x15-revb1.dts" +#include "am57xx-evm-common.dtsi" +#include "am57xx-industrial-grade.dtsi" + +/ { + model = "TI AM572x EVM Rev A3"; +}; + +&dra7_pmx_core { + + /* + * TODO: We should be able to move PinMux values defined here to + * am57xx-beagle-x15-revb1.dts once that board is available and + * its MMC/SD interface is verified. For now these stay here until + * that exercise is complete. + */ + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_hs: pinmux_mmc1_hs_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x379c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x37b0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x37a0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x37a4, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x37a8, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x37ac, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3794, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3798, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_hs: mmc2_pins_hs { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x379c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x37b0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x37a0, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x37a4, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x37a8, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x37ac, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3794, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3798, (PIN_INPUT_PULLUP | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x379c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x37b0, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x37a0, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x37a4, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x37a8, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x37ac, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3794, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3798, (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1)) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&dra7_iodelay_core { + mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { + pinctrl-single,pins = < + 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ + 0x620 (A_DELAY(1271) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ + 0x624 (A_DELAY(229) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x630 (A_DELAY(850) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(20) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x63C (A_DELAY(468) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x648 (A_DELAY(466) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ + 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x654 (A_DELAY(399) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf { + pinctrl-single,pins = < + 0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ + >; + }; + + mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf { + pinctrl-single,pins = < + 0x18c (A_DELAY(270) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(170) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(758) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(81) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(286) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(123) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(346) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(55) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(422) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(642) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(128) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(395) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(623) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(54) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + >; + }; +}; + +&mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>; + vmmc-supply = <&vdd_3v3>; + vmmc_aux-supply = <&ldo1_reg>; + max-frequency = <192000000>; +}; + +&mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>; + + max-frequency = <192000000>; + /delete-property/ mmc-hs200-1_8v; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,589 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "am57xx-industrial-grade.dtsi" + +/ { + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi0; + sound0 = &hdmi; + }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "VMAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + v3_3d: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "V3_3D"; + vin-supply = <&smps9_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&v3_3d>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder@0 { + compatible = "ti,tpd12s016", "ti,tpd12s015"; + + gpios = <0>, /* optional CT_CP_HPD */ + <0>, /* optional LS_OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + src_clk_x1: src_clk_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + + leds-iio { + status = "disabled"; + compatible = "gpio-leds"; + led-out0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-out7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&dra7_pmx_core { + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x3d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x3d4 (MUX_MODE15 | PULL_UP) /* dcan1_rx.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x418>; + #interrupt-cells = <2>; + interrupt-controller; + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + vin-supply = <&vmain>; + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + vin-supply = <&vmain>; + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE on AM572 */ + /* VDD_IVA + VDD_DSP on AM571 */ + vin-supply = <&vmain>; + regulator-name = "smps45"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU */ + vin-supply = <&vmain>; + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDD_CORE */ + vin-supply = <&vmain>; + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* 5728 - VDD_IVAHD */ + /* 5718 - N.C. test point */ + vin-supply = <&vmain>; + regulator-name = "smps8"; + }; + + smps9_reg: smps9 { + /* VDD_3_3D */ + vin-supply = <&vmain>; + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* VDDSHV8 - VSDMMC */ + /* NOTE: on rev 1.3a, data supply */ + vin-supply = <&vmain>; + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDDSH18V */ + vin-supply = <&vmain>; + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* R1.2a 572x V1_8PHY: USB1,2,3, SATA, PCIE, HDMI */ + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + /* R1.2a 571x V1_8PHY_LDO3: USB1,2, CSI; V1_8PHYA: SATA */ + vin-supply = <&vmain>; + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* R1.2a 572x - unused */ + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI */ + /* R1.2a 571x V1_8PHY_LDO4: V1_8PHYB: USB3, PCIE, HDMI */ + vin-supply = <&vmain>; + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + ldo9_reg: ldo9 { + /* VDD_RTC (unused in rev 1.3a am572x-idk) */ + vin-supply = <&vmain>; + regulator-name = "ldo9"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + vin-supply = <&vmain>; + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + vin-supply = <&vmain>; + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC (unused on rev am572x 1.3a) */ + vin-supply = <&vmain>; + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + tc358778: tc358778@0e { + compatible = "toshiba,tc358778", "toshiba,tc358768"; + reg = <0x0e>; + status = "disabled"; + + clocks = <&src_clk_x1>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tc358778_in: endpoint { + remote-endpoint = <&dpi_out>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + tc358778_out: endpoint { + /* + * lanes and remote-endpoint defined per + * panel. + */ + }; + }; + }; + }; + + tpic2810: tpic2810@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; + + ov2659: ov2659@30 { + compatible = "ovti,ov2659"; + reg = <0x30>; + + clocks = <&src_clk_x1>; + clock-names = "xvclk"; + + pwrdn-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + + port { + ov2659_1: endpoint { + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <1>; + link-frequencies = /bits/ 64 <70000000>; + }; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x248>; +}; + +&rtc { + status = "okay"; + ext-clk-src; +}; + +&mac { + status = "okay"; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&usb2 { + dr_mode = "otg"; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&v3_3d>; + bus-width = <8>; + ti,non-removable; + max-frequency = <96000000>; +}; + +&hdmi { + status = "okay"; + /* + * XXX: Support AM572x-Rev 1.2a. this is wrong for AM571x-rev 1.3a, + * AM572x-Rev1.3a - but thanks to always-on, they work. + * TODO: SWITCH TO LDO4 once rev 1.2a is deprecated + * (on rev 1.3a availability) + */ + vdda-supply = <&ldo3_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&dss { + status = "okay"; + + vdda_video-supply = <&ldoln_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&tc358778_in>; + data-lines = <24>; + }; + }; + }; +}; + +&mailbox3 { + status = "okay"; + mbox_pru1_0: mbox_pru1_0 { + status = "okay"; + }; + mbox_pru1_1: mbox_pru1_1 { + status = "okay"; + }; +}; + +&mailbox4 { + status = "okay"; + mbox_pru2_0: mbox_pru2_0 { + status = "okay"; + }; + mbox_pru2_1: mbox_pru2_1 { + status = "okay"; + }; +}; + +&pruss1 { + status = "okay"; + pru1_0: pru0@4b234000 { + mboxes = <&mailbox3 &mbox_pru1_0>; + status = "okay"; + }; + + pru1_1: pru1@4b238000 { + mboxes = <&mailbox3 &mbox_pru1_1>; + status = "okay"; + }; +}; + +&pruss2 { + status = "okay"; + pru2_0: pru0@4b2b4000 { + mboxes = <&mailbox4 &mbox_pru2_0>; + status = "okay"; + }; + + pru2_1: pru1@4b2b8000 { + mboxes = <&mailbox4 &mbox_pru2_1>; + status = "okay"; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-idk-lcd-osd.dtsi b/arch/arm/boot/dts/am57xx-idk-lcd-osd.dtsi --- a/arch/arm/boot/dts/am57xx-idk-lcd-osd.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-idk-lcd-osd.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + aliases { + display1 = &lcd; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; + + lcd: display { + /* + * TODO: Not a DPI panel, but a dummy DSI video mode panel. + * This needs to be changed later when we can support DSI VM + * panels properly. + */ + compatible = "osd,osd101t2045-53ts", "panel-dpi"; + + label = "lcd"; + + panel-timing { + clock-frequency = <154000000>; + hactive = <1920>; + vactive = <1200>; + + hfront-porch = <112>; + hback-porch = <32>; + hsync-len = <16>; + + vfront-porch = <16>; + vback-porch = <16>; + vsync-len = <2>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&tc358778_out>; + }; + }; + }; +}; + +&tc358778 { + status = "okay"; +}; + +&tc358778_out { + remote-endpoint = <&lcd_in>; + lanes = <0 1 2 3 4 5 6 7 8 9>; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; + +&i2c1 { + touchscreen: edt-ft5506@38 { + status = "okay"; + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/am57xx-industrial-grade.dtsi --- a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/am57xx-industrial-grade.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,23 @@ +&cpu_alert0 { + temperature = <90000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <105000>; /* milliCelsius */ +}; diff -Naur --no-dereference a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi --- a/arch/arm/boot/dts/da850.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/da850.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -203,13 +203,13 @@ interrupts = <16>; status = "disabled"; }; - ehrpwm0: ehrpwm@01f00000 { + ehrpwm0: pwm@01f00000 { compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; status = "disabled"; }; - ehrpwm1: ehrpwm@01f02000 { + ehrpwm1: pwm@01f02000 { compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; diff -Naur --no-dereference a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts --- a/arch/arm/boot/dts/dm8168-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dm8168-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -6,6 +6,7 @@ /dts-v1/; #include "dm816x.dtsi" +#include / { model = "DM8168 EVM"; @@ -85,8 +86,12 @@ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; linux,mtd-name= "micron,mt29f2g16aadwp"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ #address-cells = <1>; #size-cells = <1>; ti,nand-ecc-opt = "bch8"; @@ -106,12 +111,9 @@ gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; - gpmc,wait-on-read = "true"; - gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; partition@0 { diff -Naur --no-dereference a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi --- a/arch/arm/boot/dts/dm816x.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dm816x.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -182,6 +182,10 @@ interrupts = <100>; gpmc,num-cs = <6>; gpmc,num-waitpins = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; i2c1: i2c@48028000 { diff -Naur --no-dereference a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi --- a/arch/arm/boot/dts/dra72-evm-common.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,712 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include +#include + +/ { + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + aliases { + display0 = &hdmi0; + }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&evm_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "DRA7xx-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + sound0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + system-clock-frequency = <5644800>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&atl_clkin2_ck>; + }; + }; + + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; + + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */ + 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */ + 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */ + 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */ + 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */ + 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */ + 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */ + >; + }; + + wlirq_pins: pinmux_wlirq_pins { + pinctrl-single,pins = < + 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + interrupts = ; /* IRQ_SYS_1N */ + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + pcf_gpio_21: gpio@21 { + compatible = "ti,pcf8575"; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&evm_3v3>; + IOVDD-supply = <&evm_3v3>; + DRVDD-supply = <&evm_3v3>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + + p1 { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&uart3 { + status = "okay"; + gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra72-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "otg"; +}; + +&usb2 { + dr_mode = "host"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc-supply = <&evm_3v3_sd>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; + max-frequency = <192000000>; +}; + +&mmc4 { + status = "okay"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins &wlirq_pins>; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&mac { + status = "okay"; +}; + +&dcan1 { + status = "ok"; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <48000000>; + m25p80@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "ok"; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&atl { + assigned-clocks = <&abe_dpll_sys_clk_mux>, + <&atl_gfclk_mux>, + <&dpll_abe_ck>, + <&dpll_abe_m2x2_ck>, + <&atl_clkin2_ck>; + assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; + assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; + + status = "okay"; + + atl2 { + bws = ; + aws = ; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&atl_clkin2_ck>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; + +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + +&ipu2 { + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + timers = <&timer3>; + watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + timers = <&timer11>; +}; + +&dsp1 { + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + timers = <&timer5>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts --- a/arch/arm/boot/dts/dra72-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra72-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -1,214 +1,60 @@ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include "dra72x.dtsi" -#include -#include - +#include "dra72-evm-common.dtsi" / { model = "TI DRA722"; - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; memory { device_type = "memory"; - reg = <0x80000000 0x40000000>; /* 1024 MB */ - }; - - aliases { - display0 = &hdmi0; - }; - - evm_3v3: fixedregulator-evm_3v3 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; }; - }; - sound0: sound@0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; }; - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; }; }; }; -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> TP1017 (UNUSED) */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; }; +}; - mmc1_pins_default: mmc1_pins_default { +&dra7_pmx_core { + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < - 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ @@ -218,470 +64,233 @@ >; }; - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { + mmc1_pins_hs: pinmux_mmc1_hs_pins { pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mcasp3_pins: pinmux_mcasp3_pins { + mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { pinctrl-single,pins = < - 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { + mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { pinctrl-single,pins = < - 0x324 (PIN_INPUT_PULLDOWN | MUX_MODE15) - 0x328 (PIN_INPUT_PULLDOWN | MUX_MODE15) - 0x32c (PIN_INPUT_PULLDOWN | MUX_MODE15) - 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE15) + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + 0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; + + mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + >; + }; + + mmc2_pins_hs: pinmux_mmc2_hs_pins { + pinctrl-single,pins = < + 0x08C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x090 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x094 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x098 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + 0x09C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0x0A0 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0x0A4 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0x0A8 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0x0AC (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x0B0 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE13 | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + >; + }; + + mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins { + pinctrl-single,pins = < + 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + >; + }; + + mmc2_pins_hs200_1_8v: pinmux_mmc2_hs200_1_8v_pins { + pinctrl-single,pins = < + 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + >; + }; +}; + +&dra7_iodelay_core { + mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf { + pinctrl-single,pins = < + 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ + 0x620 (A_DELAY(1353) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ + 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ + 0x62C (A_DELAY(1) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x630 (A_DELAY(483) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ + 0x638 (A_DELAY(16) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x63C (A_DELAY(126) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x648 (A_DELAY(104) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ + 0x650 (A_DELAY(34) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x654 (A_DELAY(33) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ + 0x65C (A_DELAY(18) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + >; + }; + + mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf { + pinctrl-single,pins = < + 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ + 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x1A4 (A_DELAY(391) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ + 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ + 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1BC (A_DELAY(211) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ + 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1C8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ + 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1D4 (A_DELAY(320) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ + 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1EC (A_DELAY(159) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1F8 (A_DELAY(232) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + >; + }; + + mmc2_iodelay_hs200_1_8v_conf: mmc2_iodelay_hs200_1_8v_conf { + pinctrl-single,pins = < + 0x194 (A_DELAY(0) | G_DELAY(95)) /* CFG_GPMC_A19_OUT */ + 0x190 (A_DELAY(695) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x1AC (A_DELAY(214) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1A8 (A_DELAY(924) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1B8 (A_DELAY(19) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1B4 (A_DELAY(719) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1C4 (A_DELAY(83) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1C0 (A_DELAY(824) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1D0 (A_DELAY(1020) | G_DELAY(416)) /* CFG_GPMC_A23_OUT */ + 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1D8 (A_DELAY(877) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1E8 (A_DELAY(167) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1E4 (A_DELAY(446) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1F4 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1F0 (A_DELAY(847) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x1FC (A_DELAY(586) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x368 (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + 0x364 (A_DELAY(1039) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ >; }; }; &i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = ; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3>; - IOVDD-supply = <&evm_3v3>; - DRVDD-supply = <&evm_3v3>; - DVDD-supply = <&aic_dvdd>; - }; -}; - -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { + pcf_lcd: gpio@20 { compatible = "nxp,pcf8575"; - reg = <0x26>; + reg = <0x20>; gpio-controller; #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; }; }; -&uart1 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; +&i2c5 { + ov10633@37 { + compatible = "ovti,ov10633"; + reg = <0x37>; -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - reg = <0 0 4>; /* device IO registers */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; + mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */ + <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */ + port { + onboardLI: endpoint { + remote-endpoint = <&vin2a>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; }; }; }; -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; +&hdmi { + vdda_video-supply = <&ldo5_reg>; }; -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; +&pcf_gpio_21 { + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; }; &mmc1 { - status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50"; pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - max-frequency = <192000000>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>; }; &mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3>; - bus-width = <8>; - ti,non-removable; - max-frequency = <192000000>; -}; - -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (MUX_MODE15) - 0x19c (MUX_MODE15) - 0x1a0 (MUX_MODE15) - 0x1a4 (MUX_MODE15) - 0x1a8 (MUX_MODE15) - 0x1ac (MUX_MODE15) - 0x1b0 (MUX_MODE15) - 0x1b4 (MUX_MODE15) - 0x1b8 (MUX_MODE15) - 0x1bc (MUX_MODE15) - 0x1c0 (MUX_MODE15) - 0x1c4 (MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - 0x23c (MUX_MODE15) - 0x240 (MUX_MODE15) - >; - }; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>; + pinctrl-3 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_conf>; }; &mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; slaves = <1>; mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; }; @@ -691,157 +300,29 @@ phy-mode = "rgmii"; }; -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { +&ipu2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldo5_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo3_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; + memory-region = <&ipu2_cma_pool>; }; -&atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - +&ipu1 { status = "okay"; - - atl2 { - bws = ; - aws = ; - }; + memory-region = <&ipu1_cma_pool>; }; -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; - - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&atl_clkin2_ck>; - +&dsp1 { status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; + memory-region = <&dsp1_cma_pool>; }; -&mailbox5 { +&vip1 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; }; -&mailbox6 { +&vin2a { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; + endpoint@0 { + slave-mode; + remote-endpoint = <&onboardLI>; }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/dra72-evm-lcd-lg.dts b/arch/arm/boot/dts/dra72-evm-lcd-lg.dts --- a/arch/arm/boot/dts/dra72-evm-lcd-lg.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra72-evm-lcd-lg.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + #include "dra72-evm.dts" + #include "dra7x-evm-lcd-lg.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/dra72-evm-lcd-osd.dts b/arch/arm/boot/dts/dra72-evm-lcd-osd.dts --- a/arch/arm/boot/dts/dra72-evm-lcd-osd.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra72-evm-lcd-osd.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra72-evm.dts" +#include "dra7x-evm-lcd-osd.dtsi" + +&touchscreen { + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts --- a/arch/arm/boot/dts/dra72-evm-revc.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra72-evm-revc.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "dra72-evm-common.dtsi" +#include + +/ { + model = "TI DRA722 Rev C EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; +}; + +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hdmi { + vdda_video-supply = <&ldo2_reg>; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi --- a/arch/arm/boot/dts/dra72x.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra72x.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -28,11 +28,59 @@ }; }; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; interrupts = ; }; + + ocp { + cal: cal@4845b000 { + compatible = "ti,dra72-cal"; + ti,hwmods = "cal"; + reg = <0x4845B000 0x400>, + <0x4845B800 0x40>, + <0x4845B900 0x40>, + <0x4A002e94 0x4>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1", + "camerrx_control"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + }; +}; + +&scm { + dra72_vip_mux: pinmux@4a002e8c { + compatible = "pinctrl-single"; + reg = <0xe8c 0x4>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; }; &dss { @@ -46,6 +94,32 @@ clock-names = "fck", "video1_clk"; }; +&mailbox3 { + mbox_pru1_0: mbox_pru1_0 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + status = "disabled"; + }; + mbox_pru1_1: mbox_pru1_1 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + status = "disabled"; + }; +}; + +&mailbox4 { + mbox_pru2_0: mbox_pru2_0 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + status = "disabled"; + }; + mbox_pru2_1: mbox_pru2_1 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + status = "disabled"; + }; +}; + &mailbox5 { mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { ti,mbox-tx = <6 2 2>; diff -Naur --no-dereference a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi --- a/arch/arm/boot/dts/dra74x.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra74x.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -44,6 +44,13 @@ }; }; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + rproc3 = &dsp2; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; @@ -101,6 +108,111 @@ ti,syscon-mmuconfig = <&dsp2_system 0x1>; status = "disabled"; }; + + dsp2: dsp@41000000 { + compatible = "ti,dra7-dsp"; + reg = <0x41000000 0x48000>, + <0x41600000 0x8000>, + <0x41700000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,hwmods = "dsp2"; + syscon-bootreg = <&scm_conf 0x560>; + iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; + ti,rproc-standby-info = <0x4a005620>; + status = "disabled"; + }; + + vip2: vip@0x48990000 { + compatible = "ti,vip2"; + reg = <0x48990000 0x114>, + <0x48995500 0xD8>, + <0x48995700 0x18>, + <0x48995800 0x80>, + <0x48995a00 0xD8>, + <0x48995c00 0x18>, + <0x48995d00 0x80>, + <0x4899d000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + ti,hwmods = "vip2"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + vin3a: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + }; + vin4a: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + }; + vin3b: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + status = "disabled"; + }; + vin4b: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + status = "disabled"; + }; + }; + + vip3: vip@0x489b0000 { + compatible = "ti,vip3"; + reg = <0x489b0000 0x114>, + <0x489b5500 0xD8>, + <0x489b5700 0x18>, + <0x489b5800 0x80>, + <0x489b5a00 0xD8>, + <0x489b5c00 0x18>, + <0x489b5d00 0x80>, + <0x489bd000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + ti,hwmods = "vip3"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + vin5a: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + }; + vin6a: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + }; + }; }; }; @@ -108,8 +220,8 @@ reg = <0x58000000 0x80>, <0x58004054 0x4>, <0x58004300 0x20>, - <0x58005054 0x4>, - <0x58005300 0x20>; + <0x58009054 0x4>, + <0x58009300 0x20>; reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2"; @@ -119,6 +231,32 @@ clock-names = "fck", "video1_clk", "video2_clk"; }; +&mailbox3 { + mbox_pru1_0: mbox_pru1_0 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + status = "disabled"; + }; + mbox_pru1_1: mbox_pru1_1 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + status = "disabled"; + }; +}; + +&mailbox4 { + mbox_pru2_0: mbox_pru2_0 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + status = "disabled"; + }; + mbox_pru2_1: mbox_pru2_1 { + ti,mbox-tx = <2 0 0>; + ti,mbox-rx = <3 0 0>; + status = "disabled"; + }; +}; + &mailbox5 { mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { ti,mbox-tx = <6 2 2>; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi --- a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,27 @@ +/* + * Device Tree Source for DRA7x SoC DSPEVE thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +dspeve_thermal: dspeve_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 3>; + + trips { + dspeve_crit: dspeve_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi --- a/arch/arm/boot/dts/dra7.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra7.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -15,8 +15,8 @@ #define MAX_SOURCES 400 / { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "ti,dra7xx"; interrupt-parent = <&crossbar_mpu>; @@ -56,10 +56,10 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>, - <0x48214000 0x2000>, - <0x48216000 0x2000>; + reg = <0x0 0x48211000 0x0 0x1000>, + <0x0 0x48212000 0x0 0x1000>, + <0x0 0x48214000 0x0 0x2000>, + <0x0 0x48216000 0x0 0x2000>; interrupts = ; interrupt-parent = <&gic>; }; @@ -68,7 +68,7 @@ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; + reg = <0x0 0x48281000 0x0 0x1000>; interrupt-parent = <&gic>; }; @@ -95,10 +95,10 @@ compatible = "ti,dra7-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x0 0x0 0xc0000000>; ti,hwmods = "l3_main_1", "l3_main_2"; - reg = <0x44000000 0x1000000>, - <0x45000000 0x1000>; + reg = <0x0 0x44000000 0x0 0x1000000>, + <0x0 0x45000000 0x0 0x1000>; interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; @@ -155,6 +155,29 @@ compatible = "syscon"; reg = <0x1c04 0x0020>; }; + + scm_conf_pcie: scm_conf@1c24 { + compatible = "syscon"; + reg = <0x1c24 0x0024>; + }; + + sdma_xbar: dma-router@b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xb78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; + + edma_xbar: dma-router@c78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xc78 0x7c>; + #dma-cells = <2>; + dma-requests = <204>; + ti,dma-safe-map = <0>; + dma-masters = <&edma>; + }; }; cm_core_aon: cm_core_aon@5000 { @@ -280,6 +303,53 @@ }; }; + ocmcram1: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x80000>; + ranges = <0x0 0x40300000 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + /* + * This is a placeholder for an optional reserved + * region for use by secure software. The size + * of this region is not known until runtime so it + * is set as zero to either be updated to reserve + * space or left unchanged to leave all SRAM for use. + * On HS parts that that require the reserved region + * either the bootloader can update the size to + * the required amount or the node can be overriden + * from the board dts file for the secure platform. + */ + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0x0>; + }; + }; + + /* + * NOTE: ocmcram2 and ocmcram3 are not available on all + * DRA7xx and AM57xx variants. Confirm availability in + * the data manual for the exact part number in use + * before enabling these nodes in the board dts file. + */ + ocmcram2: ocmcram@40400000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40400000 0x100000>; + ranges = <0x0 0x40400000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + ocmcram3: ocmcram@40500000 { + status = "disabled"; + compatible = "mmio-sram"; + reg = <0x40500000 0x100000>; + ranges = <0x0 0x40500000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc @@ -297,6 +367,13 @@ reg = <0x40d00000 0x100>; }; + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -309,13 +386,43 @@ dma-requests = <127>; }; - sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; + edma: edma@43300000 { + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x43300000 0x100000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <20 21>; + * for example. Note that these channels need to be + * masked in the xbar as well. + */ + }; + + edma_tptc0: tptc@43400000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x43400000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@43500000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x43500000 0x100000>; + interrupts = ; + interrupt-names = "edma3_tcerrint"; }; gpio1: gpio@4ae10000 { @@ -413,7 +520,7 @@ ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; + dmas = <&edma_xbar 49 0>, <&edma_xbar 50 0>; dma-names = "tx", "rx"; }; @@ -424,7 +531,7 @@ ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; + dmas = <&edma_xbar 51 0>, <&edma_xbar 52 0>; dma-names = "tx", "rx"; }; @@ -435,7 +542,7 @@ ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; + dmas = <&edma_xbar 53 0>, <&edma_xbar 54 0>; dma-names = "tx", "rx"; }; @@ -446,7 +553,7 @@ ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; + dmas = <&edma_xbar 55 0>, <&edma_xbar 56 0>; dma-names = "tx", "rx"; }; @@ -457,7 +564,7 @@ ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; + dmas = <&edma_xbar 63 0>, <&edma_xbar 64 0>; dma-names = "tx", "rx"; }; @@ -468,7 +575,7 @@ ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; - dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; + dmas = <&edma_xbar 79 0>, <&edma_xbar 80 0>; dma-names = "tx", "rx"; }; @@ -767,6 +874,15 @@ ti,hwmods = "timer11"; }; + timer12: timer@4ae20000 { + compatible = "ti,omap5430-timer"; + reg = <0x4ae20000 0x80>; + interrupts = ; + ti,hwmods = "timer12"; + ti,timer-alwon; + ti,timer-secure; + }; + timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>; @@ -820,6 +936,50 @@ ti,hwmods = "dmm"; }; + ipu1: ipu@58820000 { + compatible = "ti,dra7-ipu"; + reg = <0x58820000 0x10000>; + reg-names = "l2ram"; + ti,hwmods = "ipu1"; + iommus = <&mmu_ipu1>; + ti,rproc-standby-info = <0x4a005520>; + status = "disabled"; + }; + + ipu2: ipu@55020000 { + compatible = "ti,dra7-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + ti,hwmods = "ipu2"; + iommus = <&mmu_ipu2>; + ti,rproc-standby-info = <0x4a008920>; + status = "disabled"; + }; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,hwmods = "dsp1"; + syscon-bootreg = <&scm_conf 0x55c>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + ti,rproc-standby-info = <0x4a005420>; + status = "disabled"; + }; + + sgx: sgx@0x56000000 { + compatible = "ti,dra7-sgx544", "img,sgx544"; + reg = <0x5600fe00 0x200>; + reg-names = "gpu_ocp_base"; + interrupts = ; + ti,hwmods = "gpu"; + clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>, + <&gpu_hyd_gclk_mux>; + clock-names = "iclk", "fclk1", "fclk2"; + }; + i2c1: i2c@48070000 { compatible = "ti,omap4-i2c"; reg = <0x48070000 0x100>; @@ -871,7 +1031,7 @@ }; mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = ; ti,hwmods = "mmc1"; @@ -881,10 +1041,15 @@ dma-names = "tx", "rx"; status = "disabled"; pbias-supply = <&pbias_mmc_reg>; + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr25; + sd-uhs-sdr12; }; mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = ; ti,hwmods = "mmc2"; @@ -892,10 +1057,14 @@ dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; dma-names = "tx", "rx"; status = "disabled"; + sd-uhs-sdr25; + sd-uhs-sdr12; + mmc-hs200-1_8v; + mmc-ddr-1_8v; }; mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = ; ti,hwmods = "mmc3"; @@ -903,10 +1072,13 @@ dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; dma-names = "tx", "rx"; status = "disabled"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; }; mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = ; ti,hwmods = "mmc4"; @@ -914,6 +1086,8 @@ dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; dma-names = "tx", "rx"; status = "disabled"; + sd-uhs-sdr12; + sd-uhs-sdr25; }; mmu0_dsp1: mmu@40d01000 { @@ -956,6 +1130,134 @@ status = "disabled"; }; + pruss1: pruss@4b200000 { + compatible = "ti,am5728-pruss"; + ti,hwmods = "pruss1"; + reg = <0x4b200000 0x2000>, + <0x4b202000 0x2000>, + <0x4b210000 0x8000>, + <0x4b220000 0x2000>, + <0x4b226000 0x2000>, + <0x4b22e000 0x31c>, + <0x4b232000 0x58>; + reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg", + "iep", "mii_rt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pruss1_intc: intc@4b220000 { + compatible = "ti,am5728-pruss-intc"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru1_0: pru0@4b234000 { + compatible = "ti,am5728-pru"; + reg = <0x4b234000 0x3000>, + <0x4b222000 0x400>, + <0x4b222400 0x100>; + reg-names = "iram", "control", "debug"; + status = "disabled"; + }; + + pru1_1: pru1@4b238000 { + compatible = "ti,am5728-pru"; + reg = <0x4b238000 0x3000>, + <0x4b224000 0x400>, + <0x4b224400 0x100>; + reg-names = "iram", "control", "debug"; + status = "disabled"; + }; + + pruss1_mdio: mdio@4b232400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x4b232400 0x90>; + status = "disabled"; + }; + }; + + pruss2: pruss@4b280000 { + compatible = "ti,am5728-pruss"; + ti,hwmods = "pruss2"; + reg = <0x4b280000 0x2000>, + <0x4b282000 0x2000>, + <0x4b290000 0x8000>, + <0x4b2a0000 0x2000>, + <0x4b2a6000 0x2000>, + <0x4b2ae000 0x31c>, + <0x4b2b2000 0x58>; + reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg", + "iep", "mii_rt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pruss2_intc: intc@4b2a0000 { + compatible = "ti,am5728-pruss-intc"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru2_0: pru0@4b2b4000 { + compatible = "ti,am5728-pru"; + reg = <0x4b2b4000 0x3000>, + <0x4b2a2000 0x400>, + <0x4b2a2400 0x100>; + reg-names = "iram", "control", "debug"; + status = "disabled"; + }; + + pru2_1: pru1@4b2b8000 { + compatible = "ti,am5728-pru"; + reg = <0x4b2b8000 0x3000>, + <0x4b2a4000 0x400>, + <0x4b2a4400 0x100>; + reg-names = "iram", "control", "debug"; + status = "disabled"; + }; + + pruss2_mdio: mdio@4b2b2400 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&dpll_gmac_h13x2_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + reg = <0x4b2b2400 0x90>; + status = "disabled"; + }; + }; + abb_mpu: regulator-abb-mpu { compatible = "ti,abb-v3"; regulator-name = "abb_mpu"; @@ -1153,8 +1455,10 @@ qspi: qspi@4b300000 { compatible = "ti,dra7xxx-qspi"; - reg = <0x4b300000 0x100>; - reg-names = "qspi_base"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>; + reg-names = "qspi_base", "qspi_mmap"; + syscon-chipselects = <&scm_conf 0x558>; #address-cells = <1>; #size-cells = <0>; ti,hwmods = "qspi"; @@ -1165,14 +1469,6 @@ status = "disabled"; }; - omap_control_sata: control-phy@4a002374 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002374 0x4>; - reg-names = "power"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - }; - /* OCP2SCP3 */ ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp"; @@ -1187,7 +1483,7 @@ <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_sata>; + syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin1>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; @@ -1199,16 +1495,18 @@ reg = <0x4a094000 0x80>, /* phy_rx */ <0x4a094400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; - ctrl-module = <&omap_control_pcie1phy>; + syscon-phy-power = <&scm_conf_pcie 0x1c>; + syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&optfclk_pciephy1_32khz>, <&optfclk_pciephy1_clk>, <&optfclk_pciephy1_div_clk>, - <&optfclk_pciephy_div>; + <&optfclk_pciephy_div>, + <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", - "div-clk", "phy-div"; + "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; }; @@ -1217,16 +1515,18 @@ reg = <0x4a095000 0x80>, /* phy_rx */ <0x4a095400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; - ctrl-module = <&omap_control_pcie2phy>; + syscon-phy-power = <&scm_conf_pcie 0x20>; + syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&optfclk_pciephy2_32khz>, <&optfclk_pciephy2_clk>, <&optfclk_pciephy2_div_clk>, - <&optfclk_pciephy_div>; + <&optfclk_pciephy_div>, + <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", - "div-clk", "phy-div"; + "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; status = "disabled"; }; @@ -1242,23 +1542,6 @@ ti,hwmods = "sata"; }; - omap_control_pcie1phy: control-phy@0x4a003c40 { - compatible = "ti,control-phy-pcie"; - reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; - reg-names = "power", "control_sma", "pcie_pcs"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - }; - - omap_control_pcie2phy: control-pcie@0x4a003c44 { - compatible = "ti,control-phy-pcie"; - reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; - reg-names = "power", "control_sma", "pcie_pcs"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - status = "disabled"; - }; - rtc: rtc@48838000 { compatible = "ti,am3352-rtc"; reg = <0x48838000 0x100>; @@ -1268,24 +1551,6 @@ clocks = <&sys_32k_ck>; }; - omap_control_usb2phy1: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usb3phy1: control-phy@4a002370 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002370 0x4>; - reg-names = "power"; - }; - - omap_control_usb2phy2: control-phy@0x4a002e74 { - compatible = "ti,control-phy-usb2-dra7"; - reg = <0x4a002e74 0x4>; - reg-names = "power"; - }; - /* OCP2SCP1 */ ocp2scp@4a080000 { compatible = "ti,omap-ocp2scp"; @@ -1296,9 +1561,9 @@ ti,hwmods = "ocp2scp1"; usb2_phy1: phy@4a084000 { - compatible = "ti,omap-usb2"; + compatible = "ti,dra7x-usb2", "ti,omap-usb2"; reg = <0x4a084000 0x400>; - ctrl-module = <&omap_control_usb2phy1>; + syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, <&usb_otg_ss1_refclk960m>; clock-names = "wkupclk", @@ -1307,9 +1572,10 @@ }; usb2_phy2: phy@4a085000 { - compatible = "ti,omap-usb2"; + compatible = "ti,dra7x-usb2-phy2", + "ti,omap-usb2"; reg = <0x4a085000 0x400>; - ctrl-module = <&omap_control_usb2phy2>; + syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, <&usb_otg_ss2_refclk960m>; clock-names = "wkupclk", @@ -1323,7 +1589,7 @@ <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb3phy1>; + syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, <&usb_otg_ss1_refclk960m>; @@ -1435,6 +1701,10 @@ gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; @@ -1449,21 +1719,136 @@ status = "disabled"; }; + mcasp1: mcasp@48460000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x48460000 0x2000>, + <0x45800000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, + <&mcasp1_ahclkr_mux>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + + mcasp2: mcasp@48464000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp2"; + reg = <0x48464000 0x2000>, + <0x45c00000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, + <&mcasp2_ahclkr_mux>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + mcasp3: mcasp@48468000 { compatible = "ti,dra7-mcasp-audio"; ti,hwmods = "mcasp3"; - reg = <0x48468000 0x2000>; - reg-names = "mpu"; + reg = <0x48468000 0x2000>, + <0x46000000 0x1000>; + reg-names = "mpu","dat"; interrupts = , ; interrupt-names = "tx", "rx"; - dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; + dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; clock-names = "fck", "ahclkx"; status = "disabled"; }; + mcasp4: mcasp@4846c000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp4"; + reg = <0x4846c000 0x2000>, + <0x48436000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp5: mcasp@48470000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp5"; + reg = <0x48470000 0x2000>, + <0x4843a000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp6: mcasp@48474000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp6"; + reg = <0x48474000 0x2000>, + <0x4844c000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp7: mcasp@48478000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp7"; + reg = <0x48478000 0x2000>, + <0x48450000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp8: mcasp@4847c000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp8"; + reg = <0x4847c000 0x2000>, + <0x48454000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + crossbar_mpu: crossbar@4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; @@ -1602,14 +1987,233 @@ ti,hwmods = "dss_hdmi"; clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; clock-names = "fck", "sys_clk"; + dmas = <&sdma_xbar 76>; + dma-names = "audio_tx"; + }; + }; + + vpe { + compatible = "ti,vpe"; + ti,hwmods = "vpe"; + clocks = <&dpll_core_h23x2_ck>; + clock-names = "fck"; + reg = <0x489d0000 0x120>, + <0x489d0300 0x20>, + <0x489d0400 0x20>, + <0x489d0500 0x20>, + <0x489d0600 0x3c>, + <0x489d0700 0x80>, + <0x489d5700 0x18>, + <0x489dd000 0x400>; + reg-names = "vpe_top", + "vpe_chr_us0", + "vpe_chr_us1", + "vpe_chr_us2", + "vpe_dei", + "sc", + "csc", + "vpdma"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; + + vip1: vip@0x48970000 { + compatible = "ti,vip1"; + reg = <0x48970000 0x114>, + <0x48975500 0xD8>, + <0x48975700 0x18>, + <0x48975800 0x80>, + <0x48975a00 0xD8>, + <0x48975c00 0x18>, + <0x48975d00 0x80>, + <0x4897d000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + ti,hwmods = "vip1"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + vin1a: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + }; + vin2a: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + }; + vin1b: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + status = "disabled"; + }; + vin2b: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + status = "disabled"; + }; + }; + + epwmss0: epwmss@4843e000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm0: pwm@4843e200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap0: ecap@4843e100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48440000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48440000 0x30>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm1: pwm@48440200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm1_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap1: ecap@48440100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48440100 0x80>; + status = "disabled"; }; }; + + epwmss2: epwmss@48442000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48442000 0x30>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm2: pwm@48442200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48442200 0x80>; + clocks = <&ehrpwm2_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap2: ecap@48442100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48442100 0x80>; + status = "disabled"; + }; + }; + + aes1: aes@4b500000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes1"; + reg = <0x4b500000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + aes2: aes@4b700000 { + compatible = "ti,omap4-aes"; + ti,hwmods = "aes2"; + reg = <0x4b700000 0xa0>; + interrupts = ; + dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + des: des@480a5000 { + compatible = "ti,omap4-des"; + ti,hwmods = "des"; + reg = <0x480a5000 0xa0>; + interrupts = ; + dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; + dma-names = "tx", "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + sham: sham@53100000 { + compatible = "ti,omap5-sham"; + ti,hwmods = "sham"; + reg = <0x4b101000 0x300>; + interrupts = ; + dmas = <&edma_xbar 119 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + + rng: rng@48090000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48090000 0x2000>; + interrupts = ; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; }; thermal_zones: thermal-zones { #include "omap4-cpu-thermal.dtsi" #include "omap5-gpu-thermal.dtsi" #include "omap5-core-thermal.dtsi" + #include "dra7-dspeve-thermal.dtsi" + #include "dra7-iva-thermal.dtsi" }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts --- a/arch/arm/boot/dts/dra7-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra7-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -18,7 +18,45 @@ memory { device_type = "memory"; - reg = <0x80000000 0x60000000>; /* 1536 MB */ + reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + + aliases { + display0 = &hdmi0; }; evm_3v3_sd: fixedregulator-sd { @@ -33,6 +71,7 @@ evm_3v3_sw: fixedregulator-evm_3v3_sw { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sw"; + vin-supply = <&sysen1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -46,6 +85,16 @@ regulator-max-microvolt = <1800000>; }; + vmmcwl_fixed: fixedregulator-mmcwl { + compatible = "regulator-fixed"; + regulator-name = "vmmcwl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio5 8 0>; /* gpio5_8 */ + startup-delay-us = <70000>; + enable-active-high; + }; + extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; @@ -64,6 +113,7 @@ regulator-always-on; regulator-boot-on; enable-active-high; + vin-supply = <&sysen2>; gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; }; @@ -146,265 +196,427 @@ gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; }; }; + + hdmi0: connector@1 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder@1 { + compatible = "ti,dra7evm-tpd12s015"; + + pinctrl-names = "i2c", "ddc"; + pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>; + pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>; + + ddc-i2c-bus = <&i2c2>; + mcasp-gpio = <&mcasp8>; + + gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 0>, /* P5, LS OE */ + <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &dra7_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&vtt_pin>; - - vtt_pin: pinmux_vtt_pin { + dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < - 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ >; }; - i2c1_pins: pinmux_i2c1_pins { + dcan1_pins_sleep: dcan1_pins_sleep { pinctrl-single,pins = < - 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ - 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ >; }; - i2c2_pins: pinmux_i2c2_pins { + hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin { pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ - 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + /* this pin is used as a GPIO via mcasp */ + 0x2fc (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */ >; }; - i2c3_pins: pinmux_i2c3_pins { + hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default { pinctrl-single,pins = < - 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ - 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ + 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ + 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ >; }; - mcspi1_pins: pinmux_mcspi1_pins { + hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc { pinctrl-single,pins = < - 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */ - 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */ - 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */ - 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ - 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ - 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ + 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ >; }; - mcspi2_pins: pinmux_mcspi2_pins { + mmc1_pins_default: pinmux_mmc1_default_pins { pinctrl-single,pins = < - 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */ - 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ - 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - uart1_pins: pinmux_uart1_pins { + mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins { pinctrl-single,pins = < - 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ - 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ - 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ - 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - uart2_pins: pinmux_uart2_pins { + mmc1_pins_hs: pinmux_mmc1_hs_pins { pinctrl-single,pins = < - 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */ - 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */ - 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ - 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - uart3_pins: pinmux_uart3_pins { + mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins { pinctrl-single,pins = < - 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ - 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - qspi1_pins: pinmux_qspi1_pins { + mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins { pinctrl-single,pins = < - 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ - 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ - 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ + 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - nand_flash_x16: nand_flash_x16 { - /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch - * So NAND flash requires following switch settings: - * SW5.9 (GPMC_WPN) = LOW - * SW5.1 (NAND_BOOTn) = HIGH */ + mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins { pinctrl-single,pins = < - 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ + 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ >; }; - cpsw_default: cpsw_default { + mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins { pinctrl-single,pins = < - /* Slave 1 */ - 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ - 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ - 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ - 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ - 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ - 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ - 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ - 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ - 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ - 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ - 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ - 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ - - /* Slave 2 */ - 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */ >; + }; + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; }; - cpsw_sleep: cpsw_sleep { + mmc2_pins_hs: mmc2_pins_hs { pinctrl-single,pins = < - /* Slave 1 */ - 0x250 (MUX_MODE15) - 0x254 (MUX_MODE15) - 0x258 (MUX_MODE15) - 0x25c (MUX_MODE15) - 0x260 (MUX_MODE15) - 0x264 (MUX_MODE15) - 0x268 (MUX_MODE15) - 0x26c (MUX_MODE15) - 0x270 (MUX_MODE15) - 0x274 (MUX_MODE15) - 0x278 (MUX_MODE15) - 0x27c (MUX_MODE15) + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; - /* Slave 2 */ - 0x198 (MUX_MODE15) - 0x19c (MUX_MODE15) - 0x1a0 (MUX_MODE15) - 0x1a4 (MUX_MODE15) - 0x1a8 (MUX_MODE15) - 0x1ac (MUX_MODE15) - 0x1b0 (MUX_MODE15) - 0x1b4 (MUX_MODE15) - 0x1b8 (MUX_MODE15) - 0x1bc (MUX_MODE15) - 0x1c0 (MUX_MODE15) - 0x1c4 (MUX_MODE15) + mmc2_pins_ddr_1_8v: pinmux_mmc2_ddr_1_8v_pins { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - davinci_mdio_default: davinci_mdio_default { + mmc2_pins_hs200_1_8v: mmc2_pins_hs200_1_8v { pinctrl-single,pins = < - 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; +}; - davinci_mdio_sleep: davinci_mdio_sleep { +&dra7_iodelay_core { + mmc1_iodelay_ddr50_rev11_conf: mmc1_iodelay_ddr50_rev11_conf { pinctrl-single,pins = < - 0x23c (MUX_MODE15) - 0x240 (MUX_MODE15) + 0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */ + 0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */ + 0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */ + 0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */ + 0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */ + 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ + 0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ >; }; - dcan1_pins_default: dcan1_pins_default { + mmc1_iodelay_ddr50_rev20_conf: mmc1_iodelay_ddr50_rev20_conf { pinctrl-single,pins = < - 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */ + 0x620 (A_DELAY(1271) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */ + 0x624 (A_DELAY(229) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x630 (A_DELAY(850) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(20) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x63C (A_DELAY(468) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x648 (A_DELAY(466) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */ + 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x654 (A_DELAY(399) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ >; }; - dcan1_pins_sleep: dcan1_pins_sleep { + mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf { pinctrl-single,pins = < - 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ + 0x620 (A_DELAY(1063) | G_DELAY(17)) /* CFG_MMC1_CLK_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62c (A_DELAY(23) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(2) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ >; }; - atl_pins: pinmux_atl_pins { + mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf { pinctrl-single,pins = < - 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ + 0x620 (A_DELAY(600) | G_DELAY(400)) /* CFG_MMC1_CLK_OUT */ + 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */ + 0x62c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */ + 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */ + 0x638 (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */ + 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */ + 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */ + 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */ + 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */ + 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */ + 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */ >; }; - mcasp3_pins: pinmux_mcasp3_pins { + mmc2_iodelay_hs200_1_8v_rev11_conf: mmc2_iodelay_hs200_1_8v_rev11_conf { + pinctrl-single,pins = < + 0x190 (A_DELAY(621) | G_DELAY(600)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(300) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(739) | G_DELAY(600)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(812) | G_DELAY(600)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(240) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(954) | G_DELAY(600)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(1340)| G_DELAY(420)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(935) | G_DELAY(600)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(525) | G_DELAY(600)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(767) | G_DELAY(600)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(225) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(565) | G_DELAY(600)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(60) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(969) | G_DELAY(600)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(180) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + >; + }; + + mmc2_iodelay_hs200_1_8v_rev20_conf: mmc2_iodelay_hs200_1_8v_rev20_conf { + pinctrl-single,pins = < + 0x190 (A_DELAY(274) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(162) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(401) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(73) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(465) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(115) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(633) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(47) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(935) | G_DELAY(280)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(621) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(183) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(467) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(262) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(46) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(684) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(76) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ + >; + }; + + mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf { pinctrl-single,pins = < - 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ + 0x18c (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(274) | G_DELAY(240)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(514) | G_DELAY(360)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(187) | G_DELAY(120)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(0) | G_DELAY(60)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(121) | G_DELAY(60)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ >; }; - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { + mmc2_iodelay_ddr_1_8v_rev20_conf: mmc2_iodelay_ddr_1_8v_rev20_conf { pinctrl-single,pins = < - 0x324 (MUX_MODE15) - 0x328 (MUX_MODE15) - 0x32c (MUX_MODE15) - 0x330 (MUX_MODE15) + 0x18c (A_DELAY(270) | G_DELAY(0)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(170) | G_DELAY(0)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(758) | G_DELAY(0)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(81) | G_DELAY(0)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(286) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(123) | G_DELAY(0)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(346) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */ + 0x194 (A_DELAY(55) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */ + 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */ + 0x1ac (A_DELAY(422) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */ + 0x1b4 (A_DELAY(642) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */ + 0x1b8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */ + 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */ + 0x1c4 (A_DELAY(128) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */ + 0x1d0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */ + 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */ + 0x1dc (A_DELAY(395) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */ + 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */ + 0x1e8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */ + 0x1f0 (A_DELAY(623) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */ + 0x1f4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */ + 0x1fc (A_DELAY(54) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */ + 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */ + 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */ + 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */ >; }; }; &i2c1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; clock-frequency = <400000>; tps659038: tps659038@58 { @@ -428,7 +640,7 @@ /* VDD_DSPEVE */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; @@ -446,7 +658,7 @@ /* CORE_VDD */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; + regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; @@ -504,6 +716,7 @@ regulator-max-microvolt = <1050000>; regulator-always-on; regulator-boot-on; + regulator-allow-bypass; }; ldoln_reg: ldoln { @@ -522,6 +735,31 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; }; + + /* REGEN1 is unused */ + + regen2: regen2 { + /* Needed for PMIC internal resources */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + + /* REGEN3 is unused */ + + sysen1: sysen1 { + /* PMIC_REGEN_3V3 */ + regulator-name = "sysen1"; + regulator-boot-on; + regulator-always-on; + }; + + sysen2: sysen2 { + /* PMIC_REGEN_DDR */ + regulator-name = "sysen2"; + regulator-boot-on; + regulator-always-on; + }; }; }; }; @@ -567,8 +805,6 @@ &i2c2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; pcf_hdmi: gpio@26 { @@ -584,45 +820,48 @@ line-name = "vin6_sel_s0"; }; }; + + ov10633@37 { + compatible = "ovti,ov10633"; + reg = <0x37>; + + mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */ + port { + onboardLI: endpoint { + remote-endpoint = <&vin1a>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; }; &i2c3 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; clock-frequency = <400000>; }; &mcspi1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; }; &mcspi2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mcspi2_pins>; }; &uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3e0>; }; &uart2 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; }; &uart3 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; }; &mmc1 { @@ -635,12 +874,49 @@ * is always hardwired. */ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev11_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; + pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_rev20_conf>; + pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; }; &mmc2 { status = "okay"; vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; + max-frequency = <192000000>; + pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>; + pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>; + pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>; + pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>; +}; + +&mmc4 { + status = "okay"; + vmmc-supply = <&vmmcwl_fixed>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + ti,non-removable; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; }; &cpu0 { @@ -649,18 +925,14 @@ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; @@ -721,15 +993,11 @@ }; &usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; + dr_mode = "otg"; }; &usb2 { dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; }; &elm { @@ -738,11 +1006,14 @@ &gpmc { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_flash_x16>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; @@ -765,7 +1036,6 @@ gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length @@ -831,9 +1101,6 @@ &mac { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; dual_emac; }; @@ -849,12 +1116,6 @@ dual_emac_res_vlan = <2>; }; -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - &dcan1 { status = "ok"; pinctrl-names = "default", "sleep", "active"; @@ -864,9 +1125,6 @@ }; &atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - assigned-clocks = <&abe_dpll_sys_clk_mux>, <&atl_gfclk_mux>, <&dpll_abe_ck>, @@ -885,9 +1143,6 @@ &mcasp3 { #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clock-parents = <&atl_clkin2_ck>; @@ -900,6 +1155,13 @@ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mcasp8 { + /* not used for audio. only the AXR2 pin is used as GPIO */ + status = "okay"; }; &mailbox5 { @@ -921,3 +1183,85 @@ status = "okay"; }; }; + +&mmu0_dsp1 { + status = "okay"; +}; + +&mmu1_dsp1 { + status = "okay"; +}; + +&mmu0_dsp2 { + status = "okay"; +}; + +&mmu1_dsp2 { + status = "okay"; +}; + +&mmu_ipu1 { + status = "okay"; +}; + +&mmu_ipu2 { + status = "okay"; +}; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + timers = <&timer3>; + watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + timers = <&timer11>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + timers = <&timer5>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + timers = <&timer6>; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo3_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&vip1 { + status = "okay"; +}; + +&vin1a { + status = "okay"; + endpoint@0 { + slave-mode; + remote-endpoint = <&onboardLI>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7-evm-lcd-lg.dts b/arch/arm/boot/dts/dra7-evm-lcd-lg.dts --- a/arch/arm/boot/dts/dra7-evm-lcd-lg.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7-evm-lcd-lg.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra7-evm.dts" +#include "dra7x-evm-lcd-lg.dtsi" diff -Naur --no-dereference a/arch/arm/boot/dts/dra7-evm-lcd-osd.dts b/arch/arm/boot/dts/dra7-evm-lcd-osd.dts --- a/arch/arm/boot/dts/dra7-evm-lcd-osd.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7-evm-lcd-osd.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "dra7-evm.dts" +#include "dra7x-evm-lcd-osd.dtsi" + +&touchscreen { + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi --- a/arch/arm/boot/dts/dra7-iva-thermal.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,27 @@ +/* + * Device Tree Source for DRA7x SoC IVA thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +iva_thermal: iva_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 4>; + + trips { + iva_crit: iva_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi --- a/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7x-evm-lcd-lg.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + aliases { + display0 = &tlc59108; + display1 = &hdmi0; + }; +}; + +&i2c1 { + /* TLC chip for LCD panel power and backlight */ + tlc59108: tlc59108@40 { + compatible = "ti,tlc59108-lp101"; + reg = <0x40>; + enable-gpios = <&pcf_lcd 13 GPIO_ACTIVE_LOW>; /* P15, CON_LCD_PWR_DN */ + + port { + tlc_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&tlc_in>; + data-lines = <24>; + }; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi --- a/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/dra7x-evm-lcd-osd.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + aliases { + display0 = &lcd; + display1 = &hdmi0; + }; + + backlight { + compatible = "led-backlight"; + leds = <&backlight_led>; + brightness-levels = <0 243 245 247 248 249 251 252 255>; + default-brightness-level = <8>; + + enable-gpios = <&pcf_lcd 13 GPIO_ACTIVE_LOW>; + }; + + lcd: display { + /* + * TODO: Not a DPI panel, but a dummy DSI video mode panel. + * This needs to be changed later when we can support DSI VM + * panels properly. + */ + compatible = "osd,osd101t2045-53ts", "panel-dpi"; + + label = "lcd"; + + panel-timing { + clock-frequency = <154000000>; + hactive = <1920>; + vactive = <1200>; + + hfront-porch = <112>; + hback-porch = <32>; + hsync-len = <16>; + + vfront-porch = <16>; + vback-porch = <16>; + vsync-len = <2>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&tc358768_out>; + }; + }; + }; + + tc358768_refclk: tc358768_refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; +}; + +&i2c1 { + tc358768@0e { + compatible = "toshiba,tc358768"; + reg = <0x0e>; + + clocks = <&tc358768_refclk>; + clock-names = "refclk"; + + reset-gpios = <&pcf_display_board 0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tc358768_in: endpoint { + remote-endpoint = <&dpi_out>; + data-lines = <24>; + }; + }; + + port@1 { + reg = <1>; + tc358768_out: endpoint { + remote-endpoint = <&lcd_in>; + lanes = <0 1 2 3 4 5 6 7 8 9>; + }; + }; + }; + }; + + tlc59108: tlc59116@40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x40>; + + backlight_led: bl@2 { + label = "backlight"; + reg = <0x2>; + }; + }; + + pcf_display_board: gpio@27 { + compatible = "nxp,pcf8575"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + }; + + touchscreen: edt-ft5506@38 { + status = "okay"; + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&pcf_display_board 5 GPIO_ACTIVE_HIGH>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&tc358768_in>; + data-lines = <24>; + }; + }; + + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -98,12 +98,20 @@ clock-frequency = <32768>; }; - sys_32k_ck: sys_32k_ck { + sys_clk32_crystal_ck: sys_clk32_crystal_ck { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; + sys_clk32_pseudo_ck: sys_clk32_pseudo_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_clkin1>; + clock-mult = <1>; + clock-div = <610>; + }; + virt_12000000_ck: virt_12000000_ck { #clock-cells = <0>; compatible = "fixed-clock"; @@ -330,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck { @@ -341,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -364,6 +376,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck { @@ -375,6 +389,8 @@ reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk { @@ -651,6 +667,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { @@ -783,6 +801,8 @@ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; ti,bit-shift = <24>; reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { @@ -1710,13 +1730,20 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; ti,bit-shift = <24>; reg = <0x13d0>; - ti,dividers = <2>; + }; + + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_gmac_m2_ck>; + clock-mult = <1>; + clock-div = <2>; }; gmac_rft_clk_mux: gmac_rft_clk_mux { @@ -1856,7 +1883,7 @@ reg = <0x1908>; }; - mcasp8_ahclk_mux: mcasp8_ahclk_mux { + mcasp8_ahclkx_mux: mcasp8_ahclkx_mux { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -2146,4 +2173,36 @@ ti,bit-shift = <0>; reg = <0x558>; }; + + sys_32k_ck: sys_32k_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>; + ti,bit-shift = <8>; + reg = <0x6c4>; + }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <20>; + reg = <0x0558>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <21>; + reg = <0x0558>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l4_root_clk_div>; + ti,bit-shift = <22>; + reg = <0x0558>; + }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi --- a/arch/arm/boot/dts/k2e-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2e-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,77 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Edison SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi --- a/arch/arm/boot/dts/k2e.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2e.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,150 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison soc device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = ; - dwc3@2690000 { - interrupts = ; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = ; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - dwc3@25010000 { - compatible = "synopsys,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = ; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 - 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - , - , - , - , - ; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2e-netcp.dtsi" - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts --- a/arch/arm/boot/dts/k2e-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2e-evm.dts 1969-12-31 19:00:00.000000000 -0500 @@ -1,154 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Edison EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - soc { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2e-netcp.dtsi b/arch/arm/boot/dts/k2e-netcp.dtsi --- a/arch/arm/boot/dts/k2e-netcp.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2e-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,229 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi --- a/arch/arm/boot/dts/k2hk-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,425 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi --- a/arch/arm/boot/dts/k2hk.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2hk.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,117 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking soc specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "k2hk-clocks.dtsi" - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@2620250 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@2620254 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@2620258 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@262025c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - - mdio: mdio@02090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2hk-netcp.dtsi" - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts --- a/arch/arm/boot/dts/k2hk-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2hk-evm.dts 1969-12-31 19:00:00.000000000 -0500 @@ -1,182 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 Kepler/Hawking EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - debug1_1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - debug1_2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - debug2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - debug3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2hk-netcp.dtsi b/arch/arm/boot/dts/k2hk-netcp.dtsi --- a/arch/arm/boot/dts/k2hk-netcp.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2hk-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,232 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi --- a/arch/arm/boot/dts/k2l-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2l-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,266 +0,0 @@ -/* - * Copyright 2013-2014 Texas Instruments, Inc. - * - * Keystone 2 lamarr SoC clock nodes - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi --- a/arch/arm/boot/dts/k2l.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2l.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,111 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr SoC specific device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/ { - compatible = "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr SoC"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - soc { - /include/ "k2l-clocks.dtsi" - - uart2: serial@02348400 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = ; - }; - - uart3: serial@02348800 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = ; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "k2l-netcp.dtsi" - }; -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts --- a/arch/arm/boot/dts/k2l-evm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2l-evm.dts 1969-12-31 19:00:00.000000000 -0500 @@ -1,131 +0,0 @@ -/* - * Copyright 2014 Texas Instruments, Inc. - * - * Keystone 2 Lamarr EVM device tree - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "k2l.dtsi" - -/ { - compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7FE80000>; - }; - }; - }; -}; - -&spi0 { - nor_flash: n25q128a11@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "ok"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/k2l-netcp.dtsi b/arch/arm/boot/dts/k2l-netcp.dtsi --- a/arch/arm/boot/dts/k2l-netcp.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/k2l-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 @@ -1,212 +0,0 @@ -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright 2015 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - accumulator { - acc-low-0 { - qrange = <480 32>; - accumulator = <0 47 16 2 50>; - interrupts = <0 226 0xf01>; - multi-queue; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; - - pdsps { - #address-cells = <1>; - #size-cells = <1>; - ranges; - pdsp0@0x2a10000 { - reg = <0x2a10000 0x1000 /*iram */ - 0x2a0f000 0x100 /*reg*/ - 0x2a0c000 0x3c8 /*intd */ - 0x2a20000 0x4000>; /*cmd*/ - id = <0>; - }; - }; - -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&clkosr>, <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi --- a/arch/arm/boot/dts/keystone.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/keystone.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -8,6 +8,7 @@ #include #include +#include #include "skeleton.dtsi" @@ -59,6 +60,14 @@ ; }; + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -72,6 +81,18 @@ reg = <0x02310000 0x200>; }; + psc: power-sleep-controller@02350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + + pscrst: psc-reset { + compatible = "syscon-reset"; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + devctrl: device-state-control@02620000 { compatible = "ti,keystone-devctrl", "syscon"; reg = <0x02620000 0x1000>; @@ -87,7 +108,7 @@ /include/ "keystone-clocks.dtsi" uart0: serial@02530c00 { - compatible = "ns16550a"; + compatible = "ti,keystone-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; @@ -97,7 +118,7 @@ }; uart1: serial@02531000 { - compatible = "ns16550a"; + compatible = "ti,keystone-uart", "ns16550a"; current-speed = <115200>; reg-shift = <2>; reg-io-width = <4>; @@ -276,6 +297,15 @@ ti,syscon-dev = <&devctrl 0x2a0>; }; + pcie0_phy: phy@2320000 { + #phy-cells = <0>; + compatible = "ti,keystone-serdes-pcie"; + reg = <0x02320000 0x4000>; + link-rate-kbps = <5000000>; + num-lanes = <2>; + status = "disabled"; + }; + pcie0: pcie@21800000 { compatible = "ti,keystone-pcie", "snps,dw-pcie"; clocks = <&clkpcie>; @@ -289,6 +319,7 @@ status = "disabled"; device_type = "pci"; num-lanes = <2>; + phys = <&pcie0_phy>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -321,5 +352,13 @@ ; }; }; + + ddr3edac: edac@21010000 { + compatible = "ti,keystone-ddr3-mc-edac"; + reg = <0x21010000 0x200>; + interrupts = ; + interrupt-parent = <&gic>; + status = "disabled"; + }; }; }; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi --- a/arch/arm/boot/dts/keystone-k2e-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,77 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Edison SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkusb1: clkusb1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "usb1"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie1"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi --- a/arch/arm/boot/dts/keystone-k2e.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2e.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,189 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison soc device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + compatible = "ti,k2e", "ti,keystone"; + model = "Texas Instruments Keystone 2 Edison SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + aliases { + rproc0 = &dsp0; + }; + + soc { + /include/ "keystone-k2e-clocks.dtsi" + + usb: usb@2680000 { + interrupts = ; + dwc3@2690000 { + interrupts = ; + }; + }; + + usb1_phy: usb_phy@2620750 { + compatible = "ti,keystone-usbphy"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2620750 24>; + status = "disabled"; + }; + + usb1: usb@25000000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x25000000 0x10000>; + clocks = <&clkusb1>; + clock-names = "usb"; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + + dwc3@25010000 { + compatible = "synopsys,dwc3"; + reg = <0x25010000 0x70000>; + interrupts = ; + usb-phy = <&usb1_phy>, <&usb1_phy>; + }; + }; + + psc: power-sleep-controller@02350000 { + pscrst: psc-reset { + dsp@0 { + reg = <0>; + reset-control = <0xa3c 8 RESET_ASSERT_CLEAR>; + reset-status = <0x83c 8 RESET_ASSERT_CLEAR>; + }; + }; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dsp0: dsp0 { + compatible = "ti,k2e-dsp"; + reg = <0x10800000 0x00080000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + pcie1_phy: phy@2326000 { + #phy-cells = <0>; + compatible = "ti,keystone-serdes-pcie"; + reg = <0x02326000 0x4000>; + link-rate-kbps = <5000000>; + num-lanes = <2>; + status = "disabled"; + }; + + pcie1: pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + + status = "disabled"; + device_type = "pci"; + num-lanes = <2>; + phys = <&pcie1_phy>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ + <0 0 0 2 &pcie_intc1 1>, /* INT B */ + <0 0 0 3 &pcie_intc1 2>, /* INT C */ + <0 0 0 4 &pcie_intc1 3>; /* INT D */ + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + }; + + mdio: mdio@24200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x24200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2e-netcp.dtsi" + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts --- a/arch/arm/boot/dts/keystone-k2e-evm.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,199 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Edison EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2e.dtsi" + +/ { + compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; + model = "Texas Instruments Keystone 2 Edison EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_cma_pool: dsp_common_cma_pool { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + }; + + dsp_common_mpm_area: dsp_reserved_mpm_area { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x20000000 0x00000000 0x20000000>; + no-map; + status = "okay"; + }; + }; + + soc { + + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-pass"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + }; + + ddr3edac: edac@21010000 { + status = "ok"; + }; + + mpm_mem: dspmem { + compatible = "ti,keystone-dsp-mem"; + reg = <0x0c000000 0x00200000>, + <0xa0000000 0x20000000>; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&gbe_serdes0 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&dsp0 { + memory-region = <&dsp_common_cma_pool>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi --- a/arch/arm/boot/dts/keystone-k2e-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,538 @@ +/* + * Device Tree Source for Keystone 2 Edison Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0x104 0 53 0x204 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + netcpx-tx { + qrange = <692 8>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <10240 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@0x2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x24186000 0x100>, + <0x24187000 0x2a0>, + <0x24188000 0xb60>, + <0x24186100 0x80>, + <0x24189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + ti,enable-all; + }; + + dma_xgbe: dma_xgbe@0 { + reg = <0x2fa1000 0x100>, + <0x2fa1400 0x200>, + <0x2fa1800 0x200>, + <0x2fa1c00 0x200>, + <0x2fa2000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +gbe_subsys: subsys@24200000 { + compatible = "syscon"; + reg = <0x24200000 0x100>; +}; + +gbe_serdes0: phy@232a000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x0232a000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +gbe_serdes1: phy@2324000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x02324000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcp: netcp@24000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x24000000 0x1000000>; + + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>; + clock-names = "pa_clk", "ethss_clk", "cpts_rft_clk"; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>, + <&dma_gbe 22>, + <&dma_gbe 23>, + <&dma_gbe 24>, + <&dma_gbe 25>, + <&dma_gbe 27>, + <&dma_gbe 28>, + <&dma_gbe 29>, + <&dma_gbe 30>, + <&dma_gbe 8>, + <&dma_gbe 9>, + <&dma_gbe 10>, + <&dma_gbe 11>, + <&dma_gbe 12>, + <&dma_gbe 13>, + <&dma_gbe 14>, /* for egress cluster */ + <&dma_gbe 31>; + + ti,navigator-dma-names = "netrx0", + "netrx1", + "nettx", + "netrx0-pa", + "netrx1-pa", + "netrx2-pa", + "netrx3-pa", + "netrx4-pa", + "netrx5-pa", + "netrx6-pa", + "netrx7-pa", + "pa-cl0", + "pa-cl1", + "pa-cl2", + "pa-cl3", + "pa-cl4", + "pa-cl5", + "pa-cl6", + "pa-cmd-rsp"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-9"; + syscon-subsys = <&gbe_subsys>; + reg = <0x200100 0x800>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + phys = <&gbe_serdes0>, <&gbe_serdes1>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + port-4 { + slave-port = <4>; + link-interface = <2>; + }; + port-5 { + slave-port = <5>; + link-interface = <2>; + }; + port-6 { + slave-port = <6>; + link-interface = <2>; + }; + port-7 { + slave-port = <7>; + link-interface = <2>; + }; + }; + }; + + pa@0 { + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-pa2"; + compatible = "ti,netcp-pa2"; + + reg = <0 0x100>, /* Mailbox */ + <0x400 0x40>, /* RA bridge */ + <0x500 0x80>, /* thread mapper */ + <0x800 0x1000>, /* RA */ + <0x6000 0x100>, /* Statistics regs */ + <0x8000 0x100>, /* Statistics block */ + <0x400000 0x900000>; /* cluster memory */ + + mac-lut-ranges = <0 43 56 63>; + /* Static reservation in LUT-1 (outer IP) + * used by driver to add IP rules for Rx checksum + * offload. + */ + rx-route = <528 22>; + tx-cmd-pool = <256 12>; + /* rx command pool */ + rx-cmd-rsp-pool = <256 12>; + /* rx channel name for command response */ + rx-cmd-rsp-chan = "pa-cmd-rsp"; + rx-cmd-rsp-queue-depth = <128 32 0 0>; + rx-cmd-rsp-buffer-size = <128 512 0 0>; + + /* rx channels get overridden for the interface + * when PA is enabled + */ + interfaces { + pa0: interface-0 { + slave-port = <0>; + rx-channel = "netrx0-pa"; + }; + + pa1: interface-1 { + slave-port = <1>; + rx-channel = "netrx1-pa"; + }; + }; + + /* PA clusters that does packet processing */ + clusters { + #address-cells = <1>; + #size-cells = <0>; + cluster@0 { + reg = <0>; + tx-queue = <904>; + tx-channel = "pa-cl0"; + }; + + cluster@1 { + reg = <1>; + tx-queue = <905>; + tx-channel = "pa-cl1"; + }; + + cluster@6 { + reg = <6>; + tx-queue = <910>; + tx-channel = "pa-cl6"; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + netcp-pa2 = <&pa0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 00]; + netcp-gbe = <&gbe1>; + netcp-pa2 = <&pa1>; + }; + }; +}; + +xgbe_subsys: subsys@2f00000 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00000 0x100>; +}; + +xgbe_pcsr: pcsr@2f00600 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00600 0x100>; +}; + +xgbe_serdes: phy@231e000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-xgbe"; + reg = <0x0231e000 0x2000>; + link-rate-kbps = <10312500>; + num-lanes = <2>; + syscon-peripheral = <&xgbe_subsys>; + syscon-link = <&xgbe_pcsr>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcpx: netcpx@2f00000 { + status = "disabled"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&clkxge>; + clock-names = "xge_clk"; + dma-coherent; + /* big-endian; */ + + ti,navigator-dmas = <&dma_xgbe 0>, + <&dma_xgbe 8>, + <&dma_xgbe 0>; + ti,navigator-dma-names = "xnetrx0", "xnetrx1", "xnettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + xgbe@2f00000 { + label = "netcp-xgbe"; + compatible = "ti,netcp-xgbe"; + syscon-subsys = <&xgbe_subsys>; + syscon-pcsr = <&xgbe_pcsr>; + reg = <0x02f00100 0x200>, <0x02f01000 0xb00>; + /* enable-ale; */ + tx-queue = <692>; + tx-channel = "xnettx"; + phys = <&xgbe_serdes>; + + interfaces { + xgbe0: interface-0 { + slave-port = <0>; + link-interface = <11>; /* MAC_MAC */ + }; + xgbe1: interface-1 { + slave-port = <1>; + link-interface = <11>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "xnetrx0"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <532>; + tx-completion-queue = <534>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe0>; + + }; + interface-1 { + rx-channel = "xnetrx1"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <533>; + tx-completion-queue = <535>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe1>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi --- a/arch/arm/boot/dts/keystone-k2g.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2g.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,692 @@ +/* + * Device Tree Source for K2G SOC + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + compatible = "ti,k2g","ti,keystone"; + model = "Texas Instruments K2G SoC"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + usb0 = &usb0; + usb1 = &usb1; + phy0 = &usb0_phy; + phy1 = &usb1_phy; + d_can0 = &dcan0; + d_can1 = &dcan1; + rproc0 = &dsp0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + }; + + gic: interrupt-controller@02561000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02561000 0x0 0x1000>, + <0x0 0x02562000 0x0 0x2000>, + <0x0 0x02564000 0x0 0x1000>, + <0x0 0x02566000 0x0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = + , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = ; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,keystone","simple-bus"; + ranges = <0x0 0x0 0x0 0xc0000000>; + dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; + + devctrl: device-state-control@02620000 { + compatible = "ti,keystone-devctrl", "syscon"; + reg = <0x02620000 0x1000>; + }; + + k2g_pinctrl: pinmux@02621000 { + compatible = "pinctrl-single"; + reg = <0x02621000 0x410>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x001b0007>; + }; + + uart0: serial@02530c00 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + interrupts = ; + clocks = <&k2g_clks K2G_DEV_UART0 K2G_DEV_UART_CBA_CLK_PI>; + clock-names = "fck"; + + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_UART0>; + }; + + uart1: serial@02531000 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_UART1>; + clocks = <&k2g_clks K2G_DEV_UART1 K2G_DEV_UART_CBA_CLK_PI>; + clock-names = "fck"; + }; + + uart2: serial@02531400 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531400 0x100>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_UART2>; + clocks = <&k2g_clks K2G_DEV_UART2 K2G_DEV_UART_CBA_CLK_PI>; + clock-names = "fck"; + }; + + i2c0: i2c@2530000 { + compatible = "ti,davinci-i2c"; + reg = <0x02530000 0x400>; + clock-frequency = <100000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_I2C0>; + clocks = <&k2g_clks K2G_DEV_I2C0 K2G_DEV_I2C_VBUS_CLK>; + clock-names = "fck"; + }; + + i2c1: i2c@2530400 { + compatible = "ti,davinci-i2c"; + reg = <0x02530400 0x400>; + clock-frequency = <100000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_I2C1>; + clocks = <&k2g_clks K2G_DEV_I2C1 K2G_DEV_I2C_VBUS_CLK>; + clock-names = "fck"; + }; + + i2c2: i2c@2530800 { + compatible = "ti,davinci-i2c"; + reg = <0x02530800 0x400>; + clock-frequency = <100000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_I2C2>; + clocks = <&k2g_clks K2G_DEV_I2C2 K2G_DEV_I2C_VBUS_CLK>; + clock-names = "fck"; + }; + + spi0: spi@21805400 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_SPI0>; + clocks = <&k2g_clks K2G_DEV_SPI0 K2G_DEV_SPI_VBUSP_CLK>; + clock-names = "fck"; + }; + + spi1: spi@21805800 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_SPI1>; + clocks = <&k2g_clks K2G_DEV_SPI1 K2G_DEV_SPI_VBUSP_CLK>; + clock-names = "fck"; + }; + + spi2: spi@21805c00 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805C00 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_SPI2>; + clocks = <&k2g_clks K2G_DEV_SPI2 K2G_DEV_SPI_VBUSP_CLK>; + clock-names = "fck"; + }; + + spi3: spi@21806000 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21806000 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_SPI3>; + clocks = <&k2g_clks K2G_DEV_SPI3 K2G_DEV_SPI_VBUSP_CLK>; + clock-names = "fck"; + }; + + usb0_phy: usb-phy@0 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb0: keystone-dwc3@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_USB0>; + clocks = <&k2g_clks K2G_DEV_USB0 K2G_DEV_USB_BUS_CLK>; + clock-names = "usb"; + + usb0: usb@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb0_phy>; + status = "disabled"; + }; + }; + + usb1_phy: usb-phy@1 { + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; + + keystone_usb1: keystone-dwc3@2580000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2580000 0x10000>; + interrupts = ; + ranges; + dma-coherent; + dma-ranges; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_USB1>; + clocks = <&k2g_clks K2G_DEV_USB1 K2G_DEV_USB_BUS_CLK>; + clock-names = "usb"; + + usb1: usb@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2590000 0x10000>; + interrupts = ; + maximum-speed = "high-speed"; + dr_mode = "otg"; + usb-phy = <&usb1_phy>; + status = "disabled"; + }; + + }; + + wdt: wdt@02260000 { + compatible = "ti,keystone-wdt","ti,davinci-wdt"; + reg = <0x02260000 0x80>; + status = "disabled"; + }; + + dcan0: can@0260B200 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0260B200 0x200>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_DCAN0>; + clocks = <&k2g_clks K2G_DEV_DCAN0 K2G_DEV_DCAN_CAN_CLK>; + clock-names = "fck"; + }; + + dcan1: can@0260B400 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + reg = <0x0260B400 0x200>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_DCAN1>; + clocks = <&k2g_clks K2G_DEV_DCAN1 K2G_DEV_DCAN_CAN_CLK>; + clock-names = "fck"; + }; + + gpmc: gpmc@21818000 { + compatible = "ti,am3352-gpmc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x21818000 0x400>; + interrupts = ; + gpmc,num-cs = <4>; + gpmc,num-waitpins = <2>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_GPMC0>; + clocks = <&k2g_clks K2G_DEV_GPMC0 K2G_DEV_GPMC_GPMC_FCLK>; + clock-names = "fck"; + }; + + elm: elm@021c8000 { + compatible = "ti,am3352-elm"; + reg = <0x021c8000 0x2000>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_ELM0>; + clocks = <&k2g_clks K2G_DEV_ELM0 K2G_DEV_ELM_CLK>; + clock-names = "fck"; + }; + + msgmgr: msgmgr@02a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", + "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", + "rx_057"; + interrupts = , + ; + }; + + pmmc: pmmc { + compatible = "ti,k2g-sci"; + mbox-names = "rx", "tx"; + mboxes= <&msgmgr 5 2>, + <&msgmgr 0 0>; + reg-names = "debug_messages"; + reg = <0x02921c00 0x400>; + }; + + k2g_clks: k2g_clks { + compatible = "ti,sci-clk"; + ti,sci = <&pmmc>; + #clock-cells = <2>; + }; + + k2g_pds: k2g_pds { + compatible = "ti,sci-pm-domains"; + #power-domain-cells = <1>; + ti,sci = <&pmmc>; + }; + + k2g_reset: k2g_reset { + compatible = "ti,sci-reset"; + ti,sci = <&pmmc>; + #reset-cells = <2>; + }; + + gpio0: gpio@2603000 { + compatible = "ti,k2g-gpio"; + reg = <0x02603000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k2g_pds K2G_DEV_GPIO0>; + clocks = <&k2g_clks K2G_DEV_GPIO0 + K2G_DEV_GPIO_VBUS_CLK>; + clock-names = "fck"; + }; + + gpio1: gpio@260a000 { + compatible = "ti,k2g-gpio"; + reg = <0x0260a000 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <68>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k2g_pds K2G_DEV_GPIO1>; + clocks = <&k2g_clks K2G_DEV_GPIO1 + K2G_DEV_GPIO_VBUS_CLK>; + clock-names = "fck"; + }; + + kirq0: keystone_irq@026202a0 { + compatible = "ti,keystone-irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + #include "keystone-k2g-netcp.dtsi" + + dsp0: dsp0 { + compatible = "ti,k2g-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + power-domains = <&k2g_pds K2G_DEV_CGEM0>; + clocks = <&k2g_clks K2G_DEV_CGEM0 0>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&k2g_reset K2G_DEV_CGEM0 K2G_DEV_CGEM0_DSP0_RESET>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + mdio: mdio@4200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k2g_pds K2G_DEV_NSS0>; + clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; + clock-names = "fck"; + reg = <0x04200f00 0x100>; + status = "disabled"; + bus_freq = <2500000>; + }; + + edma0: edma@02700000 { + compatible = "ti,edma3-tpcc"; + reg = <0x02700000 0x8000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + + ti,edma-memcpy-channels = <32 33 34 35>; + + power-domains = <&k2g_pds K2G_DEV_EDMA0>; + clocks = <&k2g_clks K2G_DEV_EDMA0 K2G_DEV_EDMA_TPCC_CLK>; + clock-names = "fck"; + }; + + edma0_tptc0: tptc@02760000 { + compatible = "ti,edma3-tptc"; + reg = <0x02760000 0x400>; + power-domains = <&k2g_pds K2G_DEV_EDMA0>; + clocks = <&k2g_clks K2G_DEV_EDMA0 K2G_DEV_EDMA_TPTC_CLK>; + clock-names = "fck"; + }; + + edma0_tptc1: tptc@02768000 { + compatible = "ti,edma3-tptc"; + reg = <0x02768000 0x400>; + power-domains = <&k2g_pds K2G_DEV_EDMA0>; + clocks = <&k2g_clks K2G_DEV_EDMA0 K2G_DEV_EDMA_TPTC_CLK>; + clock-names = "fck"; + }; + + edma1: edma@02728000 { + compatible = "ti,edma3-tpcc"; + reg = <0x02728000 0x8000>; + reg-names = "edma3_cc"; + interrupts = , + , + ; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <12 13 14 15>; + * for example. + */ + + power-domains = <&k2g_pds K2G_DEV_EDMA1>; + clocks = <&k2g_clks K2G_DEV_EDMA1 K2G_DEV_EDMA_TPCC_CLK>; + clock-names = "fck"; + }; + + edma1_tptc0: tptc@027b0000 { + compatible = "ti,edma3-tptc"; + reg = <0x027b0000 0x400>; + power-domains = <&k2g_pds K2G_DEV_EDMA1>; + clocks = <&k2g_clks K2G_DEV_EDMA1 K2G_DEV_EDMA_TPTC_CLK>; + clock-names = "fck"; + }; + + edma1_tptc1: tptc@027b8000 { + compatible = "ti,edma3-tptc"; + reg = <0x027b8000 0x400>; + power-domains = <&k2g_pds K2G_DEV_EDMA1>; + clocks = <&k2g_clks K2G_DEV_EDMA1 K2G_DEV_EDMA_TPTC_CLK>; + clock-names = "fck"; + }; + + mcasp0: mcasp@02340000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02340000 0x2000>, + <0x21804000 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma0 24 1>, <&edma0 25 1>; + dma-names = "tx", "rx"; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_MCASP0>; + clocks = <&k2g_clks K2G_DEV_MCASP0 K2G_DEV_MCASP_VBUS_CLK>; + clock-names = "fck"; + }; + + mcasp1: mcasp@02342000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02342000 0x2000>, + <0x21804400 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma1 48 1>, <&edma1 49 1>; + dma-names = "tx", "rx"; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_MCASP1>; + clocks = <&k2g_clks K2G_DEV_MCASP1 K2G_DEV_MCASP_VBUS_CLK>; + clock-names = "fck"; + }; + + mcasp2: mcasp@02344000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x02344000 0x2000>, + <0x21804800 0x1000>; + reg-names = "mpu","dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + dmas = <&edma1 50 1>, <&edma1 51 1>; + dma-names = "tx", "rx"; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_MCASP2>; + clocks = <&k2g_clks K2G_DEV_MCASP2 K2G_DEV_MCASP_VBUS_CLK>; + clock-names = "fck"; + }; + + mmc0: mmc@23000000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x23000000 0x400>; + interrupts = ; + dmas = <&edma1 24 0>, <&edma1 25 0>; + dma-names = "tx", "rx"; + bus-width = <4>; + ti,needs-special-reset; + max-frequency = <96000000>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_MMCHS0>; + clocks = <&k2g_clks K2G_DEV_MMCHS0 K2G_DEV_MMCHS_CLK_ADPI>, + <&k2g_clks K2G_DEV_MMCHS0 K2G_DEV_MMCHS_CLK32K>; + clock-names = "fck", "mmchsdb_fck"; + }; + + mmc1: mmc@23100000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x23100000 0x400>; + interrupts = ; + dmas = <&edma1 26 0>, <&edma1 27 0>; + dma-names = "tx", "rx"; + bus-width = <8>; + ti,needs-special-reset; + ti,non-removable; + max-frequency = <96000000>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_MMCHS1>; + clocks = <&k2g_clks K2G_DEV_MMCHS1 K2G_DEV_MMCHS_CLK_ADPI>, + <&k2g_clks K2G_DEV_MMCHS1 K2G_DEV_MMCHS_CLK32K>; + clock-names = "fck"; + }; + + dss: dss@02540000 { + compatible = "ti,k2g-dss","simple-bus"; + reg = <0x02540000 0x400>; + clocks = <&k2g_clks K2G_DEV_DSS0 K2G_DEV_DSS_PI_DSS_OCP_CLK>; + clock-names = "fck"; + power-domains = <&k2g_pds K2G_DEV_DSS0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@02550000 { + compatible = "ti,k2g-dispc"; + reg = <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "common", "vid1", "ovr1", "vp1"; + + interrupts = ; + + clocks = <&k2g_clks K2G_DEV_DSS0 K2G_DEV_DSS_PI_DSS_OCP_CLK>, + <&k2g_clks K2G_DEV_DSS0 K2G_DEV_DSS_PI_DSS_VP_CLK>; + clock-names = "fck", "vp"; + }; + }; + + qspi: qspi@2940000 { + compatible = "ti,k2g-qspi", "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02940000 0x1000>, + <0x24000000 0x4000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x24000000>; + power-domains = <&k2g_pds K2G_DEV_QSPI0>; + clocks = <&k2g_clks K2G_DEV_QSPI0 + K2G_DEV_QSPI_QSPI_CLK>, + <&k2g_clks K2G_DEV_QSPI0 + K2G_DEV_QSPI_DATA_BUS_CLK>, + <&k2g_clks K2G_DEV_QSPI0 + K2G_DEV_QSPI_CFG_BUS_CLK>, + <&k2g_clks K2G_DEV_QSPI0 + K2G_DEV_QSPI_QSPI_CLK_O>, + <&k2g_clks K2G_DEV_QSPI0 + K2G_DEV_QSPI_QSPI_CLK_I>; + clock-names = "fck", "datack", "cfgck", "ock", "ick"; + status = "disabled"; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts --- a/arch/arm/boot/dts/keystone-k2g-evm.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,594 @@ +/* + * Device Tree Source for K2G EVM + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; + +#include +#include +#include "keystone-k2g.dtsi" + +/ { + compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone"; + model = "Texas Instruments K2G General Purpose EVM"; + + memory { + device_type = "memory"; + reg = <0x00000008 0x00000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_cma_pool: dsp_common_cma_pool { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + }; + + dsp_common_mpm_area: dsp_reserved_mpm_area { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x20000000 0x00000000 0x20000000>; + no-map; + status = "okay"; + }; + }; + + aliases { + display0 = &hdmi; + sound0 = &sound0; + }; + + vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin { + compatible = "regulator-fixed"; + regulator-name = "mmc0_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* This is actually coming from TPS659118:LDO2_1V8 */ + vcc1v8_aud_reg: fixedregulator-vcc1v8-aud { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_aud_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + soc { + mpm_mem: dspmem { + compatible = "ti,keystone-dsp-mem"; + reg = <0x0c000000 0x00100000>, + <0xa0000000 0x20000000>; + }; + }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "K2G-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + bitclock-master = <&sound0_master>; + frame-master = <&sound0_master>; + sound0_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks K2G_DEV_MCASP2 K2G_DEV_MCASP_AUX_CLK>; + system-clock-id = ; + }; + + codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <12288000>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sound1_master>; + frame-master = <&sound1_master>; + sound1_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks K2G_DEV_MCASP2 K2G_DEV_MCASP_AUX_CLK>; + system-clock-id = ; + }; + + codec { + sound-dai = <&sii9022>; + system-clock-frequency = <12288000>; + }; + }; + }; +}; + +&k2g_clks { + /* on the board 22.5792MHz is connected to AUDOSC_IN */ + assigned-clocks = <&k2g_clks K2G_DEV_BOARD0 K2G_DEV_BOARD_AUDIO_OSCIN>; + assigned-clock-rates = <22579200>; +}; + +&k2g_pinctrl { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */ + K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */ + >; + }; + + mmc0_pins: pinmux_mmc0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */ + K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */ + K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */ + K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */ + K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */ + K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */ + K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_sdcd.mmc0_sdcd */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */ + K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */ + K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */ + K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */ + K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */ + K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */ + K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */ + K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */ + K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */ + K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */ + K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */ + K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */ + K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */ + >; + }; + + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */ + K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */ + >; + }; + + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */ + K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */ + >; + }; + + nand_pins: pinmux_nand_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1000) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + K2G_CORE_IOPAD(0x1004) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + K2G_CORE_IOPAD(0x1008) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + K2G_CORE_IOPAD(0x100c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + K2G_CORE_IOPAD(0x1010) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + K2G_CORE_IOPAD(0x1014) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + K2G_CORE_IOPAD(0x1018) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + K2G_CORE_IOPAD(0x101c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + K2G_CORE_IOPAD(0x1020) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */ + K2G_CORE_IOPAD(0x1024) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */ + K2G_CORE_IOPAD(0x1028) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */ + K2G_CORE_IOPAD(0x102c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */ + K2G_CORE_IOPAD(0x1030) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */ + K2G_CORE_IOPAD(0x1034) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */ + K2G_CORE_IOPAD(0x1038) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */ + K2G_CORE_IOPAD(0x103c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */ + K2G_CORE_IOPAD(0x1044) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_advnale.gpmc_advnale */ + K2G_CORE_IOPAD(0x1048) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_oenren.gpmc_oenren */ + K2G_CORE_IOPAD(0x104c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + K2G_CORE_IOPAD(0x1050) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_beoncle.gpmc_beoncle */ + K2G_CORE_IOPAD(0x1058) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + K2G_CORE_IOPAD(0x1060) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* gpmc_wpn.gpmc_wpn */ + K2G_CORE_IOPAD(0x1068) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + >; + }; + + vout_pins: pinmux_vout_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ + K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ + K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ + K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ + K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ + K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ + K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ + K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ + K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ + K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ + K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ + K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ + K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ + K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ + K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ + K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ + K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ + K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ + K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ + K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ + K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ + K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ + K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ + K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ + K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ + >; + }; + + mcasp2_pins: pinmux_mcasp2_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ + K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ + K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ + K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&gbe0 { + phy-handle = <ðphy0>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + ranges = <0 0 0x30000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, I/O window 4 bytes */ + interrupts = ; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <25>; + gpmc,adv-wr-off-ns = <25>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <20>; + gpmc,oe-on-ns = <3>; + gpmc,oe-off-ns = <30>; + gpmc,access-ns = <30>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-pin = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block + */ + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + /* MT29F2G16ABAFAWP - 256MB */ + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0xfe80000>; + }; + }; +}; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + i2s-fifo-routing = < + (ENABLE_BIT|CONNECT_SD0) + 0 + 0 + 0 + >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vcc3v3_dcin_reg>; + IOVDD-supply = <&vcc3v3_dcin_reg>; + DRVDD-supply = <&vcc3v3_dcin_reg>; + DVDD-supply = <&vcc1v8_aud_reg>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <5000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&keystone_usb0 { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@0 { + reg = <0>; + phy-mode = "rgmii-id"; + }; +}; + +&qspi { + status = "okay"; + + flash0: m25p80@0 { + compatible = "s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + cdns,read-delay = <5>; + cdns,tshsl-ns = <500>; + cdns,tsd2d-ns = <500>; + cdns,tchsh-ns = <119>; + cdns,tslch-ns = <119>; + + partition@0 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001C0000 0x0800000>; + }; + partition@5 { + label = "QSPI.file-system"; + reg = <0x009C0000 0x3640000>; + }; + }; +}; + +&dsp0 { + memory-region = <&dsp_common_cma_pool>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc3v3_dcin_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */ + status = "okay"; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&vout_pins>; + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; + +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins>; + + assigned-clocks = <&k2g_clks K2G_DEV_MCASP2 K2G_DEV_MCASP_AUX_CLK>; + assigned-clock-parents = <&k2g_clks K2G_DEV_MCASP2 K2G_DEV_MCASP_AUX_CLK_PARENT_AUDIO_OSC>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 6 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 0 0 // AXR2: TX, AXR3: rx + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi --- a/arch/arm/boot/dts/keystone-k2g-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2g-netcp.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,157 @@ +/* + * Device Tree Source for Keystone 2 Galileo Netcp driver + * + * Copyright 2015-2016 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@4020000 { + compatible = "ti,keystone-navigator-qmss-l"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds K2G_DEV_NSS0>; + clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; + clock-names = "nss_vclk"; + ranges; + queue-range = <0 0x80>; + linkram0 = <0x4020000 0x7ff>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x80>; + reg = <0x4100000 0x800>, + <0x4040000 0x100>, + <0x4080000 0x800>, + <0x40c0000 0x800>; + reg-names = "peek", "config", + "region", "push"; + }; + + }; + queue-pools { + qpend { + qpend-0 { + qrange = <77 8>; + interrupts = + , + , + , + , + , + , + , + ; + qalloc-by-id; + }; + }; + general-purpose { + gp-0 { + qrange = <112 8>; + }; + netcp-tx { + qrange = <5 8>; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <1023 128>; /* num_desc desc_size */ + link-index = <0x400>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds K2G_DEV_NSS0>; + clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; + clock-names = "nss_vclk"; + ranges; + ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x4010000 0x100>, + <0x4011000 0x2a0>, /* 21 Tx channels */ + <0x4012000 0x400>, /* 32 Rx channels */ + <0x4010100 0x80>, + <0x4013000 0x400>; /* 32 Rx flows */ + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; + +}; + +gbe_subsys: subsys@4200000 { + compatible = "syscon"; + reg = <0x4200000 0x100>; +}; + +netcp: netcp@4000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k2g_pds K2G_DEV_NSS0>; + clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; + clock-names = "ethss_clk"; + + /* NetCP address range */ + ranges = <0 0x4000000 0x1000000>; + + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; + ti,navigator-dma-names = "netrx0", "nettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-2"; + syscon-subsys = <&gbe_subsys>; + reg = <0x200100 0xe00>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <5>; + tx-channel = "nettx"; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <5>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <512 12>; + tx-pool = <511 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <77>; + tx-completion-queue = <78>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi --- a/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,425 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkarm>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkpass>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3a>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + ddr3bpllclk: ddr3bpllclk@2620368 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclkddr3b>; + clock-output-names = "ddr-3b-pll-clk"; + reg = <0x02620368 4>; + reg-names = "control"; + }; + + clktsip: clktsip { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk16>; + clock-output-names = "tsip"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clksrio: clksrio { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1rstiso13>; + clock-output-names = "srio"; + reg = <0x0235002c 0xb00>, <0x02350010 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkhyperlink0: clkhyperlink0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-0"; + reg = <0x02350030 0xb00>, <0x02350014 0x400>; + reg-names = "control", "domain"; + domain-id = <5>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clkgem4: clkgem4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem4"; + reg = <0x0235004c 0xb00>, <0x02350030 0x400>; + reg-names = "control", "domain"; + domain-id = <12>; + }; + + clkgem5: clkgem5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem5"; + reg = <0x02350050 0xb00>, <0x02350034 0x400>; + reg-names = "control", "domain"; + domain-id = <13>; + }; + + clkgem6: clkgem6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem6"; + reg = <0x02350054 0xb00>, <0x02350038 0x400>; + reg-names = "control", "domain"; + domain-id = <14>; + }; + + clkgem7: clkgem7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem7"; + reg = <0x02350058 0xb00>, <0x0235003c 0x400>; + reg-names = "control", "domain"; + domain-id = <15>; + }; + + clkddr31: clkddr31 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "ddr3-1"; + reg = <0x02350060 0xb00>, <0x02350040 0x400>; + reg-names = "control", "domain"; + domain-id = <16>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac01: clkrac01 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-01"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac23: clkrac23 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac-23"; + reg = <0x0235006c 0xb00>, <0x02350048 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x02350074 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkfftc2: clkfftc2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-2"; + reg = <0x02350078 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc3: clkfftc3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-3"; + reg = <0x0235007c 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc4: clkfftc4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-4"; + reg = <0x02350080 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkfftc5: clkfftc5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-5"; + reg = <0x02350084 0xb00>, <0x02350050 0x400>; + reg-names = "control", "domain"; + domain-id = <20>; + }; + + clkaif: clkaif { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "aif"; + reg = <0x02350088 0xb00>, <0x02350054 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350090 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d2: clktcp3d2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-2"; + reg = <0x02350094 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clktcp3d3: clktcp3d3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-3"; + reg = <0x02350098 0xb00>, <0x0235005c 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp4: clkvcp4 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-4"; + reg = <0x023500ac 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp5: clkvcp5 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-5"; + reg = <0x023500b0 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp6: clkvcp6 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-6"; + reg = <0x023500b4 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkvcp7: clkvcp7 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-7"; + reg = <0x023500b8 0xb00>, <0x02350064 0x400>; + reg-names = "control", "domain"; + domain-id = <25>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdxb: clkdxb { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dxb"; + reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkhyperlink1: clkhyperlink1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "hyperlink-1"; + reg = <0x023500c4 0xb00>, <0x02350070 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkxge: clkxge { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "xge"; + reg = <0x023500c8 0xb00>, <0x02350074 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi --- a/arch/arm/boot/dts/keystone-k2hk.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,300 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking soc specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + compatible = "ti,k2hk", "ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + aliases { + rproc0 = &dsp0; + rproc1 = &dsp1; + rproc2 = &dsp2; + rproc3 = &dsp3; + rproc4 = &dsp4; + rproc5 = &dsp5; + rproc6 = &dsp6; + rproc7 = &dsp7; + }; + + soc { + /include/ "keystone-k2hk-clocks.dtsi" + + psc: power-sleep-controller@02350000 { + pscrst: psc-reset { + dsp@0 { + reg = <0>; + reset-control = <0xa3c 8 RESET_ASSERT_CLEAR>; + reset-status = <0x83c 8 RESET_ASSERT_CLEAR>; + }; + + dsp@1 { + reg = <1>; + reset-control = <0xa40 8 RESET_ASSERT_CLEAR>; + reset-status = <0x840 8 RESET_ASSERT_CLEAR>; + }; + + dsp@2 { + reg = <2>; + reset-control = <0xa44 8 RESET_ASSERT_CLEAR>; + reset-status = <0x844 8 RESET_ASSERT_CLEAR>; + }; + + dsp@3 { + reg = <3>; + reset-control = <0xa48 8 RESET_ASSERT_CLEAR>; + reset-status = <0x848 8 RESET_ASSERT_CLEAR>; + }; + + dsp@4 { + reg = <4>; + reset-control = <0xa4c 8 RESET_ASSERT_CLEAR>; + reset-status = <0x84c 8 RESET_ASSERT_CLEAR>; + }; + + dsp@5 { + reg = <5>; + reset-control = <0xa50 8 RESET_ASSERT_CLEAR>; + reset-status = <0x850 8 RESET_ASSERT_CLEAR>; + }; + + dsp@6 { + reg = <6>; + reset-control = <0xa54 8 RESET_ASSERT_CLEAR>; + reset-status = <0x854 8 RESET_ASSERT_CLEAR>; + }; + + dsp@7 { + reg = <7>; + reset-control = <0xa58 8 RESET_ASSERT_CLEAR>; + reset-status = <0x858 8 RESET_ASSERT_CLEAR>; + }; + }; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dspgpio4: keystone_dsp_gpio@2620250 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; + + dspgpio5: keystone_dsp_gpio@2620254 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; + + dspgpio6: keystone_dsp_gpio@2620258 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; + + dspgpio7: keystone_dsp_gpio@262025c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; + + dsp0: dsp0 { + compatible = "ti,k2hk-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x40>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + dsp1: dsp1 { + compatible = "ti,k2hk-dsp"; + reg = <0x11800000 0x00100000>, + <0x11e00000 0x00008000>, + <0x11f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem1>; + ti,syscon-dev = <&devctrl 0x44>; + resets = <&pscrst 1>; + interrupt-parent = <&kirq0>; + interrupts = <1 9>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio1 27 0>; + }; + + dsp2: dsp2 { + compatible = "ti,k2hk-dsp"; + reg = <0x12800000 0x00100000>, + <0x12e00000 0x00008000>, + <0x12f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem2>; + ti,syscon-dev = <&devctrl 0x48>; + resets = <&pscrst 2>; + interrupt-parent = <&kirq0>; + interrupts = <2 10>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio2 27 0>; + }; + + dsp3: dsp3 { + compatible = "ti,k2hk-dsp"; + reg = <0x13800000 0x00100000>, + <0x13e00000 0x00008000>, + <0x13f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem3>; + ti,syscon-dev = <&devctrl 0x4c>; + resets = <&pscrst 3>; + interrupt-parent = <&kirq0>; + interrupts = <3 11>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio3 27 0>; + }; + + dsp4: dsp4 { + compatible = "ti,k2hk-dsp"; + reg = <0x14800000 0x00100000>, + <0x14e00000 0x00008000>, + <0x14f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem4>; + ti,syscon-dev = <&devctrl 0x50>; + resets = <&pscrst 4>; + interrupt-parent = <&kirq0>; + interrupts = <4 12>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio4 27 0>; + }; + + dsp5: dsp5 { + compatible = "ti,k2hk-dsp"; + reg = <0x15800000 0x00100000>, + <0x15e00000 0x00008000>, + <0x15f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem5>; + ti,syscon-dev = <&devctrl 0x54>; + resets = <&pscrst 5>; + interrupt-parent = <&kirq0>; + interrupts = <5 13>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio5 27 0>; + }; + + dsp6: dsp6 { + compatible = "ti,k2hk-dsp"; + reg = <0x16800000 0x00100000>, + <0x16e00000 0x00008000>, + <0x16f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem6>; + ti,syscon-dev = <&devctrl 0x58>; + resets = <&pscrst 6>; + interrupt-parent = <&kirq0>; + interrupts = <6 14>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio6 27 0>; + }; + + dsp7: dsp7 { + compatible = "ti,k2hk-dsp"; + reg = <0x17800000 0x00100000>, + <0x17e00000 0x00008000>, + <0x17f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem7>; + ti,syscon-dev = <&devctrl 0x5c>; + resets = <&pscrst 7>; + interrupt-parent = <&kirq0>; + interrupts = <7 15>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio7 27 0>; + }; + + mdio: mdio@02090300 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02090300 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2hk-netcp.dtsi" + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,247 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 Kepler/Hawking EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2hk.dtsi" + +/ { + compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; + model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_cma_pool: dsp_common_cma_pool { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + }; + + dsp_common_mpm_area: dsp_reserved_mpm_area { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x20000000 0x00000000 0x20000000>; + no-map; + status = "okay"; + }; + }; + + soc { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + + refclkpass: refclkpass { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-pass"; + }; + + refclkarm: refclkarm { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "refclk-arm"; + }; + + refclkddr3a: refclkddr3a { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3a"; + }; + + refclkddr3b: refclkddr3b { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "refclk-ddr3b"; + }; + }; + + ddr3edac: edac@21010000 { + status = "ok"; + }; + + mpm_mem: dspmem { + compatible = "ti,keystone-dsp-mem"; + reg = <0x0c000000 0x00600000>, + <0xa0000000 0x20000000>; + }; + }; + + leds { + compatible = "gpio-leds"; + debug1_1 { + label = "keystone:green:debug1"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ + }; + + debug1_2 { + label = "keystone:red:debug1"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ + }; + + debug2 { + label = "keystone:blue:debug2"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ + }; + + debug3 { + label = "keystone:blue:debug3"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x1fe80000>; + }; + }; + }; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&gbe_serdes { + status = "okay"; +}; + +&dsp0 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp1 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp2 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp3 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp4 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp5 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp6 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp7 { + memory-region = <&dsp_common_cma_pool>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi --- a/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,489 @@ +/* + * Device Tree Source for Keystone 2 Hawking Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x4000>; + linkram0 = <0x100000 0x8000>; + linkram1 = <0x0 0x10000>; + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + + qmgr1 { + managed-queues = <0x2000 0x2000>; + reg = <0x2a60000 0x20000>, + <0x2a06400 0x400>, + <0x2a04000 0x1000>, + <0x2a05000 0x1000>, + <0x23aa0000 0x20000>, + <0x2aa0000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <8704 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0x104 0 53 0x204 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <8720 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <640 9>; + qalloc-by-id; + }; + netcpx-tx { + qrange = <8752 8>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + qalloc-by-id; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <10240 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@0x2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000 + 0x23aa0000 0x23ab0000>; + + dma_gbe: dma_gbe@0 { + reg = <0x2004000 0x100>, + <0x2004400 0x120>, + <0x2004800 0x300>, + <0x2004c00 0x120>, + <0x2005000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + ti,enable-all; + }; + + dma_xgbe: dma_xgbe@0 { + reg = <0x2fa1000 0x100>, + <0x2fa1400 0x200>, + <0x2fa1800 0x200>, + <0x2fa1c00 0x200>, + <0x2fa2000 0x400>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + }; +}; + +gbe_subsys: subsys@2090000 { + compatible = "syscon"; + reg = <0x02090000 0x100>; +}; + +gbe_serdes: phy@232a000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x0232a000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcp: netcp@2000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x2000000 0x100000>; + + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>; + clock-names = "pa_clk", "ethss_clk", "cpts_rft_clk" ; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 22>, /* rx flow for CPSW port 0 */ + <&dma_gbe 23>, /* rx flow for CPSW port 1 */ + <&dma_gbe 8>, /* CPSW tx channel */ + <&dma_gbe 24>, /* rx flow for CPSW port 2 */ + <&dma_gbe 25>, /* rx flow for CPSW port 3 */ + <&dma_gbe 0>, /* PA cluster 0 channel */ + <&dma_gbe 1>, /* PA cluster 1 channel */ + <&dma_gbe 2>, /* PA cluster 2 channel */ + <&dma_gbe 3>, /* PA cluster 3 channel */ + <&dma_gbe 4>, /* PA cluster 4 channel */ + <&dma_gbe 5>, /* PA cluster 5 channel */ + <&dma_gbe 31>; /* PA rx flow for cmd rsp */ + ti,navigator-dma-names = "netrx0", + "netrx1", + "nettx", + "netrx2", + "netrx3", + "pa-cl0", + "pa-cl1", + "pa-cl2", + "pa-cl3", + "pa-cl4", + "pa-cl5", + "pa-cmd-rsp"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@90000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe"; + syscon-subsys = <&gbe_subsys>; + reg = <0x90100 0x200>, <0x90400 0x200>, <0x90800 0x700>; + /* enable-ale; */ + tx-queue = <648>; + tx-channel = "nettx"; + phys = <&gbe_serdes>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + + pa@0 { + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-pa"; + compatible = "ti,netcp-pa"; + + reg = <0 0x60>, /* Mailbox */ + <0x400 0x10>, /* Packet ID */ + <0x500 0x40>, /* LUT2 */ + <0x604 0x4>, /* streaming switch */ + <0x1000 0x600>, /* Control */ + <0x3000 0x600>, /* Timers */ + <0x6000 0x100>, /* Statistics */ + <0x10000 0x30000>, /* Iram */ + <0x40000 0x8000>; /* Sram */ + + mac-lut-ranges = <0 43 56 63>; + /* Static reservation in LUT-1 (outer IP) + * used by driver to add IP rules for Rx checksum + * offload. + */ + ip-lut-ranges = <61 63>; + /* base queue, base flow. Should match with that + * for netrx0 + */ + rx-route = <8704 22>; + tx-cmd-pool = <256 12>; + /* rx command pool */ + rx-cmd-rsp-pool = <256 12>; + /* rx channel name for command response */ + rx-cmd-rsp-chan = "pa-cmd-rsp"; + rx-cmd-rsp-queue-depth = <128 32 0 0>; + rx-cmd-rsp-buffer-size = <128 512 0 0>; + + interfaces { + pa0: interface-0 { + slave-port = <0>; + }; + + pa1: interface-1 { + slave-port = <1>; + }; + }; + + /* PA clusters that does packet processing */ + clusters { + #address-cells = <1>; + #size-cells = <0>; + cluster@0 { + reg = <0>; + tx-queue = <640>; + tx-channel = "pa-cl0"; + }; + + cluster@1 { + reg = <1>; + tx-queue = <641>; + tx-channel = "pa-cl1"; + }; + + cluster@5 { + reg = <5>; + tx-queue = <645>; + tx-channel = "pa-cl5"; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8704>; + tx-completion-queue = <8706>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + netcp-pa = <&pa0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <8705>; + tx-completion-queue = <8707>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 6f]; + netcp-gbe = <&gbe1>; + netcp-pa = <&pa1>; + }; + }; +}; + +xgbe_subsys: subsys@2f00000 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00000 0x100>; +}; + +xgbe_pcsr: pcsr@2f00600 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00600 0x100>; +}; + +xgbe_serdes: phy@231e000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-xgbe"; + reg = <0x0231e000 0x2000>; + link-rate-kbps = <10312500>; + num-lanes = <2>; + syscon-peripheral = <&xgbe_subsys>; + syscon-link = <&xgbe_pcsr>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcpx: netcp@2f00000 { + status = "disabled"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&clkxge>; + clock-names = "xge_clk"; + dma-coherent; + /* big-endian; */ + + ti,navigator-dmas = <&dma_xgbe 0>, + <&dma_xgbe 8>, + <&dma_xgbe 0>; + ti,navigator-dma-names = "xnetrx0", "xnetrx1", "xnettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + xgbe@0x2f00000 { + label = "netcp-xgbe"; + compatible = "ti,netcp-xgbe"; + syscon-subsys = <&xgbe_subsys>; + syscon-pcsr = <&xgbe_pcsr>; + reg = <0x02f00100 0x200>, <0x02f01000 0xb00>; + /* enable-ale; */ + tx-queue = <8752>; + tx-channel = "xnettx"; + phys = <&xgbe_serdes>; + + interfaces { + xgbe0: interface-0 { + slave-port = <0>; + link-interface = <11>; /* MAC_MAC */ + }; + xgbe1: interface-1 { + slave-port = <1>; + link-interface = <11>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "xnetrx0"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 64 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <8708>; + tx-completion-queue = <8710>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe0>; + + }; + interface-1 { + rx-channel = "xnetrx1"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <8709>; + tx-completion-queue = <8711>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe1>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi --- a/arch/arm/boot/dts/keystone-k2l-clocks.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,266 @@ +/* + * Copyright 2013-2014 Texas Instruments, Inc. + * + * Keystone 2 lamarr SoC clock nodes + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +clocks { + armpllclk: armpllclk@2620370 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "arm-pll-clk"; + reg = <0x02620370 4>; + reg-names = "control"; + }; + + mainpllclk: mainpllclk@2310110 { + #clock-cells = <0>; + compatible = "ti,keystone,main-pll-clock"; + clocks = <&refclksys>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; + }; + + papllclk: papllclk@2620358 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "papllclk"; + reg = <0x02620358 4>; + reg-names = "control"; + }; + + ddr3apllclk: ddr3apllclk@2620360 { + #clock-cells = <0>; + compatible = "ti,keystone,pll-clock"; + clocks = <&refclksys>; + clock-output-names = "ddr-3a-pll-clk"; + reg = <0x02620360 4>; + reg-names = "control"; + }; + + clkdfeiqnsys: clkdfeiqnsys { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "dfe"; + reg-names = "control", "domain"; + reg = <0x02350004 0xb00>, <0x02350000 0x400>; + domain-id = <0>; + }; + + clkpcie1: clkpcie1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk12>; + clock-output-names = "pcie"; + reg = <0x0235002c 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <4>; + }; + + clkgem1: clkgem1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem1"; + reg = <0x02350040 0xb00>, <0x02350024 0x400>; + reg-names = "control", "domain"; + domain-id = <9>; + }; + + clkgem2: clkgem2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem2"; + reg = <0x02350044 0xb00>, <0x02350028 0x400>; + reg-names = "control", "domain"; + domain-id = <10>; + }; + + clkgem3: clkgem3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk1>; + clock-output-names = "gem3"; + reg = <0x02350048 0xb00>, <0x0235002c 0x400>; + reg-names = "control", "domain"; + domain-id = <11>; + }; + + clktac: clktac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tac"; + reg = <0x02350064 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkrac: clkrac { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "rac"; + reg = <0x02350068 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <17>; + }; + + clkdfepd0: clkdfepd0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd0"; + reg = <0x0235006c 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <18>; + }; + + clkfftc0: clkfftc0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-0"; + reg = <0x02350070 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <19>; + }; + + clkosr: clkosr { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "osr"; + reg = <0x02350088 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <21>; + }; + + clktcp3d0: clktcp3d0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-0"; + reg = <0x0235008c 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <22>; + }; + + clktcp3d1: clktcp3d1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "tcp3d-1"; + reg = <0x02350094 0xb00>, <0x02350058 0x400>; + reg-names = "control", "domain"; + domain-id = <23>; + }; + + clkvcp0: clkvcp0 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-0"; + reg = <0x0235009c 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp1: clkvcp1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-1"; + reg = <0x023500a0 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp2: clkvcp2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-2"; + reg = <0x023500a4 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkvcp3: clkvcp3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "vcp-3"; + reg = <0x023500a8 0xb00>, <0x02350060 0x400>; + reg-names = "control", "domain"; + domain-id = <24>; + }; + + clkbcp: clkbcp { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "bcp"; + reg = <0x023500bc 0xb00>, <0x02350068 0x400>; + reg-names = "control", "domain"; + domain-id = <26>; + }; + + clkdfepd1: clkdfepd1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "dfe-pd1"; + reg = <0x023500c0 0xb00>, <0x02350044 0x400>; + reg-names = "control", "domain"; + domain-id = <27>; + }; + + clkfftc1: clkfftc1 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "fftc-1"; + reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; + reg-names = "control", "domain"; + domain-id = <28>; + }; + + clkiqnail: clkiqnail { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&chipclk13>; + clock-output-names = "iqn-ail"; + reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; + reg-names = "control", "domain"; + domain-id = <29>; + }; + + clkuart2: clkuart2 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart2"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; + + clkuart3: clkuart3 { + #clock-cells = <0>; + compatible = "ti,keystone,psc-clock"; + clocks = <&clkmodrst0>; + clock-output-names = "uart3"; + reg = <0x02350000 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi --- a/arch/arm/boot/dts/keystone-k2l.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2l.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,355 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr SoC specific device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + compatible = "ti,k2l", "ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr SoC"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gic>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <1>; + }; + }; + + aliases { + rproc0 = &dsp0; + rproc1 = &dsp1; + rproc2 = &dsp2; + rproc3 = &dsp3; + }; + + soc { + /include/ "keystone-k2l-clocks.dtsi" + + uart2: serial@02348400 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348400 0x100>; + clocks = <&clkuart2>; + interrupts = ; + }; + + uart3: serial@02348800 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02348800 0x100>; + clocks = <&clkuart3>; + interrupts = ; + }; + + k2l_pmx: pinmux@02620690 { + compatible = "pinctrl-single"; + reg = <0x02620690 0xc>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1>; + status = "disabled"; + + uart3_emifa_pins: pinmux_uart3_emifa_pins { + pinctrl-single,bits = < + /* UART3_EMIFA_SEL */ + 0x0 0x0 0xc0 + >; + }; + + uart2_emifa_pins: pinmux_uart2_emifa_pins { + pinctrl-single,bits = < + /* UART2_EMIFA_SEL */ + 0x0 0x0 0x30 + >; + }; + + uart01_spi2_pins: pinmux_uart01_spi2_pins { + pinctrl-single,bits = < + /* UART01_SPI2_SEL */ + 0x0 0x0 0x4 + >; + }; + + dfesync_rp1_pins: pinmux_dfesync_rp1_pins{ + pinctrl-single,bits = < + /* DFESYNC_RP1_SEL */ + 0x0 0x0 0x2 + >; + }; + + avsif_pins: pinmux_avsif_pins { + pinctrl-single,bits = < + /* AVSIF_SEL */ + 0x0 0x0 0x1 + >; + }; + + gpio_emu_pins: pinmux_gpio_emu_pins { + pinctrl-single,bits = < + /* + * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33 + * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32 + * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31 + * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30 + * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29 + * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28 + * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27 + * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26 + * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25 + * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24 + * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23 + * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22 + * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21 + * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20 + * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19 + */ + 0x4 0x0000 0xFFFE0000 + >; + }; + + gpio_timio_pins: pinmux_gpio_timio_pins { + pinctrl-single,bits = < + /* + * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7 + * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6 + * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5 + * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4 + * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3 + * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2 + * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7 + * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6 + * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5 + * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4 + * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3 + * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2 + */ + 0x4 0x0 0xFFF0 + >; + }; + + gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins { + pinctrl-single,bits = < + /* + * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4 + * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3 + * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2 + * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1 + */ + 0x4 0x0 0xF + >; + }; + + gpio_dfeio_pins: pinmux_gpio_dfeio_pins { + pinctrl-single,bits = < + /* + * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63 + * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62 + * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61 + * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60 + * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59 + * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58 + * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57 + * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56 + * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55 + * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54 + * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53 + * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52 + * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51 + * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50 + * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49 + * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48 + */ + 0x8 0x0 0xFFFF0000 + >; + }; + + gpio_emifa_pins: pinmux_gpio_emifa_pins { + pinctrl-single,bits = < + /* + * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47 + * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46 + * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45 + * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44 + * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43 + * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42 + * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41 + * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40 + * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39 + * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38 + * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37 + * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36 + * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35 + * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34 + * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33 + * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32 + */ + 0x8 0x0 0xFFFF + >; + }; + }; + + psc: power-sleep-controller@02350000 { + pscrst: psc-reset { + dsp@0 { + reg = <0>; + reset-control = <0xa3c 8 RESET_ASSERT_CLEAR>; + reset-status = <0x83c 8 RESET_ASSERT_CLEAR>; + }; + + dsp@1 { + reg = <1>; + reset-control = <0xa40 8 RESET_ASSERT_CLEAR>; + reset-status = <0x840 8 RESET_ASSERT_CLEAR>; + }; + + dsp@2 { + reg = <2>; + reset-control = <0xa44 8 RESET_ASSERT_CLEAR>; + reset-status = <0x844 8 RESET_ASSERT_CLEAR>; + }; + + dsp@3 { + reg = <3>; + reset-control = <0xa48 8 RESET_ASSERT_CLEAR>; + reset-status = <0x848 8 RESET_ASSERT_CLEAR>; + }; + }; + }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dsp0: dsp0 { + compatible = "ti,k2l-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x844>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + dsp1: dsp1 { + compatible = "ti,k2l-dsp"; + reg = <0x11800000 0x00100000>, + <0x11e00000 0x00008000>, + <0x11f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem1>; + ti,syscon-dev = <&devctrl 0x848>; + resets = <&pscrst 1>; + interrupt-parent = <&kirq0>; + interrupts = <1 9>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio1 27 0>; + }; + + dsp2: dsp2 { + compatible = "ti,k2l-dsp"; + reg = <0x12800000 0x00100000>, + <0x12e00000 0x00008000>, + <0x12f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem2>; + ti,syscon-dev = <&devctrl 0x84c>; + resets = <&pscrst 2>; + interrupt-parent = <&kirq0>; + interrupts = <2 10>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio2 27 0>; + }; + + dsp3: dsp3 { + compatible = "ti,k2l-dsp"; + reg = <0x13800000 0x00100000>, + <0x13e00000 0x00008000>, + <0x13f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem3>; + ti,syscon-dev = <&devctrl 0x850>; + resets = <&pscrst 3>; + interrupt-parent = <&kirq0>; + interrupts = <3 11>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio3 27 0>; + }; + + mdio: mdio@26200f00 { + compatible = "ti,keystone_mdio", "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x26200f00 0x100>; + status = "disabled"; + clocks = <&clkcpgmac>; + clock-names = "fck"; + bus_freq = <2500000>; + }; + /include/ "keystone-k2l-netcp.dtsi" + }; +}; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts --- a/arch/arm/boot/dts/keystone-k2l-evm.dts 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,180 @@ +/* + * Copyright 2014 Texas Instruments, Inc. + * + * Keystone 2 Lamarr EVM device tree + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "keystone.dtsi" +#include "keystone-k2l.dtsi" + +/ { + compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; + model = "Texas Instruments Keystone 2 Lamarr EVM"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_common_cma_pool: dsp_common_cma_pool { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x1f800000 0x00000000 0x800000>; + reusable; + }; + + dsp_common_mpm_area: dsp_reserved_mpm_area { + compatible = "shared-dma-pool"; + reg = <0x00000008 0x20000000 0x00000000 0x20000000>; + no-map; + status = "okay"; + }; + }; + + soc { + clocks { + refclksys: refclksys { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <122880000>; + clock-output-names = "refclk-sys"; + }; + }; + + ddr3edac: edac@21010000 { + status = "ok"; + }; + + mpm_mem: dspmem { + compatible = "ti,keystone-dsp-mem"; + reg = <0x0c000000 0x00200000>, + <0xa0000000 0x20000000>; + }; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&i2c0 { + dtt@50 { + compatible = "at,24c1024"; + reg = <0x50>; + }; +}; + +&aemif { + cs0 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <0>; + /* all timings in nanoseconds */ + ti,cs-min-turnaround-ns = <12>; + ti,cs-read-hold-ns = <6>; + ti,cs-read-strobe-ns = <23>; + ti,cs-read-setup-ns = <9>; + ti,cs-write-hold-ns = <8>; + ti,cs-write-strobe-ns = <23>; + ti,cs-write-setup-ns = <8>; + + nand@0,0 { + compatible = "ti,keystone-nand","ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x4000000 + 1 0 0x0000100>; + + ti,davinci-chipselect = <0>; + ti,davinci-mask-ale = <0x2000>; + ti,davinci-mask-cle = <0x4000>; + ti,davinci-mask-chipsel = <0>; + nand-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + nand-on-flash-bbt; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "params"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "ubifs"; + reg = <0x180000 0x7FE80000>; + }; + }; + }; +}; + +&spi0 { + nor_flash: n25q128a11@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "Micron,n25q128a11"; + spi-max-frequency = <54000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&mdio { + status = "ok"; + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&gbe_serdes0 { + status = "okay"; +}; + +&dsp0 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp1 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp2 { + memory-region = <&dsp_common_cma_pool>; +}; + +&dsp3 { + memory-region = <&dsp_common_cma_pool>; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi --- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,393 @@ +/* + * Device Tree Source for Keystone 2 Lamarr Netcp driver + * + * Copyright 2015 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +qmss: qmss@2a40000 { + compatible = "ti,keystone-navigator-qmss"; + dma-coherent; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&chipclk13>; + ranges; + queue-range = <0 0x2000>; + linkram0 = <0x100000 0x4000>; + linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ + + qmgrs { + #address-cells = <1>; + #size-cells = <1>; + ranges; + qmgr0 { + managed-queues = <0 0x2000>; + reg = <0x2a40000 0x20000>, + <0x2a06000 0x400>, + <0x2a02000 0x1000>, + <0x2a03000 0x1000>, + <0x23a80000 0x20000>, + <0x2a80000 0x20000>; + reg-names = "peek", "status", "config", + "region", "push", "pop"; + }; + }; + queue-pools { + qpend { + qpend-0 { + qrange = <658 8>; + interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 + 0 43 0xf04 0 44 0xf04 0 45 0xf04 + 0 46 0xf04 0 47 0xf04>; + }; + qpend-1 { + qrange = <528 16>; + interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 + 0 51 0xf04 0 52 0xf04 0 53 0xf04 + 0 54 0xf04 0 55 0xf04 0 56 0xf04 + 0 57 0xf04 0 58 0xf04 0 59 0xf04 + 0 60 0xf04 0 61 0xf04 0 62 0xf04 + 0 63 0xf04>; + qalloc-by-id; + }; + qpend-2 { + qrange = <544 16>; + interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 + 0 59 0xf04 0 68 0xf04 0 69 0xf04 + 0 70 0xf04 0 71 0xf04 0 72 0xf04 + 0 73 0xf04 0 74 0xf04 0 75 0xf04 + 0 76 0xf04 0 77 0xf04 0 78 0xf04 + 0 79 0xf04>; + }; + }; + general-purpose { + gp-0 { + qrange = <4000 64>; + }; + netcp-tx { + qrange = <896 128>; + qalloc-by-id; + }; + }; + accumulator { + acc-low-0 { + qrange = <480 32>; + accumulator = <0 47 16 2 50>; + interrupts = <0 226 0xf01>; + multi-queue; + }; + }; + }; + + descriptor-regions { + #address-cells = <1>; + #size-cells = <1>; + ranges; + region-12 { + id = <12>; + region-spec = <8192 128>; /* num_desc desc_size */ + link-index = <0x4000>; + }; + }; + + pdsps { + #address-cells = <1>; + #size-cells = <1>; + ranges; + pdsp0@0x2a10000 { + reg = <0x2a10000 0x1000 /*iram */ + 0x2a0f000 0x100 /*reg*/ + 0x2a0c000 0x3c8 /*intd */ + 0x2a20000 0x4000>; /*cmd*/ + id = <0>; + }; + }; + +}; /* qmss */ + +knav_dmas: knav_dmas@0 { + compatible = "ti,keystone-navigator-dma"; + clocks = <&papllclk>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,navigator-cloud-address = <0x23a80000 0x23a90000>; + + dma_gbe: dma_gbe@0 { + reg = <0x26186000 0x100>, + <0x26187000 0x2a0>, + <0x26188000 0xb60>, + <0x26186100 0x80>, + <0x26189000 0x1000>; + reg-names = "global", "txchan", "rxchan", + "txsched", "rxflow"; + ti,enable-all; + }; +}; + +gbe_subsys: subsys@26200000 { + compatible = "syscon"; + reg = <0x26200000 0x100>; +}; + +gbe_serdes0: phy@232a000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x0232a000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <2>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +gbe_serdes1: phy@2320000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x02320000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <2>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcp: netcp@26000000 { + reg = <0x2620110 0x8>; + reg-names = "efuse"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + + /* NetCP address range */ + ranges = <0 0x26000000 0x1000000>; + + clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>, <&clkosr>; + clock-names = "pa_clk", "ethss_clk", "cpts_rft_clk", "osr_clk"; + dma-coherent; + + ti,navigator-dmas = <&dma_gbe 0>, + <&dma_gbe 8>, + <&dma_gbe 0>, + <&dma_gbe 22>, + <&dma_gbe 23>, + <&dma_gbe 24>, + <&dma_gbe 25>, + <&dma_gbe 27>, + <&dma_gbe 28>, + <&dma_gbe 29>, + <&dma_gbe 30>, + <&dma_gbe 8>, + <&dma_gbe 9>, + <&dma_gbe 10>, + <&dma_gbe 11>, + <&dma_gbe 12>, + <&dma_gbe 13>, + <&dma_gbe 14>, /* for egress cluster */ + <&dma_gbe 31>; + + ti,navigator-dma-names = "netrx0", + "netrx1", + "nettx", + "netrx0-pa", + "netrx1-pa", + "netrx2-pa", + "netrx3-pa", + "netrx4-pa", + "netrx5-pa", + "netrx6-pa", + "netrx7-pa", + "pa-cl0", + "pa-cl1", + "pa-cl2", + "pa-cl3", + "pa-cl4", + "pa-cl5", + "pa-cl6", + "pa-cmd-rsp"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + gbe@200000 { /* ETHSS */ + label = "netcp-gbe"; + compatible = "ti,netcp-gbe-5"; + syscon-subsys = <&gbe_subsys>; + reg = <0x200100 0x400>, <0x220000 0x20000>; + /* enable-ale; */ + tx-queue = <896>; + tx-channel = "nettx"; + phys = <&gbe_serdes0>, <&gbe_serdes1>; + + interfaces { + gbe0: interface-0 { + slave-port = <0>; + link-interface = <1>; + phy-handle = <ðphy0>; + }; + gbe1: interface-1 { + slave-port = <1>; + link-interface = <1>; + phy-handle = <ðphy1>; + }; + }; + + secondary-slave-ports { + port-2 { + slave-port = <2>; + link-interface = <2>; + }; + port-3 { + slave-port = <3>; + link-interface = <2>; + }; + }; + }; + + pa@0 { + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-pa2"; + compatible = "ti,netcp-pa2"; + + reg = <0 0x100>, /* Mailbox */ + <0x400 0x40>, /* RA bridge */ + <0x500 0x80>, /* thread mapper */ + <0x800 0x1000>, /* RA */ + <0x6000 0x100>, /* Statistics regs */ + <0x8000 0x100>, /* Statistics block */ + <0x400000 0x900000>; /* cluster memory */ + + mac-lut-ranges = <0 43 56 63>; + /* Static reservation in LUT-1 (outer IP) + * used by driver to add IP rules for Rx checksum + * offload. + */ + ip-lut-ranges = <61 63>; + /* base queue, base flow. Should match with that + * for netrx0 + */ + rx-route = <528 22>; + tx-cmd-pool = <256 12>; + /* rx command pool */ + rx-cmd-rsp-pool = <256 12>; + /* rx channel name for command response */ + rx-cmd-rsp-chan = "pa-cmd-rsp"; + rx-cmd-rsp-queue-depth = <128 32 0 0>; + rx-cmd-rsp-buffer-size = <128 512 0 0>; + + /* rx channels get overridden for the interface + * when PA is enabled + */ + interfaces { + pa0: interface-0 { + slave-port = <0>; + rx-channel = "netrx0-pa"; + }; + + pa1: interface-1 { + slave-port = <1>; + rx-channel = "netrx1-pa"; + }; + }; + + /* PA clusters that does packet processing */ + clusters { + #address-cells = <1>; + #size-cells = <0>; + cluster@0 { + reg = <0>; + tx-queue = <904>; + tx-channel = "pa-cl0"; + }; + + cluster@1 { + reg = <1>; + tx-queue = <905>; + tx-channel = "pa-cl1"; + }; + + cluster@6 { + reg = <6>; + tx-queue = <910>; + tx-channel = "pa-cl6"; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "netrx0"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <528>; + tx-completion-queue = <530>; + efuse-mac = <1>; + netcp-gbe = <&gbe0>; + netcp-pa2 = <&pa0>; + + }; + interface-1 { + rx-channel = "netrx1"; + rx-pool = <1024 12>; + tx-pool = <1024 12>; + rx-queue-depth = <128 128 0 0>; + rx-buffer-size = <1518 4096 0 0>; + rx-queue = <529>; + tx-completion-queue = <531>; + efuse-mac = <0>; + local-mac-address = [02 18 31 7e 3e 7f]; + netcp-gbe = <&gbe1>; + netcp-pa2 = <&pa1>; + }; + }; +}; diff -Naur --no-dereference a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts 2016-05-11 13:31:53.193225201 -0400 @@ -73,7 +73,8 @@ }; &gpmc { - ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ + 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ ethernet@gpmc { pinctrl-names = "default"; diff -Naur --no-dereference a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -35,11 +35,15 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - linux,mtd-name = "micron,mt29f4g16abbda3w"; + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + linux,mtd-name = "micron,mt29f4g16abbda3w"; nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile --- a/arch/arm/boot/dts/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/Makefile 2016-05-11 13:31:53.189225170 -0400 @@ -1,9 +1,15 @@ ifeq ($(CONFIG_OF),y) +ifeq ($(CONFIG_OF_OVERLAY),y) +DTC_FLAGS += -@ +endif + dtb-$(CONFIG_ARCH_ALPINE) += \ alpine-db.dtb + dtb-$(CONFIG_MACH_ASM9260) += \ alphascale-asm9260-devkit.dtb + # Keep at91 dtb files sorted alphabetically for each SoC dtb-$(CONFIG_SOC_SAM_V4_V5) += \ at91rm9200ek.dtb \ @@ -148,9 +154,10 @@ integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ - k2hk-evm.dtb \ - k2l-evm.dtb \ - k2e-evm.dtb + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ + keystone-k2g-evm.dtb dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-b3.dtb \ kirkwood-blackarmor-nas220.dtb \ @@ -458,10 +465,29 @@ am335x-base0033.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ + am335x-sancloud-bbe.dtb \ + am335x-boneblack-audio.dtb \ + am335x-boneblack-bbb-exp-r.dtb \ + am335x-boneblack-bbb-exp-c.dtb \ + am335x-boneblack-bbbmini.dtb \ + am335x-boneblack-wireless.dtb \ + am335x-boneblack-wl1835mod.dtb \ + am335x-boneblack-cape-bone-argus.dtb \ + am335x-bone-cape-bone-argus.dtb \ + am335x-arduino-tre.dtb \ + am335x-bonegreen-wireless.dtb \ + am335x-olimex-som.dtb \ + am335x-abbbi.dtb \ + am335x-bonegreen-overlay.dtb \ + am335x-boneblack-overlay.dtb \ + am335x-boneblack-nhdmi-overlay.dtb \ + am335x-boneblack-hdmi-overlay.dtb \ + am335x-boneblack-emmc-overlay.dtb \ am335x-bonegreen.dtb \ am335x-sl50.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ + am335x-icev2.dtb \ am335x-nano.dtb \ am335x-pepper.dtb \ am335x-lxm.dtb \ @@ -480,7 +506,8 @@ am43x-epos-evm.dtb \ am437x-sk-evm.dtb \ am437x-idk-evm.dtb \ - am437x-gp-evm.dtb + am437x-gp-evm.dtb \ + am437x-gp-evm-hdmi.dtb dtb-$(CONFIG_SOC_OMAP5) += \ omap5-cm-t54.dtb \ omap5-igep0050.dtb \ @@ -488,8 +515,20 @@ omap5-uevm.dtb dtb-$(CONFIG_SOC_DRA7XX) += \ dra7-evm.dtb \ + dra7-evm-lcd-lg.dtb \ + dra7-evm-lcd-osd.dtb \ am57xx-beagle-x15.dtb \ - dra72-evm.dtb + am57xx-beagle-x15-revb1.dtb \ + am571x-idk.dtb \ + am571x-idk-lcd-osd.dtb \ + am572x-idk.dtb \ + am572x-idk-lcd-osd.dtb \ + am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ + dra72-evm.dtb \ + dra72-evm-lcd-lg.dtb \ + dra72-evm-lcd-osd.dtb \ + dra72-evm-revc.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ diff -Naur --no-dereference a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi --- a/arch/arm/boot/dts/omap2420.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap2420.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -130,6 +130,10 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; mcbsp1: mcbsp@48074000 { diff -Naur --no-dereference a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi --- a/arch/arm/boot/dts/omap2430.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap2430.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -154,6 +154,10 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; mcbsp1: mcbsp@48074000 { diff -Naur --no-dereference a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts --- a/arch/arm/boot/dts/omap3430-sdp.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3430-sdp.dts 2016-05-11 13:31:53.193225201 -0400 @@ -103,10 +103,14 @@ }; nand@1,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; - reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ ti,nand-ecc-opt = "sw"; nand-bus-width = <8>; gpmc,cs-on-ns = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts --- a/arch/arm/boot/dts/omap3-beagle.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-beagle.dts 2016-05-11 13:31:53.193225201 -0400 @@ -384,8 +384,11 @@ /* Chip select 0 */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* NAND I/O window, 4 bytes */ - interrupts = <20>; + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "ham1"; nand-bus-width = <16>; #address-cells = <1>; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -261,10 +261,14 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x01000000>; + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <8>; gpmc,device-width = <1>; ti,nand-ecc-opt = "sw"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -204,7 +204,11 @@ ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "sw"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi --- a/arch/arm/boot/dts/omap3.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -721,6 +721,10 @@ gpmc,num-waitpins = <4>; #address-cells = <2>; #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; usb_otg_hs: usb_otg_hs@480ab000 { diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts --- a/arch/arm/boot/dts/omap3-evm-37xx.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts 2016-05-11 13:31:53.193225201 -0400 @@ -154,12 +154,16 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */ + ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ <5 0 0x2c000000 0x01000000>; nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "hynix,h8kds0un0mer-4em"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi --- a/arch/arm/boot/dts/omap3-gta04.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-gta04.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -492,7 +492,11 @@ ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -210,8 +210,8 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x20000000>, - <5 0 0x2c000000 0x01000000>; + ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */ + <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */ ethernet@gpmc { pinctrl-names = "default"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -58,3 +58,7 @@ pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; }; + +&gpmc { + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ +}; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi --- a/arch/arm/boot/dts/omap3-igep.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-igep.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -95,8 +95,12 @@ &gpmc { nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts --- a/arch/arm/boot/dts/omap3-ldp.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-ldp.dts 2016-05-11 13:31:53.193225201 -0400 @@ -97,12 +97,16 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x01000000>, - <1 0 0x08000000 0x01000000>; + ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */ + <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */ nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ linux,mtd-name= "micron,nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -362,7 +362,11 @@ <7 0 0x15000000 0x01000000>; nand@0,0 { - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; /* no elm on omap3 */ diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi --- a/arch/arm/boot/dts/omap3-overo-base.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -226,8 +226,12 @@ ranges = <0 0 0x00000000 0x20000000>; nand@0,0 { + compatible = "ti,omap2-nand"; linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 0>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -546,7 +546,11 @@ ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; ti,nand-ecc-opt = "sw"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi --- a/arch/arm/boot/dts/omap3-tao3530.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -275,10 +275,14 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x01000000>; + ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */ nand@0,0 { + compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ nand-bus-width = <16>; gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ ti,nand-ecc-opt = "sw"; diff -Naur --no-dereference a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -357,6 +357,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <931200000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -374,6 +376,8 @@ reg = <0x01b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m4x2_ck>; + assigned-clock-rates = <465600000>; }; dpll_iva_m5x2_ck: dpll_iva_m5x2_ck { @@ -385,6 +389,8 @@ reg = <0x01bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m5x2_ck>; + assigned-clock-rates = <266100000>; }; dpll_mpu_ck: dpll_mpu_ck { diff -Naur --no-dereference a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi --- a/arch/arm/boot/dts/omap4.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap4.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -25,6 +25,8 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { @@ -94,11 +96,6 @@ sram = <&ocmcram>; }; - dsp { - compatible = "ti,omap3-c64"; - ti,hwmods = "dsp"; - }; - iva { compatible = "ti,ivahd"; ti,hwmods = "iva"; @@ -360,6 +357,10 @@ ti,no-idle-on-init; clocks = <&l3_div_ck>; clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; uart1: serial@4806a000 { @@ -820,6 +821,27 @@ ti,timer-pwm; }; + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,hwmods = "dsp"; + syscon-bootreg = <&scm_conf 0x304>; + iommus = <&mmu_dsp>; + mboxes = <&mailbox &mbox_dsp>; + ti,rproc-standby-info = <0x4a004420>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap4-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + ti,hwmods = "ipu"; + iommus = <&mmu_ipu>; + mboxes = <&mailbox &mbox_ipu>; + ti,rproc-standby-info = <0x4a008920>; + status = "disabled"; + }; + usbhstll: usbhstll@4a062000 { compatible = "ti,usbhs-tll"; reg = <0x4a062000 0x1000>; diff -Naur --no-dereference a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi --- a/arch/arm/boot/dts/omap4-panda-common.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -13,6 +13,26 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_cma_pool: dsp_cma@98000000 { + compatible = "shared-dma-pool"; + reg = <0x98000000 0x800000>; + reusable; + status = "okay"; + }; + + ipu_cma_pool: ipu_cma@98800000 { + compatible = "shared-dma-pool"; + reg = <0x98800000 0x7000000>; + reusable; + status = "okay"; + }; + }; + aliases { display0 = &dvi0; display1 = &hdmi0; @@ -531,6 +551,20 @@ vdd-supply = <&vcxio>; }; +&dsp { + status = "okay"; + memory-region = <&dsp_cma_pool>; + timers = <&timer5>; + watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_cma_pool>; + timers = <&timer3>; + watchdog-timers = <&timer9>, <&timer11>; +}; + &hdmi { status = "ok"; vdda-supply = <&vdac>; diff -Naur --no-dereference a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -315,6 +315,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { @@ -339,6 +343,8 @@ ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { diff -Naur --no-dereference a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi --- a/arch/arm/boot/dts/omap5.dtsi 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap5.dtsi 2016-05-11 13:31:53.193225201 -0400 @@ -32,6 +32,8 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; + rproc0 = &dsp; + rproc1 = &ipu; }; cpus { @@ -396,6 +398,10 @@ ti,hwmods = "gpmc"; clocks = <&l3_iclk_div>; clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; i2c1: i2c@48070000 { @@ -819,6 +825,27 @@ ti,hwmods = "wd_timer2"; }; + dsp: dsp { + compatible = "ti,omap5-dsp"; + ti,hwmods = "dsp"; + syscon-bootreg = <&scm_conf 0x304>; + iommus = <&mmu_dsp>; + mboxes = <&mailbox &mbox_dsp>; + ti,rproc-standby-info = <0x4a004420>; + status = "disabled"; + }; + + ipu: ipu@55020000 { + compatible = "ti,omap5-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + ti,hwmods = "ipu"; + iommus = <&mmu_ipu>; + mboxes = <&mailbox &mbox_ipu>; + ti,rproc-standby-info = <0x4a008920>; + status = "disabled"; + }; + dmm@4e000000 { compatible = "ti,omap5-dmm"; reg = <0x4e000000 0x800>; @@ -850,18 +877,6 @@ hw-caps-temp-alert; }; - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usb3phy: control-phy@4a002370 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002370 0x4>; - reg-names = "power"; - }; - usb3: omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; @@ -897,7 +912,7 @@ usb2_phy: usb2phy@4a084000 { compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; - ctrl-module = <&omap_control_usb2phy>; + syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -909,7 +924,7 @@ <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb3phy>; + syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&usb_otg_ss_refclk960m>; @@ -965,14 +980,6 @@ #thermal-sensor-cells = <1>; }; - omap_control_sata: control-phy@4a002374 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002374 0x4>; - reg-names = "power"; - clocks = <&sys_clkin>; - clock-names = "sysclk"; - }; - /* OCP2SCP3 */ ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp"; @@ -987,7 +994,7 @@ <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_sata>; + syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; #phy-cells = <0>; diff -Naur --no-dereference a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts --- a/arch/arm/boot/dts/omap5-uevm.dts 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/dts/omap5-uevm.dts 2016-05-11 13:31:53.193225201 -0400 @@ -17,6 +17,26 @@ device_type = "memory"; reg = <0x80000000 0x7F000000>; /* 2032 MB */ }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dsp_cma_pool: dsp_cma@95000000 { + compatible = "shared-dma-pool"; + reg = <0x95000000 0x800000>; + reusable; + status = "okay"; + }; + + ipu_cma_pool: ipu_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x95800000 0x3800000>; + reusable; + status = "okay"; + }; + }; }; &hdmi { @@ -51,3 +71,17 @@ <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */ <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ }; + +&dsp { + status = "okay"; + memory-region = <&dsp_cma_pool>; + timers = <&timer5>; + watchdog-timers = <&timer6>; +}; + +&ipu { + status = "okay"; + memory-region = <&ipu_cma_pool>; + timers = <&timer3>; + watchdog-timers = <&timer9>, <&timer11>; +}; diff -Naur --no-dereference a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile --- a/arch/arm/boot/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/boot/Makefile 2016-05-11 13:31:53.189225170 -0400 @@ -27,6 +27,10 @@ targets := Image zImage xipImage bootpImage uImage +ifeq ($(CONFIG_OF_OVERLAY),y) +DTC_FLAGS += -@ +endif + ifeq ($(CONFIG_XIP_KERNEL),y) $(obj)/xipImage: vmlinux FORCE diff -Naur --no-dereference a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig --- a/arch/arm/configs/keystone_defconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/configs/keystone_defconfig 2016-05-11 13:31:53.193225201 -0400 @@ -30,6 +30,8 @@ CONFIG_PCI_MSI=y CONFIG_PCI_KEYSTONE=y CONFIG_SMP=y +CONFIG_HOTPLUG_CPU=y +CONFIG_ARM_PSCI=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y diff -Naur --no-dereference a/arch/arm/configs/rcn-ee_defconfig b/arch/arm/configs/rcn-ee_defconfig --- a/arch/arm/configs/rcn-ee_defconfig 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/configs/rcn-ee_defconfig 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,2454 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +# CONFIG_USELIB is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_KMEM=y +CONFIG_CGROUP_PERF=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_KPROBES=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_KARMA_PARTITION=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_OMAP_RESET_CLOCKS=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_SOC_OMAP5=y +CONFIG_SOC_AM33XX=y +CONFIG_SOC_AM43XX=y +CONFIG_SOC_DRA7XX=y +CONFIG_SOC_HAS_OMAP2_SDRC=y +CONFIG_ARM_THUMBEE=y +CONFIG_PL310_ERRATA_588369=y +CONFIG_PL310_ERRATA_727915=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_ARM_PSCI=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_HZ_250=y +CONFIG_THUMB2_KERNEL=y +CONFIG_KSM=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +CONFIG_ZSWAP=y +CONFIG_ZBUD=y +CONFIG_ZSMALLOC=m +CONFIG_SECCOMP=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_HIBERNATION=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_APM_EMULATION=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETLABEL=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=m +CONFIG_NF_TABLES_NETDEV=m +CONFIG_NFT_EXTHDR=m +CONFIG_NFT_META=m +CONFIG_NFT_CT=m +CONFIG_NFT_RBTREE=m +CONFIG_NFT_HASH=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NF_TABLES_ARP=m +CONFIG_NF_LOG_ARP=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m +CONFIG_NFT_MASQ_IPV6=m +CONFIG_NFT_REDIR_IPV6=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_IP_DCCP=m +CONFIG_NET_DCCPPROBE=m +CONFIG_NET_SCTPPROBE=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_RDS=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_CLS_IND=y +CONFIG_DCB=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_OPENVSWITCH=m +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=m +CONFIG_NET_MPLS_GSO=y +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=m +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_SOFTING=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_6LOWPAN=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_RXKAD=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_PN533=m +CONFIG_NFC_WILINK=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_LWTUNNEL=y +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="am335x-pm-firmware.elf am335x-bone-scale-data.bin am335x-evm-scale-data.bin am43x-evm-scale-data.bin" +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=24 +CONFIG_OMAP_OCP2SCP=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +CONFIG_MTD_OOPS=m +CONFIG_MTD_SWAP=m +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PLATRAM=m +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_M25P80=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC_BCH=y +CONFIG_MTD_NAND_OMAP2=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_ONENAND=y +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_LPDDR=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_OF_CONFIGFS=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_ZRAM=m +CONFIG_ZRAM_LZ4_COMPRESS=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_OSD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1780=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +CONFIG_TI_DAC7512=m +CONFIG_SRAM=y +CONFIG_BONE_CAPEMGR=y +CONFIG_TIEQEP=m +CONFIG_C2PORT=m +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93XX46=m +CONFIG_TI_ST=m +CONFIG_SENSORS_LIS3_SPI=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_CAPE_BONE_ARGUS=y +CONFIG_BEAGLEBONE_PINMUX_HELPER=y +CONFIG_RAID_ATTRS=m +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_UFSHCD=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_DELAY=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_EQUALIZER=m +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_ATM_DUMMY=m +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_KS8851=m +CONFIG_ENC28J60=m +CONFIG_ENCX24J600=m +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=m +CONFIG_SMC911X=m +CONFIG_SMSC911X=m +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +CONFIG_TI_CPSW=y +CONFIG_TI_CPTS=y +# CONFIG_NET_VENDOR_VIA is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_AMD_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_VITESSE_PHY=y +CONFIG_TERANETICS_PHY=m +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_STE10XP=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_DP83848_PHY=y +CONFIG_DP83867_PHY=m +CONFIG_FIXED_PHY=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_AT76C50X_USB=m +CONFIG_USB_ZD1201=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_RTL8187=m +CONFIG_MAC80211_HWSIM=m +CONFIG_ATH_CARDS=m +CONFIG_ATH9K=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_B43=m +CONFIG_B43_SDIO=y +CONFIG_B43LEGACY=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_MESH=y +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_WL_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_RTL8192CU=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8XXXU=m +CONFIG_WL_TI=y +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SPI=m +CONFIG_WLCORE_SDIO=m +CONFIG_ZD1211RW=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m +CONFIG_RSI_91X=m +# CONFIG_RSI_SDIO is not set +CONFIG_WIMAX_I2400M_USB=m +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_OMAP4=m +CONFIG_KEYBOARD_TWL4030=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +CONFIG_KEYBOARD_BCM=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_GTCO=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m +CONFIG_TOUCHSCREEN_DA9052=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_FT6236=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_IMX6UL_TSC=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_SUR40=m +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_MC13783_PWRBUTTON=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MPU3050=m +CONFIG_INPUT_GP2A=m +CONFIG_INPUT_GPIO_TILT_POLLED=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_KXTJ9_POLLED_MODE=y +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_TPS65218_PWRBUTTON=y +CONFIG_INPUT_AXP20X_PEK=y +CONFIG_INPUT_TWL4030_PWRBUTTON=y +CONFIG_INPUT_TWL4030_VIBRA=y +CONFIG_INPUT_TWL6040_VIBRA=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_PALMAS_PWRBUTTON=y +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA9052_ONKEY=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_N_GSM=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_OMAP=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=m +CONFIG_VIRTIO_CONSOLE=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m +CONFIG_SPI=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_OMAP24XX=m +CONFIG_SPI_TI_QSPI=m +CONFIG_SPI_SPIDEV=m +CONFIG_HSI=m +CONFIG_NTP_PPS=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_TI_IODELAY=y +CONFIG_PINCTRL_PALMAS=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_OF_HELPER=y +CONFIG_GPIO_SYSCON=y +CONFIG_GPIO_ADP5588=m +CONFIG_GPIO_ADNP=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_SX150X=y +CONFIG_GPIO_DA9052=m +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TWL4030=y +CONFIG_GPIO_TWL6040=y +CONFIG_GPIO_74X164=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_MCP23S08=m +CONFIG_GPIO_VIPERBOARD=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_HDQ_MASTER_OMAP=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_BQ27000=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_RX51=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_BQ2415X=m +CONFIG_POWER_AVS=y +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DA9052_ADC=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_MC13783_ADC=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=y +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_HTU21=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC2978_REGULATOR=y +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS1015=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TWL4030_MADC=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_THERMAL=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_CPU_THERMAL=y +CONFIG_CLOCK_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_TI_SOC_THERMAL=y +CONFIG_TI_THERMAL=y +CONFIG_OMAP5_THERMAL=y +CONFIG_DRA752_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_DA9052_WATCHDOG=m +CONFIG_OMAP_WATCHDOG=y +CONFIG_TWL4030_WATCHDOG=m +CONFIG_MFD_AS3722=y +CONFIG_MFD_AXP20X=y +CONFIG_MFD_DA9052_SPI=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MC13XXX_I2C=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_RTSX_USB=m +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_PALMAS=y +CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65218=y +CONFIG_MFD_TPS65910=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_POWER=y +CONFIG_TWL6040_CORE=y +CONFIG_MFD_WL1273_CORE=m +CONFIG_REGULATOR_ANATOP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MC13783=m +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_PBIAS=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_S2MPA01=m +CONFIG_REGULATOR_S2MPS11=m +CONFIG_REGULATOR_S5M8767=m +CONFIG_REGULATOR_TI_ABB=y +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y +CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65218=y +CONFIG_REGULATOR_TPS65910=y +CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_VEXPRESS=m +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_RC_MAP=m +CONFIG_LIRC=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_IMON=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_PWC=m +CONFIG_VIDEO_CPIA2=m +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160_AC97=y +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_FRIIO=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=m +CONFIG_SOC_CAMERA_PLATFORM=m +CONFIG_VIDEO_AM437X_VPFE=m +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_TI_VPE=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIVID=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_RADIO_SI470X=y +CONFIG_USB_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_USB_KEENE=m +CONFIG_USB_RAREMONO=m +CONFIG_USB_MA901=m +CONFIG_RADIO_WL128X=m +CONFIG_DRM=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_UDL=m +CONFIG_DRM_OMAP=y +CONFIG_DRM_OMAP_NUM_CRTCS=2 +CONFIG_OMAP2_DSS=y +CONFIG_OMAP5_DSS_HDMI=y +CONFIG_OMAP2_DSS_SDI=y +CONFIG_DISPLAY_ENCODER_OPA362=y +CONFIG_DISPLAY_ENCODER_TPD12S015=y +CONFIG_DISPLAY_CONNECTOR_DVI=y +CONFIG_DISPLAY_CONNECTOR_HDMI=y +CONFIG_DISPLAY_PANEL_DPI=y +CONFIG_DISPLAY_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_TILCDC=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_TILEBLITTING=y +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=y +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_SOC=m +CONFIG_SND_EDMA_SOC=m +CONFIG_SND_AM33XX_SOC_EVM=m +CONFIG_SND_AM33XX_SOC_WILINK8_BT=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_IMX_AUDMUX=m +CONFIG_SND_OMAP_SOC=m +CONFIG_SND_OMAP_SOC_RX51=m +CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m +CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CP2112=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_OTG=y +CONFIG_USB_MON=m +CONFIG_USB_WUSB_CBAF=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_U132_HCD=m +CONFIG_USB_HWA_HCD=m +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_DSPS=y +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_CHAOSKEY=m +CONFIG_AM335X_PHY_USB=y +CONFIG_USB_GPIO_VBUS=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_LED_TRIG=y +CONFIG_UWB=m +CONFIG_UWB_I1480U=m +CONFIG_MMC=y +CONFIG_SDIO_UART=m +CONFIG_MMC_OMAP=y +CONFIG_MMC_OMAP_HS=y +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_DA9052=m +CONFIG_LEDS_DAC124S085=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_REGULATOR=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MC13783=m +CONFIG_LEDS_TCA6507=m +CONFIG_LEDS_TLC591XX=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AS3722=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12057=y +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PALMAS=y +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF8523=y +CONFIG_RTC_DRV_PCF8563=y +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_TWL4030=y +CONFIG_RTC_DRV_TPS65910=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_DS3234=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_CMOS=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DA9052=y +CONFIG_RTC_DRV_STK17TA8=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_BQ4802=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_V3020=m +CONFIG_RTC_DRV_OMAP=y +CONFIG_RTC_DRV_MC13XXX=m +CONFIG_RTC_DRV_SNVS=y +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_DMADEVICES=y +CONFIG_DMA_OMAP=y +CONFIG_TI_CPPI41=y +CONFIG_TI_EDMA=y +CONFIG_DW_DMAC=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +CONFIG_STAGING=y +CONFIG_RTLLIB=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_ADIS16201=m +CONFIG_ADIS16203=m +CONFIG_ADIS16204=m +CONFIG_ADIS16209=m +CONFIG_ADIS16220=m +CONFIG_ADIS16240=m +CONFIG_LIS3L02DQ=m +CONFIG_SCA3000=m +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7780=m +CONFIG_AD7816=m +CONFIG_AD7192=m +CONFIG_AD7280=m +CONFIG_ADT7316=m +CONFIG_ADT7316_I2C=m +CONFIG_AD7150=m +CONFIG_AD7152=m +CONFIG_AD7746=m +CONFIG_AD9832=m +CONFIG_AD9834=m +CONFIG_ADIS16060=m +CONFIG_AD5933=m +CONFIG_SENSORS_ISL29018=m +CONFIG_SENSORS_ISL29028=m +CONFIG_TSL2583=m +CONFIG_TSL2x7x=m +CONFIG_ADE7753=m +CONFIG_ADE7754=m +CONFIG_ADE7758=m +CONFIG_ADE7759=m +CONFIG_ADE7854=m +CONFIG_AD2S90=m +CONFIG_AD2S1200=m +CONFIG_AD2S1210=m +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=m +CONFIG_SYNC=y +CONFIG_ION=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1325=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_FB_TFT_WATTEROTT=m +CONFIG_FB_FLEX=m +CONFIG_FB_TFT_FBTFT_DEVICE=m +CONFIG_COMMON_CLK_S2MPS11=m +CONFIG_CLK_TWL6040=y +CONFIG_COMMON_CLK_PALMAS=y +CONFIG_HWSPINLOCK_OMAP=y +CONFIG_ARM_TIMER_SP804=y +CONFIG_OMAP2PLUS_MBOX=y +CONFIG_OMAP_IOMMU=y +CONFIG_OMAP_REMOTEPROC=m +CONFIG_OMAP_REMOTEPROC_WATCHDOG=y +CONFIG_WKUP_M3_RPROC=y +CONFIG_PRUSS_REMOTEPROC=m +CONFIG_RPMSG_RPC=m +CONFIG_RPMSG_PRU=m +CONFIG_SOC_TI=y +CONFIG_AMX3_PM=y +CONFIG_WKUP_M3_IPC=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_EXTCON=y +CONFIG_EXTCON_GPIO=y +CONFIG_EXTCON_PALMAS=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_TI_EMIF=y +CONFIG_TI_EMIF_SRAM=y +CONFIG_IIO_SW_TRIGGER=m +CONFIG_BMA180=m +CONFIG_BMC150_ACCEL=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_KXSD9=m +CONFIG_KXCJK1013=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA8452=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +CONFIG_AD7266=m +CONFIG_AD7291=m +CONFIG_AD7298=m +CONFIG_AD7476=m +CONFIG_AD7791=m +CONFIG_AD7793=m +CONFIG_AD7887=m +CONFIG_AD7923=m +CONFIG_AD799X=m +CONFIG_AXP288_ADC=m +CONFIG_CC10001_ADC=m +CONFIG_HI8435=m +CONFIG_INA2XX_ADC=m +CONFIG_MAX1027=m +CONFIG_MAX1363=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_NAU7802=m +CONFIG_PALMAS_GPADC=m +CONFIG_TI_ADC081C=m +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS8688=m +CONFIG_TI_AM335X_ADC=m +CONFIG_TWL4030_MADC=m +CONFIG_TWL6030_GPADC=m +CONFIG_VF610_ADC=m +CONFIG_VIPERBOARD_ADC=m +CONFIG_AD8366=m +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_IAQCORE=m +CONFIG_VZ89X=m +CONFIG_IIO_SSP_SENSORHUB=m +CONFIG_AD5064=m +CONFIG_AD5360=m +CONFIG_AD5380=m +CONFIG_AD5421=m +CONFIG_AD5446=m +CONFIG_AD5449=m +CONFIG_AD5504=m +CONFIG_AD5624R_SPI=m +CONFIG_AD5686=m +CONFIG_AD5755=m +CONFIG_AD5761=m +CONFIG_AD5764=m +CONFIG_AD5791=m +CONFIG_AD7303=m +CONFIG_M62332=m +CONFIG_MAX517=m +CONFIG_MAX5821=m +CONFIG_MCP4725=m +CONFIG_MCP4922=m +CONFIG_VF610_DAC=m +CONFIG_IIO_SIMPLE_DUMMY=m +CONFIG_AD9523=m +CONFIG_ADF4350=m +CONFIG_ADIS16080=m +CONFIG_ADIS16130=m +CONFIG_ADIS16136=m +CONFIG_ADIS16260=m +CONFIG_ADXRS450=m +CONFIG_BMG160=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_ITG3200=m +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m +CONFIG_SI7005=m +CONFIG_SI7020=m +CONFIG_ADIS16400=m +CONFIG_ADIS16480=m +CONFIG_KMX61=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_ADJD_S311=m +CONFIG_AL3320A=m +CONFIG_APDS9300=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_CM32181=m +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM36651=m +CONFIG_GP2AP020A00F=m +CONFIG_ISL29125=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_RPR0521=m +CONFIG_LTR501=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_STK3310=m +CONFIG_TCS3414=m +CONFIG_TCS3472=m +CONFIG_SENSORS_TSL2563=m +CONFIG_TSL4531=m +CONFIG_US5182D=m +CONFIG_VCNL4000=m +CONFIG_AK09911=m +CONFIG_BMC150_MAGN=m +CONFIG_MAG3110=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_MMC35240=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_SENSORS_HMC5843_I2C=m +CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_MCP4531=m +CONFIG_TPL0102=m +CONFIG_BMP280=m +CONFIG_HID_SENSOR_PRESS=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +CONFIG_MPL3115=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_T5403=m +CONFIG_AS3935=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_SX9500=m +CONFIG_MLX90614=m +CONFIG_TMP006=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_PWM_OMAP_DMTIMER=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_TIECAP=m +CONFIG_PWM_TIEHRPWM=m +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m +CONFIG_OMAP_USB2=y +CONFIG_TI_PIPE3=y +CONFIG_RAS=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=y +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_LOGFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EXOFS_FS=m +CONFIG_AUFS_FS=m +CONFIG_AUFS_EXPORT=y +CONFIG_AUFS_XATTR=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CIFS=m +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_ACL=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SMB2=y +CONFIG_CIFS_FSCACHE=y +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_AFS_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_SPLIT=y +CONFIG_DEBUG_INFO_DWARF4=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_UNUSED_SYMBOLS=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_TIMER_STATS=y +CONFIG_DEBUG_LIST=y +CONFIG_NOTIFIER_ERROR_INJECTION=m +CONFIG_CPU_NOTIFIER_ERROR_INJECT=m +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_STACK_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_UPROBE_EVENT=y +CONFIG_TEST_USER_COPY=m +CONFIG_TEST_BPF=m +CONFIG_TEST_FIRMWARE=m +CONFIG_TEST_STATIC_KEYS=m +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_DEV_OMAP_SHAM=m +CONFIG_CRYPTO_DEV_OMAP_AES=m +CONFIG_CRYPTO_DEV_OMAP_DES=m +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set diff -Naur --no-dereference a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h --- a/arch/arm/include/asm/io.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/io.h 2016-05-11 13:31:53.193225201 -0400 @@ -399,6 +399,11 @@ #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_exec(resource_size_t res_cookie, size_t size); +void __iomem *ioremap_exec_nocache(resource_size_t res_cookie, size_t size); +#define ioremap_exec ioremap_exec +#define ioremap_exec_nocache ioremap_exec_nocache + void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap diff -Naur --no-dereference a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h --- a/arch/arm/include/asm/pgtable-3level.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/pgtable-3level.h 2016-05-11 13:31:53.193225201 -0400 @@ -78,7 +78,12 @@ #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ +#ifdef CONFIG_KEYSTONE2_DMA_COHERENT +/* SH[1:0], outer shareable */ +#define L_PTE_SHARED (_AT(pteval_t, 2) << 8) +#else #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#endif #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) diff -Naur --no-dereference a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h --- a/arch/arm/include/asm/pgtable-3level-hwdef.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/pgtable-3level-hwdef.h 2016-05-11 13:31:53.193225201 -0400 @@ -44,7 +44,11 @@ #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) #define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */ #define PMD_SECT_AP2 (_AT(pmdval_t, 1) << 7) /* read only */ +#ifdef CONFIG_KEYSTONE2_DMA_COHERENT +#define PMD_SECT_S (_AT(pmdval_t, 2) << 8) +#else #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) +#endif #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) #define PMD_SECT_nG (_AT(pmdval_t, 1) << 11) #define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53) @@ -73,7 +77,12 @@ #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */ #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */ #define PTE_AP2 (_AT(pteval_t, 1) << 7) /* AP[2] */ +#ifdef CONFIG_KEYSTONE2_DMA_COHERENT +/* SH[1:0], outer shareable */ +#define PTE_EXT_SHARED (_AT(pteval_t, 2) << 8) +#else #define PTE_EXT_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#endif #define PTE_EXT_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* nG */ #define PTE_EXT_PXN (_AT(pteval_t, 1) << 53) /* PXN */ diff -Naur --no-dereference a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h --- a/arch/arm/include/asm/smp_scu.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/smp_scu.h 2016-05-11 13:31:53.193225201 -0400 @@ -8,6 +8,7 @@ #ifndef __ASSEMBLER__ #include +#include static inline bool scu_a9_has_base(void) { diff -Naur --no-dereference a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h --- a/arch/arm/include/asm/switch_to.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/switch_to.h 2016-05-11 13:31:53.193225201 -0400 @@ -3,6 +3,13 @@ #include +#if defined CONFIG_PREEMPT_RT_FULL && defined CONFIG_HIGHMEM +void switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p); +#else +static inline void +switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p) { } +#endif + /* * For v7 SMP cores running a preemptible kernel we may be pre-empted * during a TLB maintenance operation, so execute an inner-shareable dsb @@ -25,6 +32,7 @@ #define switch_to(prev,next,last) \ do { \ __complete_pending_tlbi(); \ + switch_kmaps(prev, next); \ last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ } while (0) diff -Naur --no-dereference a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h --- a/arch/arm/include/asm/thread_info.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/asm/thread_info.h 2016-05-11 13:31:53.193225201 -0400 @@ -49,6 +49,7 @@ struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0 => preemptable, <0 => bug */ + int preempt_lazy_count; /* 0 => preemptable, <0 => bug */ mm_segment_t addr_limit; /* address limit */ struct task_struct *task; /* main task structure */ __u32 cpu; /* cpu */ @@ -142,7 +143,8 @@ #define TIF_SYSCALL_TRACE 4 /* syscall trace active */ #define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ #define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ -#define TIF_SECCOMP 7 /* seccomp syscall filtering active */ +#define TIF_SECCOMP 8 /* seccomp syscall filtering active */ +#define TIF_NEED_RESCHED_LAZY 7 #define TIF_NOHZ 12 /* in adaptive nohz mode */ #define TIF_USING_IWMMXT 17 @@ -152,6 +154,7 @@ #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) #define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) @@ -167,7 +170,8 @@ * Change these and you break ASM code in entry-common.S */ #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ - _TIF_NOTIFY_RESUME | _TIF_UPROBE) + _TIF_NOTIFY_RESUME | _TIF_UPROBE | \ + _TIF_NEED_RESCHED_LAZY) #endif /* __KERNEL__ */ #endif /* __ASM_ARM_THREAD_INFO_H */ diff -Naur --no-dereference a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S --- a/arch/arm/include/debug/omap2plus.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/include/debug/omap2plus.S 2016-05-11 13:31:53.193225201 -0400 @@ -40,6 +40,11 @@ /* AM33XX serial port */ #define AM33XX_UART1_BASE 0x44E09000 +#define AM33XX_UART2_BASE 0x48022000 +#define AM33XX_UART3_BASE 0x48024000 +#define AM33XX_UART4_BASE 0x481a6000 +#define AM33XX_UART5_BASE 0x481a8000 +#define AM33XX_UART6_BASE 0x481aa000 /* OMAP5 serial ports */ #define OMAP5_UART1_BASE OMAP2_UART1_BASE @@ -128,6 +133,29 @@ and \rp, \rp, #0x00ffffff b 97f #endif +#ifdef CONFIG_DEBUG_AM33XXUART2 + mov \rp, #UART_OFFSET(AM33XX_UART2_BASE) + b 98f +#endif +#ifdef CONFIG_DEBUG_AM33XXUART3 + mov \rp, #UART_OFFSET(AM33XX_UART3_BASE) + b 98f +#endif +#ifdef CONFIG_DEBUG_AM33XXUART4 + ldr \rp, =AM33XX_UART4_BASE + and \rp, \rp, #0x00ffffff + b 98f +#endif +#ifdef CONFIG_DEBUG_AM33XXUART5 + ldr \rp, =AM33XX_UART5_BASE + and \rp, \rp, #0x00ffffff + b 98f +#endif +#ifdef CONFIG_DEBUG_AM33XXUART6 + ldr \rp, =AM33XX_UART6_BASE + and \rp, \rp, #0x00ffffff + b 98f +#endif #ifdef CONFIG_DEBUG_ZOOM_UART ldr \rp, =ZOOM_UART_BASE str \rp, [\tmp, #0] @ omap_uart_phys diff -Naur --no-dereference a/arch/arm/Kconfig b/arch/arm/Kconfig --- a/arch/arm/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/Kconfig 2016-05-11 13:31:53.189225170 -0400 @@ -33,7 +33,7 @@ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 - select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 + select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !PREEMPT_RT_BASE select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) select HAVE_ARCH_TRACEHOOK @@ -68,6 +68,7 @@ select HAVE_PERF_EVENTS select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP + select HAVE_PREEMPT_LAZY select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_SYSCALL_TRACEPOINTS diff -Naur --no-dereference a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug --- a/arch/arm/Kconfig.debug 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/Kconfig.debug 2016-05-11 13:31:53.189225170 -0400 @@ -692,6 +692,46 @@ depends on ARCH_OMAP2PLUS select DEBUG_OMAP2PLUS_UART + config DEBUG_AM33XXUART2 + bool "Kernel low-level debugging messages via AM33XX/AM43XX UART2" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + Say Y here if you want kernel low-level debugging support + on AM33xx and AM43xx based platforms on the UART2. + + config DEBUG_AM33XXUART3 + bool "Kernel low-level debugging messages via AM33XX/AM43XX UART3" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + Say Y here if you want kernel low-level debugging support + on AM33xx and AM43xx based platforms on the UART3. + + config DEBUG_AM33XXUART4 + bool "Kernel low-level debugging messages via AM33XX/AM43XX UART4" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + Say Y here if you want kernel low-level debugging support + on AM33xx and AM43xx based platforms on the UART4. + + config DEBUG_AM33XXUART5 + bool "Kernel low-level debugging messages via AM33XX/AM43XX UART5" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + Say Y here if you want kernel low-level debugging support + on AM33xx and AM43xx based platforms on the UART5. + + config DEBUG_AM33XXUART6 + bool "Kernel low-level debugging messages via AM33XX/AM43XX UART6" + depends on ARCH_OMAP2PLUS + select DEBUG_OMAP2PLUS_UART + help + Say Y here if you want kernel low-level debugging support + on AM33xx and AM43xx based platforms on the UART6. + config DEBUG_ZOOM_UART bool "Kernel low-level debugging messages via Zoom2/3 UART" depends on ARCH_OMAP2PLUS diff -Naur --no-dereference a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c --- a/arch/arm/kernel/asm-offsets.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/asm-offsets.c 2016-05-11 13:31:53.193225201 -0400 @@ -65,6 +65,7 @@ BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TI_PREEMPT_LAZY, offsetof(struct thread_info, preempt_lazy_count)); DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); diff -Naur --no-dereference a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S --- a/arch/arm/kernel/entry-armv.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/entry-armv.S 2016-05-11 13:31:53.193225201 -0400 @@ -215,11 +215,18 @@ #ifdef CONFIG_PREEMPT get_thread_info tsk ldr r8, [tsk, #TI_PREEMPT] @ get preempt count - ldr r0, [tsk, #TI_FLAGS] @ get flags teq r8, #0 @ if preempt count != 0 + bne 1f @ return from exeption + ldr r0, [tsk, #TI_FLAGS] @ get flags + tst r0, #_TIF_NEED_RESCHED @ if NEED_RESCHED is set + blne svc_preempt @ preempt! + + ldr r8, [tsk, #TI_PREEMPT_LAZY] @ get preempt lazy count + teq r8, #0 @ if preempt lazy count != 0 movne r0, #0 @ force flags to 0 - tst r0, #_TIF_NEED_RESCHED + tst r0, #_TIF_NEED_RESCHED_LAZY blne svc_preempt +1: #endif svc_exit r5, irq = 1 @ return from exception @@ -234,6 +241,8 @@ 1: bl preempt_schedule_irq @ irq en/disable is done inside ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS tst r0, #_TIF_NEED_RESCHED + bne 1b + tst r0, #_TIF_NEED_RESCHED_LAZY reteq r8 @ go again b 1b #endif diff -Naur --no-dereference a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S --- a/arch/arm/kernel/entry-common.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/entry-common.S 2016-05-11 13:31:53.193225201 -0400 @@ -36,7 +36,9 @@ UNWIND(.cantunwind ) disable_irq_notrace @ disable interrupts ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing - tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK + tst r1, #((_TIF_SYSCALL_WORK | _TIF_WORK_MASK) & ~_TIF_SECCOMP) + bne fast_work_pending + tst r1, #_TIF_SECCOMP bne fast_work_pending /* perform architecture specific actions before user return */ @@ -62,8 +64,11 @@ str r0, [sp, #S_R0 + S_OFF]! @ save returned r0 disable_irq_notrace @ disable interrupts ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing - tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK + tst r1, #((_TIF_SYSCALL_WORK | _TIF_WORK_MASK) & ~_TIF_SECCOMP) + bne do_slower_path + tst r1, #_TIF_SECCOMP beq no_work_pending +do_slower_path: UNWIND(.fnend ) ENDPROC(ret_fast_syscall) diff -Naur --no-dereference a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c --- a/arch/arm/kernel/process.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/process.c 2016-05-11 13:31:53.193225201 -0400 @@ -319,6 +319,30 @@ } #ifdef CONFIG_MMU +/* + * CONFIG_SPLIT_PTLOCK_CPUS results in a page->ptl lock. If the lock is not + * initialized by pgtable_page_ctor() then a coredump of the vector page will + * fail. + */ +static int __init vectors_user_mapping_init_page(void) +{ + struct page *page; + unsigned long addr = 0xffff0000; + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + + pgd = pgd_offset_k(addr); + pud = pud_offset(pgd, addr); + pmd = pmd_offset(pud, addr); + page = pmd_page(*(pmd)); + + pgtable_page_ctor(page); + + return 0; +} +late_initcall(vectors_user_mapping_init_page); + #ifdef CONFIG_KUSER_HELPERS /* * The vectors page is always readable from user space for the diff -Naur --no-dereference a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c --- a/arch/arm/kernel/signal.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/signal.c 2016-05-11 13:31:53.193225201 -0400 @@ -572,7 +572,8 @@ */ trace_hardirqs_off(); do { - if (likely(thread_flags & _TIF_NEED_RESCHED)) { + if (likely(thread_flags & (_TIF_NEED_RESCHED | + _TIF_NEED_RESCHED_LAZY))) { schedule(); } else { if (unlikely(!user_mode(regs))) diff -Naur --no-dereference a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c --- a/arch/arm/kernel/smp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/smp.c 2016-05-11 13:31:53.193225201 -0400 @@ -230,8 +230,6 @@ flush_cache_louis(); local_flush_tlb_all(); - clear_tasks_mm_cpumask(cpu); - return 0; } @@ -247,6 +245,9 @@ pr_err("CPU%u: cpu didn't die\n", cpu); return; } + + clear_tasks_mm_cpumask(cpu); + pr_notice("CPU%u: shutdown\n", cpu); /* diff -Naur --no-dereference a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c --- a/arch/arm/kernel/unwind.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kernel/unwind.c 2016-05-11 13:31:53.193225201 -0400 @@ -93,7 +93,7 @@ static const struct unwind_idx *__origin_unwind_idx; extern const struct unwind_idx __stop_unwind_idx[]; -static DEFINE_SPINLOCK(unwind_lock); +static DEFINE_RAW_SPINLOCK(unwind_lock); static LIST_HEAD(unwind_tables); /* Convert a prel31 symbol to an absolute address */ @@ -201,7 +201,7 @@ /* module unwind tables */ struct unwind_table *table; - spin_lock_irqsave(&unwind_lock, flags); + raw_spin_lock_irqsave(&unwind_lock, flags); list_for_each_entry(table, &unwind_tables, list) { if (addr >= table->begin_addr && addr < table->end_addr) { @@ -213,7 +213,7 @@ break; } } - spin_unlock_irqrestore(&unwind_lock, flags); + raw_spin_unlock_irqrestore(&unwind_lock, flags); } pr_debug("%s: idx = %p\n", __func__, idx); @@ -529,9 +529,9 @@ tab->begin_addr = text_addr; tab->end_addr = text_addr + text_size; - spin_lock_irqsave(&unwind_lock, flags); + raw_spin_lock_irqsave(&unwind_lock, flags); list_add_tail(&tab->list, &unwind_tables); - spin_unlock_irqrestore(&unwind_lock, flags); + raw_spin_unlock_irqrestore(&unwind_lock, flags); return tab; } @@ -543,9 +543,9 @@ if (!tab) return; - spin_lock_irqsave(&unwind_lock, flags); + raw_spin_lock_irqsave(&unwind_lock, flags); list_del(&tab->list); - spin_unlock_irqrestore(&unwind_lock, flags); + raw_spin_unlock_irqrestore(&unwind_lock, flags); kfree(tab); } diff -Naur --no-dereference a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c --- a/arch/arm/kvm/arm.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kvm/arm.c 2016-05-11 13:31:53.193225201 -0400 @@ -498,18 +498,18 @@ struct kvm_vcpu *vcpu; kvm_for_each_vcpu(i, vcpu, kvm) { - wait_queue_head_t *wq = kvm_arch_vcpu_wq(vcpu); + struct swait_queue_head *wq = kvm_arch_vcpu_wq(vcpu); vcpu->arch.pause = false; - wake_up_interruptible(wq); + swake_up(wq); } } static void vcpu_sleep(struct kvm_vcpu *vcpu) { - wait_queue_head_t *wq = kvm_arch_vcpu_wq(vcpu); + struct swait_queue_head *wq = kvm_arch_vcpu_wq(vcpu); - wait_event_interruptible(*wq, ((!vcpu->arch.power_off) && + swait_event_interruptible(*wq, ((!vcpu->arch.power_off) && (!vcpu->arch.pause))); } @@ -568,7 +568,7 @@ * involves poking the GIC, which must be done in a * non-preemptible context. */ - preempt_disable(); + migrate_disable(); kvm_timer_flush_hwstate(vcpu); kvm_vgic_flush_hwstate(vcpu); @@ -587,7 +587,7 @@ local_irq_enable(); kvm_timer_sync_hwstate(vcpu); kvm_vgic_sync_hwstate(vcpu); - preempt_enable(); + migrate_enable(); continue; } @@ -641,7 +641,7 @@ kvm_vgic_sync_hwstate(vcpu); - preempt_enable(); + migrate_enable(); ret = handle_exit(vcpu, run, ret); } diff -Naur --no-dereference a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c --- a/arch/arm/kvm/psci.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/kvm/psci.c 2016-05-11 13:31:53.193225201 -0400 @@ -70,7 +70,7 @@ { struct kvm *kvm = source_vcpu->kvm; struct kvm_vcpu *vcpu = NULL; - wait_queue_head_t *wq; + struct swait_queue_head *wq; unsigned long cpu_id; unsigned long context_id; phys_addr_t target_pc; @@ -119,7 +119,7 @@ smp_mb(); /* Make sure the above is visible */ wq = kvm_arch_vcpu_wq(vcpu); - wake_up_interruptible(wq); + swake_up(wq); return PSCI_RET_SUCCESS; } diff -Naur --no-dereference a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c --- a/arch/arm/mach-at91/at91rm9200.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/at91rm9200.c 2016-05-11 13:31:53.193225201 -0400 @@ -12,7 +12,6 @@ #include #include -#include #include "generic.h" #include "soc.h" @@ -33,7 +32,6 @@ of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); - arm_pm_idle = at91rm9200_idle; at91rm9200_pm_init(); } diff -Naur --no-dereference a/arch/arm/mach-at91/at91sam9.c b/arch/arm/mach-at91/at91sam9.c --- a/arch/arm/mach-at91/at91sam9.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/at91sam9.c 2016-05-11 13:31:53.193225201 -0400 @@ -62,8 +62,6 @@ soc_dev = soc_device_to_device(soc); of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); - - arm_pm_idle = at91sam9_idle; } static void __init at91sam9_dt_device_init(void) diff -Naur --no-dereference a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h --- a/arch/arm/mach-at91/generic.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/generic.h 2016-05-11 13:31:53.193225201 -0400 @@ -11,27 +11,18 @@ #ifndef _AT91_GENERIC_H #define _AT91_GENERIC_H -#include -#include - - /* Map io */ -extern void __init at91_map_io(void); -extern void __init at91_alt_map_io(void); - -/* idle */ -extern void at91rm9200_idle(void); -extern void at91sam9_idle(void); - #ifdef CONFIG_PM extern void __init at91rm9200_pm_init(void); extern void __init at91sam9260_pm_init(void); extern void __init at91sam9g45_pm_init(void); extern void __init at91sam9x5_pm_init(void); +extern void __init sama5_pm_init(void); #else static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9260_pm_init(void) { } static inline void __init at91sam9g45_pm_init(void) { } static inline void __init at91sam9x5_pm_init(void) { } +static inline void __init sama5_pm_init(void) { } #endif #endif /* _AT91_GENERIC_H */ diff -Naur --no-dereference a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig --- a/arch/arm/mach-at91/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -99,6 +99,7 @@ config COMMON_CLK_AT91 bool select COMMON_CLK + select MFD_SYSCON config HAVE_AT91_SMD bool diff -Naur --no-dereference a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c --- a/arch/arm/mach-at91/pm.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/pm.c 2016-05-11 13:31:53.193225201 -0400 @@ -31,10 +31,13 @@ #include #include #include +#include #include "generic.h" #include "pm.h" +static void __iomem *pmc; + /* * FIXME: this is needed to communicate between the pinctrl driver and * the PM implementation in the machine. Possibly part of the PM @@ -87,7 +90,7 @@ unsigned long scsr; int i; - scsr = at91_pmc_read(AT91_PMC_SCSR); + scsr = readl(pmc + AT91_PMC_SCSR); /* USB must not be using PLLB */ if ((scsr & at91_pm_data.uhp_udp_mask) != 0) { @@ -101,8 +104,7 @@ if ((scsr & (AT91_PMC_PCK0 << i)) == 0) continue; - - css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; + css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS; if (css != AT91_PMC_CSS_SLOW) { pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); return 0; @@ -145,8 +147,8 @@ flush_cache_all(); outer_disable(); - at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0], - at91_ramc_base[1], pm_data); + at91_suspend_sram_fn(pmc, at91_ramc_base[0], + at91_ramc_base[1], pm_data); outer_resume(); } @@ -353,6 +355,21 @@ at91_pm_set_standby(standby); } +void at91rm9200_idle(void) +{ + /* + * Disable the processor clock. The processor will be automatically + * re-enabled by an interrupt or by a reset. + */ + writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); +} + +void at91sam9_idle(void) +{ + writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR); + cpu_do_idle(); +} + static void __init at91_pm_sram_init(void) { struct gen_pool *sram_pool; @@ -399,13 +416,36 @@ &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); } -static void __init at91_pm_init(void) +static const struct of_device_id atmel_pmc_ids[] __initconst = { + { .compatible = "atmel,at91rm9200-pmc" }, + { .compatible = "atmel,at91sam9260-pmc" }, + { .compatible = "atmel,at91sam9g45-pmc" }, + { .compatible = "atmel,at91sam9n12-pmc" }, + { .compatible = "atmel,at91sam9x5-pmc" }, + { .compatible = "atmel,sama5d3-pmc" }, + { .compatible = "atmel,sama5d2-pmc" }, + { /* sentinel */ }, +}; + +static void __init at91_pm_init(void (*pm_idle)(void)) { - at91_pm_sram_init(); + struct device_node *pmc_np; if (at91_cpuidle_device.dev.platform_data) platform_device_register(&at91_cpuidle_device); + pmc_np = of_find_matching_node(NULL, atmel_pmc_ids); + pmc = of_iomap(pmc_np, 0); + if (!pmc) { + pr_err("AT91: PM not supported, PMC not found\n"); + return; + } + + if (pm_idle) + arm_pm_idle = pm_idle; + + at91_pm_sram_init(); + if (at91_suspend_sram_fn) suspend_set_ops(&at91_pm_ops); else @@ -424,7 +464,7 @@ at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP; at91_pm_data.memctrl = AT91_MEMCTRL_MC; - at91_pm_init(); + at91_pm_init(at91rm9200_idle); } void __init at91sam9260_pm_init(void) @@ -432,7 +472,7 @@ at91_dt_ramc(); at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC; at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; - return at91_pm_init(); + at91_pm_init(at91sam9_idle); } void __init at91sam9g45_pm_init(void) @@ -440,7 +480,7 @@ at91_dt_ramc(); at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP; at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; - return at91_pm_init(); + at91_pm_init(at91sam9_idle); } void __init at91sam9x5_pm_init(void) @@ -448,5 +488,13 @@ at91_dt_ramc(); at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; - return at91_pm_init(); + at91_pm_init(at91sam9_idle); +} + +void __init sama5_pm_init(void) +{ + at91_dt_ramc(); + at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP; + at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR; + at91_pm_init(NULL); } diff -Naur --no-dereference a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c --- a/arch/arm/mach-at91/sama5.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-at91/sama5.c 2016-05-11 13:31:53.193225201 -0400 @@ -51,7 +51,7 @@ soc_dev = soc_device_to_device(soc); of_platform_populate(NULL, of_default_bus_match_table, NULL, soc_dev); - at91sam9x5_pm_init(); + sama5_pm_init(); } static const char *const sama5_dt_board_compat[] __initconst = { diff -Naur --no-dereference a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c --- a/arch/arm/mach-davinci/board-mityomapl138.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/board-mityomapl138.c 2016-05-11 13:31:53.193225201 -0400 @@ -115,13 +115,14 @@ static void mityomapl138_cpufreq_init(const char *partnum) { } #endif -static void read_factory_config(struct memory_accessor *a, void *context) +static void read_factory_config(struct nvmem_device *nvmem, void *context) { int ret; const char *partnum = NULL; struct davinci_soc_info *soc_info = &davinci_soc_info; - ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config)); + ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), + &factory_config); if (ret != sizeof(struct factory_config)) { pr_warn("Read Factory Config Failed: %d\n", ret); goto bad_config; diff -Naur --no-dereference a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c --- a/arch/arm/mach-davinci/common.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/common.c 2016-05-11 13:31:53.193225201 -0400 @@ -28,13 +28,13 @@ void __iomem *davinci_intc_base; int davinci_intc_type; -void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context) +void davinci_get_mac_addr(struct nvmem_device *nvmem, void *context) { char *mac_addr = davinci_soc_info.emac_pdata->mac_addr; off_t offset = (off_t)context; /* Read MAC addr from EEPROM */ - if (mem_acc->read(mem_acc, mac_addr, offset, ETH_ALEN) == ETH_ALEN) + if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN) pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr); } diff -Naur --no-dereference a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c --- a/arch/arm/mach-davinci/devices-da8xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/devices-da8xx.c 2016-05-11 13:31:53.193225201 -0400 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -233,16 +234,54 @@ .size_data = sizeof(da850_edma1_pdata), }; +static const struct dma_slave_map da830_edma_map[] = { + { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, + { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, + { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) }, + { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) }, + { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) }, + { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, + { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, + { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, + { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, + { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, + { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, +}; + int __init da830_register_edma(struct edma_rsv_info *rsv) { struct platform_device *edma_pdev; da8xx_edma0_pdata.rsv = rsv; + da8xx_edma0_pdata.slave_map = da830_edma_map; + da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map); + edma_pdev = platform_device_register_full(&da8xx_edma0_device); return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0; } +static const struct dma_slave_map da850_edma0_map[] = { + { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) }, + { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) }, + { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) }, + { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) }, + { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) }, + { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) }, + { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) }, + { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) }, + { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) }, + { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) }, + { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) }, +}; + +static const struct dma_slave_map da850_edma1_map[] = { + { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 28) }, + { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 29) }, +}; + int __init da850_register_edma(struct edma_rsv_info *rsv[2]) { struct platform_device *edma_pdev; @@ -252,11 +291,18 @@ da850_edma1_pdata.rsv = rsv[1]; } + da8xx_edma0_pdata.slave_map = da850_edma0_map; + da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map); + edma_pdev = platform_device_register_full(&da8xx_edma0_device); if (IS_ERR(edma_pdev)) { pr_warn("%s: Failed to register eDMA0\n", __func__); return PTR_ERR(edma_pdev); } + + da850_edma1_pdata.slave_map = da850_edma1_map; + da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map); + edma_pdev = platform_device_register_full(&da850_edma1_device); return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0; } diff -Naur --no-dereference a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c --- a/arch/arm/mach-davinci/dm355.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/dm355.c 2016-05-11 13:31:53.193225201 -0400 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -576,9 +577,28 @@ {-1, -1}, }; +static const struct dma_slave_map da355_edma_map[] = { + { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, + { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) }, + { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) }, + { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, + { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, + { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, + { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, + { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, + { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, + { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, + { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, + { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, + { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, +}; + static struct edma_soc_info dm355_edma_pdata = { .queue_priority_mapping = queue_priority_mapping, .default_queue = EVENTQ_1, + .slave_map = da355_edma_map, + .slavecnt = ARRAY_SIZE(da355_edma_map), }; static struct resource edma_resources[] = { diff -Naur --no-dereference a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c --- a/arch/arm/mach-davinci/dm365.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/dm365.c 2016-05-11 13:31:53.193225201 -0400 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -862,9 +863,30 @@ {-1, -1}, }; +static const struct dma_slave_map da365_edma_map[] = { + { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, + { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) }, + { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, + { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) }, + { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) }, + { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) }, + { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) }, + { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) }, + { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) }, + { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) }, + { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, + { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, + { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) }, + { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) }, +}; + static struct edma_soc_info dm365_edma_pdata = { .queue_priority_mapping = dm365_queue_priority_mapping, .default_queue = EVENTQ_3, + .slave_map = da365_edma_map, + .slavecnt = ARRAY_SIZE(da365_edma_map), }; static struct resource edma_resources[] = { diff -Naur --no-dereference a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c --- a/arch/arm/mach-davinci/dm644x.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/dm644x.c 2016-05-11 13:31:53.193225201 -0400 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -505,9 +506,20 @@ {-1, -1}, }; +static const struct dma_slave_map da644x_edma_map[] = { + { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) }, + { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) }, + { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, + { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, + { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) }, + { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) }, +}; + static struct edma_soc_info dm644x_edma_pdata = { .queue_priority_mapping = queue_priority_mapping, .default_queue = EVENTQ_1, + .slave_map = da644x_edma_map, + .slavecnt = ARRAY_SIZE(da644x_edma_map), }; static struct resource edma_resources[] = { diff -Naur --no-dereference a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c --- a/arch/arm/mach-davinci/dm646x.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-davinci/dm646x.c 2016-05-11 13:31:53.193225201 -0400 @@ -9,6 +9,7 @@ * or implied. */ #include +#include #include #include #include @@ -540,9 +541,19 @@ {-1, -1}, }; +static const struct dma_slave_map da646x_edma_map[] = { + { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) }, + { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) }, + { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) }, + { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) }, + { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) }, +}; + static struct edma_soc_info dm646x_edma_pdata = { .queue_priority_mapping = dm646x_queue_priority_mapping, .default_queue = EVENTQ_1, + .slave_map = da646x_edma_map, + .slavecnt = ARRAY_SIZE(da646x_edma_map), }; static struct resource edma_resources[] = { diff -Naur --no-dereference a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c --- a/arch/arm/mach-exynos/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-exynos/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -230,7 +230,7 @@ return (void __iomem *)(S5P_VA_SCU); } -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); static void exynos_secondary_init(unsigned int cpu) { @@ -243,8 +243,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr) @@ -308,7 +308,7 @@ * Set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from @@ -335,7 +335,7 @@ if (timeout == 0) { printk(KERN_ERR "cpu1 power enable failed"); - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return -ETIMEDOUT; } } @@ -381,7 +381,7 @@ * calibrations, then wait for it to finish */ fail: - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return pen_release != -1 ? ret : 0; } diff -Naur --no-dereference a/arch/arm/mach-hisi/platmcpm.c b/arch/arm/mach-hisi/platmcpm.c --- a/arch/arm/mach-hisi/platmcpm.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-hisi/platmcpm.c 2016-05-11 13:31:53.193225201 -0400 @@ -61,7 +61,7 @@ static void __iomem *sysctrl, *fabric; static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER]; -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); static u32 fabric_phys_addr; /* * [0]: bootwrapper physical address @@ -113,7 +113,7 @@ if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER) return -EINVAL; - spin_lock_irq(&boot_lock); + raw_spin_lock_irq(&boot_lock); if (hip04_cpu_table[cluster][cpu]) goto out; @@ -147,7 +147,7 @@ out: hip04_cpu_table[cluster][cpu]++; - spin_unlock_irq(&boot_lock); + raw_spin_unlock_irq(&boot_lock); return 0; } @@ -162,11 +162,11 @@ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); hip04_cpu_table[cluster][cpu]--; if (hip04_cpu_table[cluster][cpu] == 1) { /* A power_up request went ahead of us. */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return; } else if (hip04_cpu_table[cluster][cpu] > 1) { pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu); @@ -174,7 +174,7 @@ } last_man = hip04_cluster_is_down(cluster); - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); if (last_man) { /* Since it's Cortex A15, disable L2 prefetching. */ asm volatile( @@ -203,7 +203,7 @@ cpu >= HIP04_MAX_CPUS_PER_CLUSTER); count = TIMEOUT_MSEC / POLL_MSEC; - spin_lock_irq(&boot_lock); + raw_spin_lock_irq(&boot_lock); for (tries = 0; tries < count; tries++) { if (hip04_cpu_table[cluster][cpu]) goto err; @@ -211,10 +211,10 @@ data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); if (data & CORE_WFI_STATUS(cpu)) break; - spin_unlock_irq(&boot_lock); + raw_spin_unlock_irq(&boot_lock); /* Wait for clean L2 when the whole cluster is down. */ msleep(POLL_MSEC); - spin_lock_irq(&boot_lock); + raw_spin_lock_irq(&boot_lock); } if (tries >= count) goto err; @@ -231,10 +231,10 @@ goto err; if (hip04_cluster_is_down(cluster)) hip04_set_snoop_filter(cluster, 0); - spin_unlock_irq(&boot_lock); + raw_spin_unlock_irq(&boot_lock); return 1; err: - spin_unlock_irq(&boot_lock); + raw_spin_unlock_irq(&boot_lock); return 0; } #endif diff -Naur --no-dereference a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig --- a/arch/arm/mach-imx/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-imx/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -524,7 +524,7 @@ bool "i.MX6 Quad/DualLite support" select ARM_ERRATA_764369 if SMP select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if SMP + select HAVE_ARM_TWD select PCI_DOMAINS if PCI select PINCTRL_IMX6Q select SOC_IMX6 diff -Naur --no-dereference a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig --- a/arch/arm/mach-keystone/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-keystone/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -5,12 +5,20 @@ select ARM_GIC select HAVE_ARM_ARCH_TIMER select CLKSRC_MMIO + select ARCH_HAS_RESET_CONTROLLER select ARM_ERRATA_798181 if SMP select COMMON_CLK_KEYSTONE select ARCH_SUPPORTS_BIG_ENDIAN select ZONE_DMA if ARM_LPAE select MIGHT_HAVE_PCI select PCI_DOMAINS if PCI + select KEYSTONE2_DMA_COHERENT + select PM_GENERIC_DOMAINS if PM + select OMAP_GPMC + select PINCTRL help Support for boards based on the Texas Instruments Keystone family of SoCs. + +config KEYSTONE2_DMA_COHERENT + bool diff -Naur --no-dereference a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c --- a/arch/arm/mach-keystone/keystone.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-keystone/keystone.c 2016-05-11 13:31:53.193225201 -0400 @@ -100,6 +100,7 @@ "ti,k2hk", "ti,k2e", "ti,k2l", + "ti,k2g", "ti,keystone", NULL, }; diff -Naur --no-dereference a/arch/arm/mach-keystone/pm_domain.c b/arch/arm/mach-keystone/pm_domain.c --- a/arch/arm/mach-keystone/pm_domain.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-keystone/pm_domain.c 2016-05-11 13:31:53.193225201 -0400 @@ -27,10 +27,13 @@ static struct pm_clk_notifier_block platform_domain_notifier = { .pm_domain = &keystone_pm_domain, + .con_ids = { "fck", "ethss_clk", "osr_clk", "xge_clk", NULL }, }; static const struct of_device_id of_keystone_table[] = { - {.compatible = "ti,keystone"}, + {.compatible = "ti,k2hk"}, + {.compatible = "ti,k2e"}, + {.compatible = "ti,k2l"}, { /* end of list */ }, }; diff -Naur --no-dereference a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c --- a/arch/arm/mach-omap1/dma.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap1/dma.c 2016-05-11 13:31:53.193225201 -0400 @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -265,6 +266,42 @@ .num_res = 1, }; +/* OMAP730, OMAP850 */ +static const struct dma_slave_map omap7xx_sdma_map[] = { + { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, + { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) }, + { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) }, + { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) }, + { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) }, + { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) }, + { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) }, + { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) }, + { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) }, + { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) }, + { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) }, + { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) }, +}; + +/* OMAP1510, OMAP1610*/ +static const struct dma_slave_map omap1xxx_sdma_map[] = { + { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, + { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) }, + { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) }, + { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) }, + { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) }, + { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) }, + { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) }, + { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) }, + { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) }, + { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) }, + { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) }, + { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) }, + { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) }, + { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) }, + { "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) }, + { "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) }, +}; + static struct omap_system_dma_plat_info dma_plat_info __initdata = { .reg_map = reg_map, .channel_stride = 0x40, @@ -342,6 +379,14 @@ p.dma_attr = d; p.errata = configure_dma_errata(); + if (cpu_is_omap7xx()) { + p.slave_map = omap7xx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map); + } else { + p.slave_map = omap1xxx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map); + } + ret = platform_device_add_data(pdev, &p, sizeof(p)); if (ret) { dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", diff -Naur --no-dereference a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c --- a/arch/arm/mach-omap2/clock.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/clock.c 2016-05-11 13:31:53.193225201 -0400 @@ -225,5 +225,9 @@ if (omap_rev() == OMAP3430_REV_ES1_0) features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; + /* Errata I810 for omap5 / dra7 */ + if (soc_is_omap54xx() || soc_is_dra7xx()) + features.flags |= TI_CLK_ERRATA_I810; + ti_clk_setup_features(&features); } diff -Naur --no-dereference a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c --- a/arch/arm/mach-omap2/clockdomain.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/clockdomain.c 2016-05-11 13:31:53.193225201 -0400 @@ -1213,6 +1213,86 @@ } /** + * clkdm_hwmod_prevent_hwauto - prevent a future hwauto on a clock domain. + * @clkdm: struct clockdomain * + * @oh: struct omap_hwmod * of the enabled downstream hwmod + * + * Prevent future hwauto for this clkdm. This will only prevent future hwauto + * but not bring it out of hwauto. + */ +int clkdm_hwmod_prevent_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh) +{ + /* The clkdm attribute does not exist yet prior OMAP4 */ + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + return 0; + + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) + return -EINVAL; + + pwrdm_lock(clkdm->pwrdm.ptr); + clkdm->noidlecount++; + pwrdm_unlock(clkdm->pwrdm.ptr); + + return 0; +} + +/** + * clkdm_hwmod_allow_hwauto - allow future hwauto for this clkdm + * @clkdm: struct clockdomain * + * @oh: struct omap_hwmod * of the enabled downstream hwmod + * + * Allow future hwauto for this clkdm. It won't put clkdm into hwauto. + * use clkdm_hwmod_hwauto() for that. + */ +int clkdm_hwmod_allow_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh) +{ + /* The clkdm attribute does not exist yet prior OMAP4 */ + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + return 0; + + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) + return -EINVAL; + + pwrdm_lock(clkdm->pwrdm.ptr); + + if (clkdm->noidlecount == 0) { + pwrdm_unlock(clkdm->pwrdm.ptr); + WARN_ON(1); /* underflow */ + return -ERANGE; + } + + clkdm->noidlecount--; + pwrdm_unlock(clkdm->pwrdm.ptr); + + return 0; +} + +/** + * clkdm_hwmod_hwauto - put clkdm in hwauto + * @clkdm: struct clockdomain * + * @oh: struct omap_hwmod * of the enabled downstream hwmod + * + * Put clkdm in hwauto if we can. Checks noidlecount to see if we can. + */ +int clkdm_hwmod_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh) +{ + /* The clkdm attribute does not exist yet prior OMAP4 */ + if (cpu_is_omap24xx() || cpu_is_omap34xx()) + return 0; + + if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) + return -EINVAL; + + pwrdm_lock(clkdm->pwrdm.ptr); + if (clkdm->noidlecount == 0) + clkdm_allow_idle_nolock(clkdm); + + pwrdm_unlock(clkdm->pwrdm.ptr); + + return 0; +} + +/** * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm * @clkdm: struct clockdomain * * @oh: struct omap_hwmod * of the enabled downstream hwmod @@ -1295,3 +1375,49 @@ return 0; } +/** + * _clkdm_save_context - save the context for the control of this clkdm + * + * Due to a suspend or hibernation operation, the state of the registers + * controlling this clkdm will be lost, save their context. + */ +static int _clkdm_save_context(struct clockdomain *clkdm, void *ununsed) +{ + if (!arch_clkdm || !arch_clkdm->clkdm_save_context) + return -EINVAL; + + return arch_clkdm->clkdm_save_context(clkdm); +} + +/** + * _clkdm_restore_context - restore context for control of this clkdm + * + * Restore the register values for this clockdomain. + */ +static int _clkdm_restore_context(struct clockdomain *clkdm, void *ununsed) +{ + if (!arch_clkdm || !arch_clkdm->clkdm_restore_context) + return -EINVAL; + + return arch_clkdm->clkdm_restore_context(clkdm); +} + +/** + * clkdm_save_context - Saves the context for each registered clkdm + * + * Save the context for each registered clockdomain. + */ +void clkdm_save_context(void) +{ + clkdm_for_each(_clkdm_save_context, NULL); +} + +/** + * clkdm_restore_context - Restores the context for each registered clkdm + * + * Restore the context for each registered clockdomain. + */ +void clkdm_restore_context(void) +{ + clkdm_for_each(_clkdm_restore_context, NULL); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h --- a/arch/arm/mach-omap2/clockdomain.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/clockdomain.h 2016-05-11 13:31:53.193225201 -0400 @@ -114,6 +114,7 @@ * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact * @usecount: Usecount tracking + * @noidlecount: Noidle count tracking. Domain won't be auto idled this is > 0. * @node: list_head to link all clockdomains together * * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) @@ -138,7 +139,9 @@ struct clkdm_dep *wkdep_srcs; struct clkdm_dep *sleepdep_srcs; int usecount; + int noidlecount; struct list_head node; + u32 context; }; /** @@ -157,6 +160,8 @@ * @clkdm_deny_idle: Disable hw supervised idle transitions for clock domain * @clkdm_clk_enable: Put the clkdm in right state for a clock enable * @clkdm_clk_disable: Put the clkdm in right state for a clock disable + * @clkdm_save_context: Save the current clkdm context + * @clkdm_restore_context: Restore the clkdm context */ struct clkdm_ops { int (*clkdm_add_wkdep)(struct clockdomain *clkdm1, struct clockdomain *clkdm2); @@ -173,6 +178,8 @@ void (*clkdm_deny_idle)(struct clockdomain *clkdm); int (*clkdm_clk_enable)(struct clockdomain *clkdm); int (*clkdm_clk_disable)(struct clockdomain *clkdm); + int (*clkdm_save_context)(struct clockdomain *clkdm); + int (*clkdm_restore_context)(struct clockdomain *clkdm); }; int clkdm_register_platform_funcs(struct clkdm_ops *co); @@ -211,6 +218,12 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); +int clkdm_hwmod_prevent_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh); +int clkdm_hwmod_allow_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh); +int clkdm_hwmod_hwauto(struct clockdomain *clkdm, struct omap_hwmod *oh); + +void clkdm_save_context(void); +void clkdm_restore_context(void); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); diff -Naur --no-dereference a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c --- a/arch/arm/mach-omap2/clockdomains7xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -409,7 +409,7 @@ .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, .wkdep_srcs = l4sec_wkup_sleep_deps, .sleepdep_srcs = l4sec_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l3main1_7xx_clkdm = { @@ -461,7 +461,7 @@ .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST, .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS, .dep_bit = DRA7XX_IPU_STATDEP_SHIFT, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain mpu1_7xx_clkdm = { @@ -609,7 +609,7 @@ .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, .wkdep_srcs = cam_wkup_sleep_deps, .sleepdep_srcs = cam_wkup_sleep_deps, - .flags = CLKDM_CAN_HWSUP_SWSUP, + .flags = CLKDM_CAN_SWSUP, }; static struct clockdomain l4per_7xx_clkdm = { diff -Naur --no-dereference a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c --- a/arch/arm/mach-omap2/cm33xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/cm33xx.c 2016-05-11 13:31:53.193225201 -0400 @@ -72,6 +72,17 @@ return v; } +static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) +{ + u32 v; + + v = am33xx_cm_read_reg(inst, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + /** * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield * @inst: CM instance register offset (*_INST macro) @@ -336,6 +347,45 @@ return 0; } +/** + * am33xx_clkdm_save_context - Save the clockdomain transition context + * @clkdm: The clockdomain pointer whose context needs to be saved + * + * Save the clockdomain transition context. + */ +static int am33xx_clkdm_save_context(struct clockdomain *clkdm) +{ + clkdm->context = am33xx_cm_read_reg_bits(clkdm->cm_inst, + clkdm->clkdm_offs, AM33XX_CLKTRCTRL_MASK); + + return 0; +} + +/** + * am33xx_restore_save_context - Restore the clockdomain transition context + * @clkdm: The clockdomain pointer whose context needs to be restored + * + * Restore the clockdomain transition context. + */ +static int am33xx_clkdm_restore_context(struct clockdomain *clkdm) +{ + switch (clkdm->context) { + case OMAP34XX_CLKSTCTRL_DISABLE_AUTO: + am33xx_clkdm_deny_idle(clkdm); + break; + case OMAP34XX_CLKSTCTRL_FORCE_SLEEP: + am33xx_clkdm_sleep(clkdm); + break; + case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP: + am33xx_clkdm_wakeup(clkdm); + break; + case OMAP34XX_CLKSTCTRL_ENABLE_AUTO: + am33xx_clkdm_allow_idle(clkdm); + break; + } + return 0; +} + struct clkdm_ops am33xx_clkdm_operations = { .clkdm_sleep = am33xx_clkdm_sleep, .clkdm_wakeup = am33xx_clkdm_wakeup, @@ -343,6 +393,8 @@ .clkdm_deny_idle = am33xx_clkdm_deny_idle, .clkdm_clk_enable = am33xx_clkdm_clk_enable, .clkdm_clk_disable = am33xx_clkdm_clk_disable, + .clkdm_save_context = am33xx_clkdm_save_context, + .clkdm_restore_context = am33xx_clkdm_restore_context, }; static struct cm_ll_data am33xx_cm_ll_data = { diff -Naur --no-dereference a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c --- a/arch/arm/mach-omap2/cminst44xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/cminst44xx.c 2016-05-11 13:31:53.193225201 -0400 @@ -481,6 +481,47 @@ return 0; } +/** + * omap4_clkdm_save_context - Save the clockdomain modulemode context + * @clkdm: The clockdomain pointer whose context needs to be saved + * + * Save the clockdomain modulemode context. + */ +static int omap4_clkdm_save_context(struct clockdomain *clkdm) +{ + clkdm->context = omap4_cminst_read_inst_reg(clkdm->prcm_partition, + clkdm->cm_inst, + clkdm->clkdm_offs + + OMAP4_CM_CLKSTCTRL); + clkdm->context &= OMAP4430_MODULEMODE_MASK; + return 0; +} + +/** + * omap4_clkdm_restore_context - Restore the clockdomain modulemode context + * @clkdm: The clockdomain pointer whose context needs to be restored + * + * Restore the clockdomain modulemode context. + */ +static int omap4_clkdm_restore_context(struct clockdomain *clkdm) +{ + switch (clkdm->context) { + case OMAP34XX_CLKSTCTRL_DISABLE_AUTO: + omap4_clkdm_deny_idle(clkdm); + break; + case OMAP34XX_CLKSTCTRL_FORCE_SLEEP: + omap4_clkdm_sleep(clkdm); + break; + case OMAP34XX_CLKSTCTRL_FORCE_WAKEUP: + omap4_clkdm_wakeup(clkdm); + break; + case OMAP34XX_CLKSTCTRL_ENABLE_AUTO: + omap4_clkdm_allow_idle(clkdm); + break; + } + return 0; +} + struct clkdm_ops omap4_clkdm_operations = { .clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep, .clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep, @@ -505,6 +546,8 @@ .clkdm_deny_idle = omap4_clkdm_deny_idle, .clkdm_clk_enable = omap4_clkdm_clk_enable, .clkdm_clk_disable = omap4_clkdm_clk_disable, + .clkdm_save_context = omap4_clkdm_save_context, + .clkdm_restore_context = omap4_clkdm_restore_context, }; static struct cm_ll_data omap4xxx_cm_ll_data = { diff -Naur --no-dereference a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h --- a/arch/arm/mach-omap2/common.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/common.h 2016-05-11 13:31:53.193225201 -0400 @@ -77,6 +77,13 @@ } #endif +#if defined(CONFIG_PM) && (defined(CONFIG_SOC_AM33XX) || \ + defined(CONFIG_SOC_AM43XX)) +void amx3_common_pm_init(void); +#else +static inline void amx3_common_pm_init(void) { } +#endif + #ifdef CONFIG_OMAP_MUX int omap_mux_late_init(void); #else diff -Naur --no-dereference a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c --- a/arch/arm/mach-omap2/control.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/control.c 2016-05-11 13:31:53.193225201 -0400 @@ -631,8 +631,180 @@ omap3_ctrl_setup_d2d_padconf(); } + #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ +#if defined(CONFIG_PM) +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +static unsigned long am33xx_control_reg_offsets[] = { + AM33XX_CONTROL_SYSCONFIG_OFFSET, + AM33XX_CONTROL_STATUS_OFFSET, + AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET, + AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET, + AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET, + AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET, + AM33XX_CONTROL_BANDGAP_CTRL_OFFSET, + AM33XX_CONTROL_BANDGAP_TRIM_OFFSET, + AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET, + AM33XX_CONTROL_MOSC_CTRL_OFFSET, + AM33XX_CONTROL_RCOSC_CTRL_OFFSET, + AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET, + AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET, + AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET, + AM33XX_CONTROL_MMU_CFG_OFFSET, + AM33XX_CONTROL_TPTC_CFG_OFFSET, + AM33XX_CONTROL_USB_CTRL0_OFFSET, + AM33XX_CONTROL_USB_CTRL1_OFFSET, + AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET, + AM33XX_CONTROL_MREQPRIO_0_OFFSET, + AM33XX_CONTROL_MREQPRIO_1_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET, + AM33XX_CONTROL_SMRT_CTRL_OFFSET, + AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET, + AM33XX_CONTROL_VREF_CTRL_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET, + AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET, + AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET, + AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET, + AM33XX_CONTROL_RESET_ISO_OFFSET, +}; + +static unsigned long am43xx_control_reg_offsets[] = { + AM33XX_CONTROL_SYSCONFIG_OFFSET, + AM33XX_CONTROL_STATUS_OFFSET, + AM43XX_CONTROL_MPU_L2_CTRL_OFFSET, + AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET, + AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET, + AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET, + AM33XX_CONTROL_BANDGAP_CTRL_OFFSET, + AM33XX_CONTROL_BANDGAP_TRIM_OFFSET, + AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET, + AM33XX_CONTROL_MOSC_CTRL_OFFSET, + AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET, + AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET, + AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET, + AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET, + AM33XX_CONTROL_TPTC_CFG_OFFSET, + AM33XX_CONTROL_USB_CTRL0_OFFSET, + AM33XX_CONTROL_USB_CTRL1_OFFSET, + AM43XX_CONTROL_USB_CTRL2_OFFSET, + AM43XX_CONTROL_GMII_SEL_OFFSET, + AM43XX_CONTROL_MPUSS_CTRL_OFFSET, + AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET, + AM43XX_CONTROL_PWMSS_CTRL_OFFSET, + AM33XX_CONTROL_MREQPRIO_0_OFFSET, + AM33XX_CONTROL_MREQPRIO_1_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET, + AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET, + AM33XX_CONTROL_SMRT_CTRL_OFFSET, + AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET, + AM43XX_CONTROL_CQDETECT_STS_OFFSET, + AM43XX_CONTROL_CQDETECT_STS2_OFFSET, + AM43XX_CONTROL_VTP_CTRL_OFFSET, + AM33XX_CONTROL_VREF_CTRL_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET, + AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET, + AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET, + AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET, + AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET, + AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET, + AM33XX_CONTROL_RESET_ISO_OFFSET, +}; + +static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)]; + +/** + * am33xx_control_save_context - Save the wakeup domain registers + * + * Save the wkup domain registers + */ +void am33xx_control_save_context(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am33xx_control_reg_offsets); i++) + am33xx_control_vals[i] = omap_ctrl_readl( + am33xx_control_reg_offsets[i]); +} + +/** + * am33xx_control_restore_context - Restore the wakeup domain registers + * + * Restore the wkup domain registers + */ +void am33xx_control_restore_context(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am33xx_control_reg_offsets); i++) + omap_ctrl_writel(am33xx_control_vals[i], + am33xx_control_reg_offsets[i]); +} + +/** + * am43xx_control_save_context - Save the wakeup domain registers + * + * Save the wkup domain registers + */ +void am43xx_control_save_context(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) + am33xx_control_vals[i] = omap_ctrl_readl( + am43xx_control_reg_offsets[i]); +} + +/** + * am43xx_control_restore_context - Restore the wakeup domain registers + * + * Restore the wkup domain registers + */ +void am43xx_control_restore_context(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) + omap_ctrl_writel(am33xx_control_vals[i], + am43xx_control_reg_offsets[i]); +} +#endif /* CONFIG_PM */ +#endif /* CONFIG_SOC_AM33XX || CONFIG_SOC_AM43XX */ + struct control_init_data { int index; s16 offset; diff -Naur --no-dereference a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h --- a/arch/arm/mach-omap2/control.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/control.h 2016-05-11 13:31:53.193225201 -0400 @@ -409,6 +409,67 @@ #define AM33XX_DEV_FEATURE 0x604 #define AM33XX_SGX_MASK BIT(29) +/* Additional AM33XX/AM43XX CONTROL registers */ +#define AM33XX_CONTROL_SYSCONFIG_OFFSET 0x0010 +#define AM33XX_CONTROL_STATUS_OFFSET 0x0040 +#define AM43XX_CONTROL_MPU_L2_CTRL_OFFSET 0x01e0 +#define AM33XX_CONTROL_CORTEX_VBBLDO_CTRL_OFFSET 0x041c +#define AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET 0x0428 +#define AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET 0x042c +#define AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET 0x0444 +#define AM33XX_CONTROL_BANDGAP_CTRL_OFFSET 0x0448 +#define AM33XX_CONTROL_BANDGAP_TRIM_OFFSET 0x044c +#define AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET 0x0458 +#define AM33XX_CONTROL_MOSC_CTRL_OFFSET 0x0468 +#define AM33XX_CONTROL_RCOSC_CTRL_OFFSET 0x046c +#define AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET 0x0470 +#define AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET 0x0534 +#define AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET 0x0608 +#define AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET 0x060c +#define AM33XX_CONTROL_MMU_CFG_OFFSET 0x0610 +#define AM33XX_CONTROL_TPTC_CFG_OFFSET 0x0614 +#define AM33XX_CONTROL_USB_CTRL0_OFFSET 0x0620 +#define AM33XX_CONTROL_USB_CTRL1_OFFSET 0x0628 +#define AM33XX_CONTROL_USB_WKUP_CTRL_OFFSET 0x0648 +#define AM43XX_CONTROL_USB_CTRL2_OFFSET 0x064c +#define AM43XX_CONTROL_GMII_SEL_OFFSET 0x0650 +#define AM43XX_CONTROL_MPUSS_CTRL_OFFSET 0x0654 +#define AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET 0x0658 +#define AM43XX_CONTROL_PWMSS_CTRL_OFFSET 0x0664 +#define AM33XX_CONTROL_MREQPRIO_0_OFFSET 0x0670 +#define AM33XX_CONTROL_MREQPRIO_1_OFFSET 0x0674 +#define AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET 0x0690 +#define AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET 0x0694 +#define AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET 0x0698 +#define AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET 0x069c +#define AM33XX_CONTROL_SMRT_CTRL_OFFSET 0x06a0 +#define AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET 0x06a4 +#define AM43XX_CONTROL_CQDETECT_STS_OFFSET 0x0e00 +#define AM43XX_CONTROL_CQDETECT_STS2_OFFSET 0x0e08 +#define AM43XX_CONTROL_VTP_CTRL_OFFSET 0x0e0c +#define AM33XX_CONTROL_VREF_CTRL_OFFSET 0x0e14 +#define AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET 0x0f90 +#define AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET 0x0f94 +#define AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET 0x0f98 +#define AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET 0x0f9c +#define AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET 0x0fa0 +#define AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET 0x0fa4 +#define AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET 0x0fa8 +#define AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET 0x0fac +#define AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET 0x0fb0 +#define AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET 0x0fb4 +#define AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET 0x0fb8 +#define AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET 0x0fbc +#define AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET 0x0fc0 +#define AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET 0x0fc4 +#define AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET 0x0fc8 +#define AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET 0x0fcc +#define AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET 0x0fd0 +#define AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET 0x0fd4 +#define AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET 0x0fd8 +#define AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET 0x0fdc +#define AM33XX_CONTROL_RESET_ISO_OFFSET 0x1000 + /* CONTROL OMAP STATUS register to identify OMAP3 features */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c @@ -467,6 +528,10 @@ int omap2_control_base_init(void); int omap_control_init(void); void omap2_set_globals_control(void __iomem *ctrl); +extern void am33xx_control_save_context(void); +extern void am33xx_control_restore_context(void); +extern void am43xx_control_save_context(void); +extern void am43xx_control_restore_context(void); void __init omap3_control_legacy_iomap_init(void); #else #define omap_ctrl_readb(x) 0 diff -Naur --no-dereference a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c --- a/arch/arm/mach-omap2/devices.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/devices.c 2016-05-11 13:31:53.193225201 -0400 @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -66,32 +65,6 @@ } omap_postcore_initcall(omap3_l3_init); -#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE) -static inline void __init omap_init_mbox(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - struct omap_mbox_pdata *pdata; - - oh = omap_hwmod_lookup("mailbox"); - if (!oh) { - pr_err("%s: unable to find hwmod\n", __func__); - return; - } - if (!oh->dev_attr) { - pr_err("%s: hwmod doesn't have valid attrs\n", __func__); - return; - } - - pdata = (struct omap_mbox_pdata *)oh->dev_attr; - pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata)); - WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", - __func__, PTR_ERR(pdev)); -} -#else -static inline void omap_init_mbox(void) { } -#endif /* CONFIG_OMAP2PLUS_MBOX */ - static inline void omap_init_sti(void) {} #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) @@ -246,7 +219,6 @@ omap_init_audio(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { - omap_init_mbox(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); diff -Naur --no-dereference a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c --- a/arch/arm/mach-omap2/dma.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/dma.c 2016-05-11 13:31:53.193225201 -0400 @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -203,6 +204,108 @@ return errata; } +static const struct dma_slave_map omap24xx_sdma_map[] = { + { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) }, + { "omap-aes", "tx", SDMA_FILTER_PARAM(9) }, + { "omap-aes", "rx", SDMA_FILTER_PARAM(10) }, + { "omap-sham", "rx", SDMA_FILTER_PARAM(13) }, + { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) }, + { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) }, + { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) }, + { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) }, + { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) }, + { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) }, + { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) }, + { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) }, + { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) }, + { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) }, + { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) }, + { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) }, + { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) }, + { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) }, + { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) }, + { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) }, + { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) }, + { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) }, + { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) }, + { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) }, + { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) }, + { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) }, + { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) }, + { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) }, + { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) }, + { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) }, + { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) }, + { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) }, + { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) }, + { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) }, + { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) }, + { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) }, + { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) }, + { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) }, + { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) }, + { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) }, + { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) }, + { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) }, + { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) }, + { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) }, +}; + +static const struct dma_slave_map omap3xxx_sdma_map[] = { + { "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) }, + { "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) }, + { "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) }, + { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) }, + { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) }, + { "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) }, + { "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) }, + { "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) }, + { "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) }, + { "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) }, + { "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) }, + { "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) }, + { "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) }, + { "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) }, + { "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) }, + { "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) }, + { "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) }, + { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) }, + { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) }, + { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) }, + { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) }, + { "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) }, + { "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) }, + { "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) }, + { "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) }, + { "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) }, + { "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) }, + { "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) }, + { "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) }, + { "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) }, + { "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) }, + { "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) }, + { "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) }, + { "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) }, + { "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) }, + { "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) }, + { "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) }, + { "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) }, + { "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) }, + { "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) }, + { "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) }, + { "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) }, + { "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) }, + { "omap-aes", "tx", SDMA_FILTER_PARAM(65) }, + { "omap-aes", "rx", SDMA_FILTER_PARAM(66) }, + { "omap-sham", "rx", SDMA_FILTER_PARAM(69) }, + { "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) }, + { "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) }, + { "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) }, + { "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) }, + { "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) }, + { "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) }, +}; + static struct omap_system_dma_plat_info dma_plat_info __initdata = { .reg_map = reg_map, .channel_stride = 0x60, @@ -231,6 +334,20 @@ p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; p.errata = configure_dma_errata(); + if (!of_have_populated_dt()) { + if (soc_is_omap24xx()) { + p.slave_map = omap24xx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map); + } else if (soc_is_omap34xx() || soc_is_omap3630()) { + p.slave_map = omap3xxx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map); + } else { + pr_err("%s: The legacy DMA map is not provided!\n", + __func__); + return -ENODEV; + } + } + pdev = omap_device_build(name, 0, oh, &p, sizeof(p)); if (IS_ERR(pdev)) { pr_err("%s: Can't build omap_device for %s:%s.\n", diff -Naur --no-dereference a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c --- a/arch/arm/mach-omap2/gpio.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/gpio.c 2016-05-11 13:31:53.193225201 -0400 @@ -130,7 +130,6 @@ } pwrdm = omap_hwmod_get_pwrdm(oh); - pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); pdev = omap_device_build(name, id - 1, oh, pdata, sizeof(*pdata)); kfree(pdata); diff -Naur --no-dereference a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c --- a/arch/arm/mach-omap2/gpmc-nand.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/gpmc-nand.c 2016-05-11 13:31:53.193225201 -0400 @@ -97,10 +97,7 @@ gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); memset(&s, 0, sizeof(struct gpmc_settings)); - if (gpmc_nand_data->of_node) - gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); - else - gpmc_set_legacy(gpmc_nand_data, &s); + gpmc_set_legacy(gpmc_nand_data, &s); s.device_nand = true; @@ -121,8 +118,6 @@ if (err < 0) goto out_free_cs; - gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n"); err = -EINVAL; diff -Naur --no-dereference a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c --- a/arch/arm/mach-omap2/id.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/id.c 2016-05-11 13:31:53.193225201 -0400 @@ -667,9 +667,9 @@ case 0: omap_revision = DRA722_REV_ES1_0; break; + case 1: default: - /* If we have no new revisions */ - omap_revision = DRA722_REV_ES1_0; + omap_revision = DRA722_REV_ES2_0; break; } break; diff -Naur --no-dereference a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c --- a/arch/arm/mach-omap2/io.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/io.c 2016-05-11 13:31:53.193225201 -0400 @@ -654,6 +654,7 @@ void __init am33xx_init_late(void) { omap_common_late_init(); + amx3_common_pm_init(); } #endif @@ -678,6 +679,7 @@ { omap_common_late_init(); omap2_clk_enable_autoidle_all(); + amx3_common_pm_init(); } #endif @@ -738,7 +740,8 @@ #ifdef CONFIG_SOC_DRA7XX void __init dra7xx_init_early(void) { - omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); + omap2_set_globals_tap(DRA7XX_CLASS, + OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap2_control_base_init(); omap4_pm_init_early(); diff -Naur --no-dereference a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig --- a/arch/arm/mach-omap2/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -67,6 +67,7 @@ select HAVE_ARM_SCU select GENERIC_CLOCKEVENTS_BROADCAST select HAVE_ARM_TWD + select ARM_CPU_SUSPEND if PM config SOC_DRA7XX bool "TI DRA7XX" diff -Naur --no-dereference a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile --- a/arch/arm/mach-omap2/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/Makefile 2016-05-11 13:31:53.193225201 -0400 @@ -88,6 +88,8 @@ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common) obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-pm-common) +obj-$(CONFIG_SOC_AM33XX) += pm33xx-core.o sleep33xx.o +obj-$(CONFIG_SOC_AM43XX) += pm33xx-core.o sleep43xx.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -95,6 +97,8 @@ AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec) +AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec) endif @@ -223,8 +227,6 @@ # EMU peripherals obj-$(CONFIG_HW_PERF_EVENTS) += pmu.o -obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o - # OMAP2420 MSDI controller integration support ("MMC") obj-$(CONFIG_SOC_OMAP2420) += msdi.o @@ -261,3 +263,9 @@ obj-y += $(smsc911x-m) $(smsc911x-y) obj-y += common-board-devices.o twl-common.o dss-common.o + +obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o + +ifneq ($(CONFIG_OMAP_REMOTEPROC),) +obj-y += remoteproc.o +endif diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c --- a/arch/arm/mach-omap2/omap_device.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_device.c 2016-05-11 13:31:53.193225201 -0400 @@ -185,16 +185,63 @@ return ret; } +/** + * _omap_device_check_reidle_hwmods - check all hwmods in device for reidle flag + * @od: struct omap_device *od + * + * Checks underlying hwmods for reidle flag, if present, remove from hwmod + * list and set flag in omap_device to keep track. Returns 0. + */ +static int _omap_device_check_reidle_hwmods(struct omap_device *od) +{ + int i; + + for (i = 0; i < od->hwmods_cnt; i++) { + if (od->hwmods[i]->flags & HWMOD_NEEDS_REIDLE) { + od->flags |= OMAP_DEVICE_HAS_REIDLE_HWMODS; + omap_hwmod_disable_reidle(od->hwmods[i]); + } + } + + return 0; +} + static int _omap_device_notifier_call(struct notifier_block *nb, unsigned long event, void *dev) { struct platform_device *pdev = to_platform_device(dev); struct omap_device *od; + int i, err; switch (event) { case BUS_NOTIFY_DEL_DEVICE: - if (pdev->archdata.od) - omap_device_delete(pdev->archdata.od); + od = to_omap_device(pdev); + if (!od) + break; + + for (i = 0; i < od->hwmods_cnt; i++) { + /* shutdown hwmods */ + omap_hwmod_shutdown(od->hwmods[i]); + /* we don't remove clocks cause there's no API to do so */ + /* no harm done, since they will not be created next time */ + } + omap_device_delete(od); + break; + case BUS_NOTIFY_UNBOUND_DRIVER: + od = to_omap_device(pdev); + if (od && (od->_state == OMAP_DEVICE_STATE_ENABLED)) { + dev_info(dev, "enabled after unload, idling\n"); + err = omap_device_idle(pdev); + if (err) + dev_err(dev, "failed to idle\n"); + } + break; + case BUS_NOTIFY_BOUND_DRIVER: + od = to_omap_device(pdev); + if (od) { + od->_driver_status = BUS_NOTIFY_BOUND_DRIVER; + _omap_device_check_reidle_hwmods(od); + } break; case BUS_NOTIFY_ADD_DEVICE: if (pdev->dev.of_node) @@ -244,6 +291,24 @@ return ret; } +/** + * _omap_device_reidle_hwmods - call omap_hwmod_enable_reidle on all hwmods + * @od: struct omap_device *od + * + * Add all underlying hwmods to hwmod reidle list. Returns 0. + */ +static int _omap_device_reidle_hwmods(struct omap_device *od) +{ + int i; + + for (i = 0; i < od->hwmods_cnt; i++) + if (od->hwmods[i]->flags | HWMOD_NEEDS_REIDLE) + omap_hwmod_enable_reidle(od->hwmods[i]); + + /* XXX pass along return value here? */ + return 0; +} + /* Public functions for use by core code */ /** @@ -482,6 +547,9 @@ if (!od) return; + if (od->flags & OMAP_DEVICE_HAS_REIDLE_HWMODS) + _omap_device_reidle_hwmods(od); + od->pdev->archdata.od = NULL; kfree(od->hwmods); kfree(od); @@ -757,6 +825,8 @@ struct omap_device *od; od = to_omap_device(pdev); + if (!od) + return 0; if (od->_state != OMAP_DEVICE_STATE_ENABLED) { dev_warn(&pdev->dev, @@ -866,6 +936,7 @@ static int __init omap_device_init(void) { + omap_hwmod_setup_reidle(); bus_register_notifier(&platform_bus_type, &platform_nb); return 0; } diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h --- a/arch/arm/mach-omap2/omap_device.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_device.h 2016-05-11 13:31:53.193225201 -0400 @@ -39,6 +39,7 @@ /* omap_device.flags values */ #define OMAP_DEVICE_SUSPENDED BIT(0) +#define OMAP_DEVICE_HAS_REIDLE_HWMODS BIT(1) /** * struct omap_device - omap_device wrapper for platform_devices diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h 2016-05-11 13:31:53.193225201 -0400 @@ -36,17 +36,8 @@ extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio; extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0; -extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1; -extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1; extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2; -extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2; extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2; extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3; @@ -77,6 +68,7 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0; extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0; +extern struct omap_hwmod_ocp_if am33xx_l4_per__rng; extern struct omap_hwmod am33xx_l3_main_hwmod; extern struct omap_hwmod am33xx_l3_s_hwmod; @@ -89,6 +81,7 @@ extern struct omap_hwmod am33xx_prcm_hwmod; extern struct omap_hwmod am33xx_aes0_hwmod; extern struct omap_hwmod am33xx_sha0_hwmod; +extern struct omap_hwmod am33xx_rng_hwmod; extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod; @@ -98,17 +91,8 @@ extern struct omap_hwmod am33xx_dcan1_hwmod; extern struct omap_hwmod am33xx_elm_hwmod; extern struct omap_hwmod am33xx_epwmss0_hwmod; -extern struct omap_hwmod am33xx_ecap0_hwmod; -extern struct omap_hwmod am33xx_eqep0_hwmod; -extern struct omap_hwmod am33xx_ehrpwm0_hwmod; extern struct omap_hwmod am33xx_epwmss1_hwmod; -extern struct omap_hwmod am33xx_ecap1_hwmod; -extern struct omap_hwmod am33xx_eqep1_hwmod; -extern struct omap_hwmod am33xx_ehrpwm1_hwmod; extern struct omap_hwmod am33xx_epwmss2_hwmod; -extern struct omap_hwmod am33xx_ecap2_hwmod; -extern struct omap_hwmod am33xx_eqep2_hwmod; -extern struct omap_hwmod am33xx_ehrpwm2_hwmod; extern struct omap_hwmod am33xx_gpio1_hwmod; extern struct omap_hwmod am33xx_gpio2_hwmod; extern struct omap_hwmod am33xx_gpio3_hwmod; diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -176,28 +176,6 @@ .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ecap0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_eqep0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { - .master = &am33xx_epwmss0_hwmod, - .slave = &am33xx_ehrpwm0_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - - static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { { .pa_start = 0x48302000, @@ -215,27 +193,6 @@ .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ecap1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_eqep1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { - .master = &am33xx_epwmss1_hwmod, - .slave = &am33xx_ehrpwm1_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { { .pa_start = 0x48304000, @@ -253,27 +210,6 @@ .user = OCP_USER_MPU, }; -struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ecap2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_eqep2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - -struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { - .master = &am33xx_epwmss2_hwmod, - .slave = &am33xx_ehrpwm2_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - /* l3s cfg -> gpmc */ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .master = &am33xx_l3_s_hwmod, @@ -611,3 +547,11 @@ .addr = am33xx_aes0_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; + +/* l4 per -> rng */ +struct omap_hwmod_ocp_if am33xx_l4_per__rng = { + .master = &am33xx_l4_ls_hwmod, + .slave = &am33xx_rng_hwmod, + .clk = "rng_fck", + .user = OCP_USER_MPU, +}; diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -267,6 +267,33 @@ }, }; +/* rng */ +static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { + .rev_offs = 0x1fe0, + .sysc_offs = 0x1fe4, + .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, + .idlemodes = SIDLE_FORCE | SIDLE_NO, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class am33xx_rng_hwmod_class = { + .name = "rng", + .sysc = &am33xx_rng_sysc, +}; + +struct omap_hwmod am33xx_rng_hwmod = { + .name = "rng", + .class = &am33xx_rng_hwmod_class, + .clkdm_name = "l4ls_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "rng_fck", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* ocmcram */ static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { .name = "ocmcram", @@ -347,7 +374,8 @@ .name = "cpgmac0", .class = &am33xx_cpgmac0_hwmod_class, .clkdm_name = "cpsw_125mhz_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_NEEDS_REIDLE, .main_clk = "cpsw_125mhz_gclk", .mpu_rt_idx = 1, .prcm = { @@ -449,18 +477,6 @@ .sysc = &am33xx_epwmss_sysc, }; -static struct omap_hwmod_class am33xx_ecap_hwmod_class = { - .name = "ecap", -}; - -static struct omap_hwmod_class am33xx_eqep_hwmod_class = { - .name = "eqep", -}; - -struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { - .name = "ehrpwm", -}; - /* epwmss0 */ struct omap_hwmod am33xx_epwmss0_hwmod = { .name = "epwmss0", @@ -474,30 +490,6 @@ }, }; -/* ecap0 */ -struct omap_hwmod am33xx_ecap0_hwmod = { - .name = "ecap0", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep0 */ -struct omap_hwmod am33xx_eqep0_hwmod = { - .name = "eqep0", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm0 */ -struct omap_hwmod am33xx_ehrpwm0_hwmod = { - .name = "ehrpwm0", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* epwmss1 */ struct omap_hwmod am33xx_epwmss1_hwmod = { .name = "epwmss1", @@ -511,30 +503,6 @@ }, }; -/* ecap1 */ -struct omap_hwmod am33xx_ecap1_hwmod = { - .name = "ecap1", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep1 */ -struct omap_hwmod am33xx_eqep1_hwmod = { - .name = "eqep1", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm1 */ -struct omap_hwmod am33xx_ehrpwm1_hwmod = { - .name = "ehrpwm1", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* epwmss2 */ struct omap_hwmod am33xx_epwmss2_hwmod = { .name = "epwmss2", @@ -548,30 +516,6 @@ }, }; -/* ecap2 */ -struct omap_hwmod am33xx_ecap2_hwmod = { - .name = "ecap2", - .class = &am33xx_ecap_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* eqep2 */ -struct omap_hwmod am33xx_eqep2_hwmod = { - .name = "eqep2", - .class = &am33xx_eqep_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - -/* ehrpwm2 */ -struct omap_hwmod am33xx_ehrpwm2_hwmod = { - .name = "ehrpwm2", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - /* * 'gpio' class: for gpio 0,1,2,3 */ @@ -682,7 +626,7 @@ .class = &am33xx_gpmc_hwmod_class, .clkdm_name = "l3s_clkdm", /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ - .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, + .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS | HWMOD_NEEDS_REIDLE, .main_clk = "l3s_gclk", .prcm = { .omap4 = { @@ -918,6 +862,8 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = { .name = "rtc", .sysc = &am33xx_rtc_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; struct omap_hwmod am33xx_rtc_hwmod = { @@ -1169,7 +1115,8 @@ .name = "tptc0", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_NEEDS_REIDLE, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -1183,7 +1130,8 @@ .name = "tptc1", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_NEEDS_REIDLE, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -1197,7 +1145,8 @@ .name = "tptc2", .class = &am33xx_tptc_hwmod_class, .clkdm_name = "l3_clkdm", - .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_NEEDS_REIDLE, .main_clk = "l3_gclk", .prcm = { .omap4 = { @@ -1240,7 +1189,7 @@ .name = "uart2", .class = &uart_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_AM33XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1254,7 +1203,7 @@ .name = "uart3", .class = &uart_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_AM33XXUART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1267,7 +1216,7 @@ .name = "uart4", .class = &uart_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_AM33XXUART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1280,7 +1229,7 @@ .name = "uart5", .class = &uart_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_AM33XXUART5_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1293,7 +1242,7 @@ .name = "uart6", .class = &uart_class, .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE_ACT, + .flags = DEBUG_AM33XXUART6_FLAGS | HWMOD_SWSUP_SIDLE_ACT, .main_clk = "dpll_per_m2_div4_ck", .prcm = { .omap4 = { @@ -1395,6 +1344,7 @@ CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET); CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET); + CLKCTRL(am33xx_rng_hwmod, AM33XX_CM_PER_RNG_CLKCTRL_OFFSET); } static void omap_hwmod_am33xx_rst(void) @@ -1468,6 +1418,7 @@ CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET); CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET); + CLKCTRL(am33xx_rng_hwmod, AM43XX_CM_PER_RNG_CLKCTRL_OFFSET); } static void omap_hwmod_am43xx_rst(void) diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -305,7 +305,8 @@ .name = "usb_otg_hs", .class = &am33xx_usbotg_class, .clkdm_name = "l3s_clkdm", - .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | + HWMOD_NEEDS_REIDLE, .main_clk = "usbotg_fck", .prcm = { .omap4 = { @@ -503,41 +504,6 @@ .flags = OCPIF_SWSUP_IDLE, }; -/* rng */ -static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = { - .rev_offs = 0x1fe0, - .sysc_offs = 0x1fe4, - .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, - .idlemodes = SIDLE_FORCE | SIDLE_NO, - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class am33xx_rng_hwmod_class = { - .name = "rng", - .sysc = &am33xx_rng_sysc, -}; - -static struct omap_hwmod am33xx_rng_hwmod = { - .name = "rng", - .class = &am33xx_rng_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .flags = HWMOD_SWSUP_SIDLE, - .main_clk = "rng_fck", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -static struct omap_hwmod_ocp_if am33xx_l4_per__rng = { - .master = &am33xx_l4_ls_hwmod, - .slave = &am33xx_rng_hwmod, - .clk = "rng_fck", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__emif, &am33xx_mpu__l3_main, @@ -593,17 +559,8 @@ &am33xx_l4_ls__spinlock, &am33xx_l4_ls__elm, &am33xx_l4_ls__epwmss0, - &am33xx_epwmss0__ecap0, - &am33xx_epwmss0__eqep0, - &am33xx_epwmss0__ehrpwm0, &am33xx_l4_ls__epwmss1, - &am33xx_epwmss1__ecap1, - &am33xx_epwmss1__eqep1, - &am33xx_epwmss1__ehrpwm1, &am33xx_l4_ls__epwmss2, - &am33xx_epwmss2__ecap2, - &am33xx_epwmss2__eqep2, - &am33xx_epwmss2__ehrpwm2, &am33xx_l3_s__gpmc, &am33xx_l3_main__lcdc, &am33xx_l4_ls__mcspi0, diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -25,7 +25,6 @@ #include "l4_3xxx.h" #include #include -#include #include #include "soc.h" @@ -2957,80 +2956,40 @@ }; /* mmu isp */ - -static struct omap_mmu_dev_attr mmu_isp_dev_attr = { - .nr_tlb_entries = 8, -}; - static struct omap_hwmod omap3xxx_mmu_isp_hwmod; -static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { - { .irq = 24 + OMAP_INTC_START, }, - { .irq = -1 } -}; - -static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { - { - .pa_start = 0x480bd400, - .pa_end = 0x480bd47f, - .flags = ADDR_TYPE_RT, - }, - { } -}; /* l4_core -> mmu isp */ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { .master = &omap3xxx_l4_core_hwmod, .slave = &omap3xxx_mmu_isp_hwmod, - .addr = omap3xxx_mmu_isp_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { .name = "mmu_isp", .class = &omap3xxx_mmu_hwmod_class, - .mpu_irqs = omap3xxx_mmu_isp_irqs, .main_clk = "cam_ick", - .dev_attr = &mmu_isp_dev_attr, .flags = HWMOD_NO_IDLEST, }; /* mmu iva */ -static struct omap_mmu_dev_attr mmu_iva_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap3xxx_mmu_iva_hwmod; -static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { - { .irq = 28 + OMAP_INTC_START, }, - { .irq = -1 } -}; static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, }; -static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { - { - .pa_start = 0x5d000000, - .pa_end = 0x5d00007f, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l3_main -> iva mmu */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { .master = &omap3xxx_l3_main_hwmod, .slave = &omap3xxx_mmu_iva_hwmod, - .addr = omap3xxx_mmu_iva_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { .name = "mmu_iva", .class = &omap3xxx_mmu_hwmod_class, - .mpu_irqs = omap3xxx_mmu_iva_irqs, .clkdm_name = "iva2_clkdm", .rst_lines = omap3xxx_mmu_iva_resets, .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), @@ -3043,7 +3002,6 @@ .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, }, }, - .dev_attr = &mmu_iva_dev_attr, .flags = HWMOD_NO_IDLEST, }; diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -202,13 +202,6 @@ }, }; -static struct omap_hwmod am43xx_ehrpwm3_hwmod = { - .name = "ehrpwm3", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_epwmss4_hwmod = { .name = "epwmss4", .class = &am33xx_epwmss_hwmod_class, @@ -222,13 +215,6 @@ }, }; -static struct omap_hwmod am43xx_ehrpwm4_hwmod = { - .name = "ehrpwm4", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_epwmss5_hwmod = { .name = "epwmss5", .class = &am33xx_epwmss_hwmod_class, @@ -242,13 +228,6 @@ }, }; -static struct omap_hwmod am43xx_ehrpwm5_hwmod = { - .name = "ehrpwm5", - .class = &am33xx_ehrpwm_hwmod_class, - .clkdm_name = "l4ls_clkdm", - .main_clk = "l4ls_gclk", -}; - static struct omap_hwmod am43xx_spi2_hwmod = { .name = "spi2", .class = &am33xx_spi_hwmod_class, @@ -463,6 +442,31 @@ }, }; +static struct omap_hwmod_class_sysconfig am43xx_des_sysc = { + .rev_offs = 0x30, + .sysc_offs = 0x34, + .syss_offs = 0x38, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class am43xx_des_hwmod_class = { + .name = "des", + .sysc = &am43xx_des_sysc, +}; + +static struct omap_hwmod am43xx_des_hwmod = { + .name = "des", + .class = &am43xx_des_hwmod_class, + .clkdm_name = "l3_clkdm", + .main_clk = "l3_gclk", + .prcm = { + .omap4 = { + .clkctrl_offs = AM43XX_CM_PER_DES_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + /* dss */ static struct omap_hwmod am43xx_dss_core_hwmod = { @@ -744,13 +748,6 @@ .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = { - .master = &am43xx_epwmss3_hwmod, - .slave = &am43xx_ehrpwm3_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_epwmss4_hwmod, @@ -758,13 +755,6 @@ .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = { - .master = &am43xx_epwmss4_hwmod, - .slave = &am43xx_ehrpwm4_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_epwmss5_hwmod, @@ -772,13 +762,6 @@ .user = OCP_USER_MPU, }; -static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = { - .master = &am43xx_epwmss5_hwmod, - .slave = &am43xx_ehrpwm5_hwmod, - .clk = "l4ls_gclk", - .user = OCP_USER_MPU, -}; - static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = { .master = &am33xx_l4_ls_hwmod, .slave = &am43xx_spi2_hwmod, @@ -912,6 +895,13 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +static struct omap_hwmod_ocp_if am43xx_l3_main__des = { + .master = &am33xx_l3_main_hwmod, + .slave = &am43xx_des_hwmod, + .clk = "l3_gclk", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l4_wkup__synctimer, &am43xx_l4_ls__timer8, @@ -919,11 +909,8 @@ &am43xx_l4_ls__timer10, &am43xx_l4_ls__timer11, &am43xx_l4_ls__epwmss3, - &am43xx_epwmss3__ehrpwm3, &am43xx_l4_ls__epwmss4, - &am43xx_epwmss4__ehrpwm4, &am43xx_l4_ls__epwmss5, - &am43xx_epwmss5__ehrpwm5, &am43xx_l4_ls__mcspi2, &am43xx_l4_ls__mcspi3, &am43xx_l4_ls__mcspi4, @@ -962,6 +949,7 @@ &am33xx_l4_per__i2c2, &am33xx_l4_per__i2c3, &am33xx_l4_per__mailbox, + &am33xx_l4_per__rng, &am33xx_l4_ls__mcasp0, &am33xx_l4_ls__mcasp1, &am33xx_l4_ls__mmc0, @@ -982,17 +970,8 @@ &am33xx_l4_ls__spinlock, &am33xx_l4_ls__elm, &am33xx_l4_ls__epwmss0, - &am33xx_epwmss0__ecap0, - &am33xx_epwmss0__eqep0, - &am33xx_epwmss0__ehrpwm0, &am33xx_l4_ls__epwmss1, - &am33xx_epwmss1__ecap1, - &am33xx_epwmss1__eqep1, - &am33xx_epwmss1__ehrpwm1, &am33xx_l4_ls__epwmss2, - &am33xx_epwmss2__ecap2, - &am33xx_epwmss2__eqep2, - &am33xx_epwmss2__ehrpwm2, &am33xx_l3_s__gpmc, &am33xx_l4_ls__mcspi0, &am33xx_l4_ls__mcspi1, @@ -1004,6 +983,7 @@ &am33xx_cpgmac0__mdio, &am33xx_l3_main__sha0, &am33xx_l3_main__aes0, + &am43xx_l3_main__des, &am43xx_l4_ls__ocp2scp0, &am43xx_l4_ls__ocp2scp1, &am43xx_l3_s__usbotgss0, @@ -1020,9 +1000,21 @@ NULL, }; +static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = { + &am33xx_l4_wkup__rtc, + NULL, +}; + int __init am43xx_hwmod_init(void) { + int ret; + omap_hwmod_am43xx_reg(); omap_hwmod_init(); - return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); + + if (!(of_machine_is_compatible("ti,am438x"))) + ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs); + + return ret; } diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -30,7 +30,6 @@ #include #include -#include #include #include "omap_hwmod.h" @@ -551,7 +550,6 @@ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, }; @@ -1431,7 +1429,6 @@ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, - .modulemode = MODULEMODE_HWCTRL, }, }, }; @@ -2088,30 +2085,16 @@ /* mmu ipu */ -static struct omap_mmu_dev_attr mmu_ipu_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap44xx_mmu_ipu_hwmod; static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = { { .name = "mmu_cache", .rst_shift = 2 }, }; -static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = { - { - .pa_start = 0x55082000, - .pa_end = 0x550820ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l3_main_2 -> mmu_ipu */ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = { .master = &omap44xx_l3_main_2_hwmod, .slave = &omap44xx_mmu_ipu_hwmod, .clk = "l3_div_ck", - .addr = omap44xx_mmu_ipu_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -2130,35 +2113,20 @@ .modulemode = MODULEMODE_HWCTRL, }, }, - .dev_attr = &mmu_ipu_dev_attr, }; /* mmu dsp */ -static struct omap_mmu_dev_attr mmu_dsp_dev_attr = { - .nr_tlb_entries = 32, -}; - static struct omap_hwmod omap44xx_mmu_dsp_hwmod; static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = { { .name = "mmu_cache", .rst_shift = 1 }, }; -static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = { - { - .pa_start = 0x4a066000, - .pa_end = 0x4a0660ff, - .flags = ADDR_TYPE_RT, - }, - { } -}; - /* l4_cfg -> dsp */ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = { .master = &omap44xx_l4_cfg_hwmod, .slave = &omap44xx_mmu_dsp_hwmod, .clk = "l4_div_ck", - .addr = omap44xx_mmu_dsp_addrs, .user = OCP_USER_MPU | OCP_USER_SDMA, }; @@ -2177,7 +2145,6 @@ .modulemode = MODULEMODE_HWCTRL, }, }, - .dev_attr = &mmu_dsp_dev_attr, }; /* diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -335,6 +335,36 @@ }; /* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class omap54xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp */ +static struct omap_hwmod omap54xx_dsp_hwmod = { + .name = "dsp", + .class = &omap54xx_dsp_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap54xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_dsp_resets), + .main_clk = "dpll_iva_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * display sub-system */ @@ -941,6 +971,37 @@ }; /* + * 'ipu' class + * imaging processor unit + */ + +static struct omap_hwmod_class omap54xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu */ +static struct omap_hwmod omap54xx_ipu_hwmod = { + .name = "ipu", + .class = &omap54xx_ipu_hwmod_class, + .clkdm_name = "ipu_clkdm", + .rst_lines = omap54xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'kbd' class * keyboard controller */ @@ -2133,6 +2194,14 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* dsp -> l3_main_1 */ +static struct omap_hwmod_ocp_if omap54xx_dsp__l3_main_1 = { + .master = &omap54xx_dsp_hwmod, + .slave = &omap54xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mmu_dsp */ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { .master = &omap54xx_l4_cfg_hwmod, @@ -2165,6 +2234,14 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> ipu */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_ipu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_2 -> mmu_ipu */ static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { .master = &omap54xx_l3_main_2_hwmod, @@ -2764,7 +2841,9 @@ &omap54xx_l3_main_3__l3_instr, &omap54xx_l3_main_2__l3_main_1, &omap54xx_l4_cfg__l3_main_1, + &omap54xx_dsp__l3_main_1, &omap54xx_mpu__l3_main_1, + &omap54xx_l3_main_2__ipu, &omap54xx_l3_main_1__l3_main_2, &omap54xx_l4_cfg__l3_main_2, &omap54xx_l3_main_1__l3_main_3, diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -240,6 +240,142 @@ }; /* + * 'vpe' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_vpe_hwmod_class = { + .name = "vpe", + .sysc = &dra7xx_vpe_sysc, +}; + +/* vpe */ +static struct omap_hwmod dra7xx_vpe_hwmod = { + .name = "vpe", + .class = &dra7xx_vpe_hwmod_class, + .clkdm_name = "vpe_clkdm", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'vip' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_vip_hwmod_class = { + .name = "vip", + .sysc = &dra7xx_vip_sysc, +}; + +/* vip1 */ +static struct omap_hwmod dra7xx_vip1_hwmod = { + .name = "vip1", + .class = &dra7xx_vip_hwmod_class, + .clkdm_name = "cam_clkdm", + .main_clk = "vip1_gclk_mux", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* vip2 */ +static struct omap_hwmod dra7xx_vip2_hwmod = { + .name = "vip2", + .class = &dra7xx_vip_hwmod_class, + .clkdm_name = "cam_clkdm", + .main_clk = "vip2_gclk_mux", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* vip3 */ +static struct omap_hwmod dra7xx_vip3_hwmod = { + .name = "vip3", + .class = &dra7xx_vip_hwmod_class, + .clkdm_name = "cam_clkdm", + .main_clk = "vip3_gclk_mux", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'cal' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_cal_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_cal_hwmod_class = { + .name = "cal", + .sysc = &dra7xx_cal_sysc, +}; + +/* cal */ +static struct omap_hwmod dra7xx_cal_hwmod = { + .name = "cal", + .class = &dra7xx_cal_hwmod_class, + .clkdm_name = "cam_clkdm", + .main_clk = "vip2_gclk_mux", + .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'counter' class * */ @@ -383,6 +519,65 @@ }, }; +/* pwmss */ +static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &dra7xx_epwmss_sysc, +}; + +/* epwmss0 */ +struct omap_hwmod dra7xx_epwmss0_hwmod = { + .name = "epwmss0", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss1 */ +struct omap_hwmod dra7xx_epwmss1_hwmod = { + .name = "epwmss1", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss2 */ +struct omap_hwmod dra7xx_epwmss2_hwmod = { + .name = "epwmss2", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, + }, + }, +}; + /* * 'dma' class * @@ -430,6 +625,114 @@ }; /* + * 'tpcc' class + * + */ +static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = { + .name = "tpcc", +}; + +static struct omap_hwmod dra7xx_tpcc_hwmod = { + .name = "tpcc", + .class = &dra7xx_tpcc_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'tptc' class + * + */ +static struct omap_hwmod_class dra7xx_tptc_hwmod_class = { + .name = "tptc", +}; + +/* tptc0 */ +static struct omap_hwmod dra7xx_tptc0_hwmod = { + .name = "tptc0", + .class = &dra7xx_tptc_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* tptc1 */ +static struct omap_hwmod dra7xx_tptc1_hwmod = { + .name = "tptc1", + .class = &dra7xx_tptc_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'dsp' class + * dsp sub-system + */ + +static struct omap_hwmod_class dra7xx_dsp_hwmod_class = { + .name = "dsp", +}; + +static struct omap_hwmod_rst_info dra7xx_dsp_resets[] = { + { .name = "dsp", .rst_shift = 0 }, +}; + +/* dsp1 processor */ +static struct omap_hwmod dra7xx_dsp1_hwmod = { + .name = "dsp1", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + }, + }, +}; + +/* dsp2 processor */ +static struct omap_hwmod dra7xx_dsp2_hwmod = { + .name = "dsp2", + .class = &dra7xx_dsp_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'dss' class * */ @@ -567,6 +870,78 @@ .parent_hwmod = &dra7xx_dss_hwmod, }; +/* AES (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = { + .rev_offs = 0x0080, + .sysc_offs = 0x0084, + .syss_offs = 0x0088, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_aes_hwmod_class = { + .name = "aes", + .sysc = &dra7xx_aes_sysc, + .rev = 2, +}; + +/* AES1 */ +static struct omap_hwmod dra7xx_aes1_hwmod = { + .name = "aes1", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* AES2 */ +static struct omap_hwmod dra7xx_aes2_hwmod = { + .name = "aes2", + .class = &dra7xx_aes_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* sha0 HIB2 (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = { + .rev_offs = 0x100, + .sysc_offs = 0x110, + .syss_offs = 0x114, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_sha0_hwmod_class = { + .name = "sham", + .sysc = &dra7xx_sha0_sysc, + .rev = 2, +}; + +struct omap_hwmod dra7xx_sha0_hwmod = { + .name = "sham", + .class = &dra7xx_sha0_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'elm' class * @@ -855,6 +1230,40 @@ }; /* + * 'gpu' class + * 3d graphics accelerator + */ + +static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_gpu_hwmod_class = { + .name = "gpu", + .sysc = &dra7xx_gpu_sysc, +}; + +static struct omap_hwmod dra7xx_gpu_hwmod = { + .name = "gpu", + .class = &dra7xx_gpu_hwmod_class, + .clkdm_name = "gpu_clkdm", + .main_clk = "gpu_core_gclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'hdq1w' class * */ @@ -1005,6 +1414,54 @@ }; /* + * 'ipu' class + * imaging processor unit + */ + +static struct omap_hwmod_class dra7xx_ipu_hwmod_class = { + .name = "ipu", +}; + +static struct omap_hwmod_rst_info dra7xx_ipu_resets[] = { + { .name = "cpu0", .rst_shift = 0 }, + { .name = "cpu1", .rst_shift = 1 }, +}; + +/* ipu1 processor */ +static struct omap_hwmod dra7xx_ipu1_hwmod = { + .name = "ipu1", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + }, + }, +}; + +/* ipu2 processor */ +static struct omap_hwmod dra7xx_ipu2_hwmod = { + .name = "ipu2", + .class = &dra7xx_ipu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mailbox' class * */ @@ -1313,6 +1770,52 @@ .sysc = &dra7xx_mcasp_sysc, }; +/* mcasp1 */ +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "mcasp1_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), +}; + +/* mcasp2 */ +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp2_hwmod = { + .name = "mcasp2", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp2_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), +}; + /* mcasp3 */ static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, @@ -1335,6 +1838,116 @@ .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), }; +/* mcasp4 */ +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp4_hwmod = { + .name = "mcasp4", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp4_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), +}; + +/* mcasp5 */ +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp5_hwmod = { + .name = "mcasp5", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp5_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), +}; + +/* mcasp6 */ +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp6_hwmod = { + .name = "mcasp6", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp6_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), +}; + +/* mcasp7 */ +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp7_hwmod = { + .name = "mcasp7", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp7_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), +}; + +/* mcasp8 */ +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp8_hwmod = { + .name = "mcasp8", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp8_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), +}; + /* * 'mmc' class * @@ -1448,6 +2061,146 @@ }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mmu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &dra7xx_mmu_sysc, +}; + +/* DSP MMUs */ +static struct omap_hwmod_rst_info dra7xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +/* mmu0 - dsp1 */ +static struct omap_hwmod dra7xx_mmu0_dsp1_hwmod = { + .name = "mmu0_dsp1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu1 - dsp1 */ +static struct omap_hwmod dra7xx_mmu1_dsp1_hwmod = { + .name = "mmu1_dsp1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp1_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu0 - dsp2 */ +static struct omap_hwmod dra7xx_mmu0_dsp2_hwmod = { + .name = "mmu0_dsp2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu1 - dsp2 */ +static struct omap_hwmod dra7xx_mmu1_dsp2_hwmod = { + .name = "mmu1_dsp2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "dsp2_clkdm", + .rst_lines = dra7xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_dsp_resets), + .main_clk = "dpll_dsp_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* IPU MMUs */ +static struct omap_hwmod_rst_info dra7xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +/* mmu ipu1 */ +static struct omap_hwmod dra7xx_mmu_ipu1_hwmod = { + .name = "mmu_ipu1", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu1_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "ipu1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU1_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu ipu2 */ +static struct omap_hwmod dra7xx_mmu_ipu2_hwmod = { + .name = "mmu_ipu2", + .class = &dra7xx_mmu_hwmod_class, + .clkdm_name = "ipu2_clkdm", + .rst_lines = dra7xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_mmu_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_IPU2_RSTCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'mpu' class * */ @@ -1482,8 +2235,7 @@ .syss_offs = 0x0014, .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .sysc_fields = &omap_hwmod_sysc_type1, }; @@ -1527,19 +2279,49 @@ * */ +/* + * As noted in documentation for _reset() in omap_hwmod.c, the stock reset + * functionality of OMAP HWMOD layer does not deassert the hardreset lines + * associated with an IP automatically leaving the driver to handle that + * by itself. This does not work for PCIeSS which needs the reset lines + * deasserted for the driver to start accessing registers. + * + * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset + * lines after asserting them. + */ +static int dra7xx_pciess_reset(struct omap_hwmod *oh) +{ + int i; + + for (i = 0; i < oh->rst_lines_cnt; i++) { + omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name); + omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name); + } + + return 0; +} + static struct omap_hwmod_class dra7xx_pciess_hwmod_class = { .name = "pcie", + .reset = dra7xx_pciess_reset, }; /* pcie1 */ +static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = { + { .name = "pcie", .rst_shift = 0 }, +}; + static struct omap_hwmod dra7xx_pciess1_hwmod = { .name = "pcie1", .class = &dra7xx_pciess_hwmod_class, .clkdm_name = "pcie_clkdm", + .rst_lines = dra7xx_pciess1_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets), .main_clk = "l4_root_clk_div", .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, @@ -1547,14 +2329,22 @@ }; /* pcie2 */ +static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = { + { .name = "pcie", .rst_shift = 1 }, +}; + +/* pcie2 */ static struct omap_hwmod dra7xx_pciess2_hwmod = { .name = "pcie2", .class = &dra7xx_pciess_hwmod_class, .clkdm_name = "pcie_clkdm", + .rst_lines = dra7xx_pciess2_resets, + .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets), .main_clk = "l4_root_clk_div", .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET, + .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET, .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET, .modulemode = MODULEMODE_SWCTRL, }, @@ -1562,6 +2352,42 @@ }; /* + * 'pru-icss' class + * Programmable Real-Time Unit and Industrial Communication Subsystem + */ +static struct omap_hwmod_class dra7xx_pruss_hwmod_class = { + .name = "pruss", +}; + +/* pru-icss1 */ +static struct omap_hwmod dra7xx_pruss1_hwmod = { + .name = "pruss1", + .class = &dra7xx_pruss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* pru-icss2 */ +static struct omap_hwmod dra7xx_pruss2_hwmod = { + .name = "pruss2", + .class = &dra7xx_pruss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* * 'qspi' class * */ @@ -1609,6 +2435,8 @@ static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { .name = "rtcss", .sysc = &dra7xx_rtcss_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; /* rtcss */ @@ -1967,6 +2795,20 @@ }, }; +/* timer12 */ +static struct omap_hwmod dra7xx_timer12_hwmod = { + .name = "timer12", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "secure_32k_clk_src_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, + }, + }, +}; + /* timer13 */ static struct omap_hwmod dra7xx_timer13_hwmod = { .name = "timer13", @@ -2209,6 +3051,62 @@ }, }; +/* DES (the 'P' (public) device) */ +static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = { + .rev_offs = 0x0030, + .sysc_offs = 0x0034, + .syss_offs = 0x0038, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_des_hwmod_class = { + .name = "des", + .sysc = &dra7xx_des_sysc, +}; + +/* DES */ +static struct omap_hwmod dra7xx_des_hwmod = { + .name = "des", + .class = &dra7xx_des_hwmod_class, + .clkdm_name = "l4sec_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* rng */ +static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = { + .rev_offs = 0x1fe0, + .sysc_offs = 0x1fe4, + .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE, + .idlemodes = SIDLE_FORCE | SIDLE_NO, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_rng_hwmod_class = { + .name = "rng", + .sysc = &dra7xx_rng_sysc, +}; + +static struct omap_hwmod dra7xx_rng_hwmod = { + .name = "rng", + .class = &dra7xx_rng_hwmod_class, + .flags = HWMOD_SWSUP_SIDLE, + .clkdm_name = "l4sec_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + /* * 'usb_otg_ss' class * @@ -2240,6 +3138,7 @@ .class = &dra7xx_usb_otg_ss_hwmod_class, .clkdm_name = "l3init_clkdm", .main_clk = "dpll_core_h13x2_ck", + .flags = HWMOD_CLKDM_NOAUTO, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, @@ -2261,6 +3160,7 @@ .class = &dra7xx_usb_otg_ss_hwmod_class, .clkdm_name = "l3init_clkdm", .main_clk = "dpll_core_h13x2_ck", + .flags = HWMOD_CLKDM_NOAUTO, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, @@ -2438,6 +3338,54 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> mmu0_dsp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu0_dsp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu1_dsp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu1_dsp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu0_dsp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu0_dsp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu0_dsp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu1_dsp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu1_dsp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu1_dsp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu_ipu1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mmu_ipu2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mmu_ipu2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mmu_ipu2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l4_per1 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { .master = &dra7xx_l3_main_1_hwmod, @@ -2549,6 +3497,46 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> tpcc */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_tpcc_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_1 -> tptc0 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_tptc0_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_1 -> tptc1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_tptc1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* dsp1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp1__l3_main_1 = { + .master = &dra7xx_dsp1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* dsp2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = { + .master = &dra7xx_dsp2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { { .name = "family", @@ -2604,6 +3592,62 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> aes1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> aes2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_aes2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> sha0 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_sha0_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp3 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .master = &dra7xx_l4_per2_hwmod, @@ -2620,6 +3664,46 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> elm */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { .master = &dra7xx_l4_per1_hwmod, @@ -2676,6 +3760,27 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss0_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + /* l4_per1 -> gpio7 */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = { .master = &dra7xx_l4_per1_hwmod, @@ -2700,6 +3805,14 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_1 -> gpu */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_gpu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { { .pa_start = 0x480b2000, @@ -2758,6 +3871,22 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* ipu1 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu1__l3_main_1 = { + .master = &dra7xx_ipu1_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* ipu2 -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_ipu2__l3_main_1 = { + .master = &dra7xx_ipu2_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_cfg -> mailbox1 */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = { .master = &dra7xx_l4_cfg_hwmod, @@ -2982,6 +4111,22 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> pruss1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pruss1_hwmod, + .clk = "dpll_gmac_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> pruss2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pruss2 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_pruss2_hwmod, + .clk = "dpll_gmac_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { { .pa_start = 0x4b300000, @@ -3159,6 +4304,14 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_wkup -> timer12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_timer12_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per3 -> timer13 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { .master = &dra7xx_l4_per3_hwmod, @@ -3247,6 +4400,14 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per1 -> des */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_des_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> uart8 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { .master = &dra7xx_l4_per2_hwmod, @@ -3271,6 +4432,13 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per1 -> rng */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_rng_hwmod, + .user = OCP_USER_MPU, +}; + /* l4_per3 -> usb_otg_ss1 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { .master = &dra7xx_l4_per3_hwmod, @@ -3335,6 +4503,46 @@ .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per3 -> vpe */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_vpe_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> vip1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_vip1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> vip2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_vip2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> vip3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_vip3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> cal */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__cal = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_cal_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_wkup -> wd_timer2 */ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { .master = &dra7xx_l4_wkup_hwmod, @@ -3362,13 +4570,29 @@ &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, &dra7xx_l4_per2__cpgmac0, + &dra7xx_l4_per2__mcasp1, + &dra7xx_l3_main_1__mcasp1, + &dra7xx_l4_per2__mcasp2, + &dra7xx_l3_main_1__mcasp2, &dra7xx_l4_per2__mcasp3, &dra7xx_l3_main_1__mcasp3, + &dra7xx_l4_per2__mcasp4, + &dra7xx_l4_per2__mcasp5, + &dra7xx_l4_per2__mcasp6, + &dra7xx_l4_per2__mcasp7, + &dra7xx_l4_per2__mcasp8, &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, + &dra7xx_l3_main_1__tpcc, + &dra7xx_l3_main_1__tptc0, + &dra7xx_l3_main_1__tptc1, &dra7xx_l3_main_1__dss, &dra7xx_l3_main_1__dispc, + &dra7xx_dsp1__l3_main_1, &dra7xx_l3_main_1__hdmi, + &dra7xx_l3_main_1__aes1, + &dra7xx_l3_main_1__aes2, + &dra7xx_l3_main_1__sha0, &dra7xx_l4_per1__elm, &dra7xx_l4_wkup__gpio1, &dra7xx_l4_per1__gpio2, @@ -3379,12 +4603,15 @@ &dra7xx_l4_per1__gpio7, &dra7xx_l4_per1__gpio8, &dra7xx_l3_main_1__gpmc, + &dra7xx_l3_main_1__gpu, &dra7xx_l4_per1__hdq1w, &dra7xx_l4_per1__i2c1, &dra7xx_l4_per1__i2c2, &dra7xx_l4_per1__i2c3, &dra7xx_l4_per1__i2c4, &dra7xx_l4_per1__i2c5, + &dra7xx_ipu1__l3_main_1, + &dra7xx_ipu2__l3_main_1, &dra7xx_l4_cfg__mailbox1, &dra7xx_l4_per3__mailbox2, &dra7xx_l4_per3__mailbox3, @@ -3406,6 +4633,10 @@ &dra7xx_l4_per1__mmc2, &dra7xx_l4_per1__mmc3, &dra7xx_l4_per1__mmc4, + &dra7xx_l3_main_1__mmu0_dsp1, + &dra7xx_l3_main_1__mmu1_dsp1, + &dra7xx_l3_main_1__mmu_ipu1, + &dra7xx_l3_main_1__mmu_ipu2, &dra7xx_l4_cfg__mpu, &dra7xx_l4_cfg__ocp2scp1, &dra7xx_l4_cfg__ocp2scp3, @@ -3413,6 +4644,8 @@ &dra7xx_l4_cfg__pciess1, &dra7xx_l3_main_1__pciess2, &dra7xx_l4_cfg__pciess2, + &dra7xx_l4_cfg__pruss1, + &dra7xx_l4_cfg__pruss2, &dra7xx_l3_main_1__qspi, &dra7xx_l4_per3__rtcss, &dra7xx_l4_cfg__sata, @@ -3444,6 +4677,7 @@ &dra7xx_l4_per2__uart8, &dra7xx_l4_per2__uart9, &dra7xx_l4_wkup__uart10, + &dra7xx_l4_per1__des, &dra7xx_l4_per3__usb_otg_ss1, &dra7xx_l4_per3__usb_otg_ss2, &dra7xx_l4_per3__usb_otg_ss3, @@ -3451,16 +4685,35 @@ &dra7xx_l4_per2__vcp1, &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, + &dra7xx_l4_per3__vpe, + &dra7xx_l4_per3__vip1, &dra7xx_l4_wkup__wd_timer2, + &dra7xx_l4_per2__epwmss0, + &dra7xx_l4_per2__epwmss1, + &dra7xx_l4_per2__epwmss2, NULL, }; +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_wkup__timer12, + &dra7xx_l4_per1__rng, + NULL, +}; + +/* SoC variant specific hwmod links */ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, + &dra7xx_l4_per3__vip2, + &dra7xx_l4_per3__vip3, + &dra7xx_l3_main_1__mmu0_dsp2, + &dra7xx_l3_main_1__mmu1_dsp2, + &dra7xx_dsp2__l3_main_1, NULL, }; static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_per3__cal, NULL, }; @@ -3472,9 +4725,12 @@ ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); if (!ret && soc_is_dra74x()) - return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); else if (!ret && soc_is_dra72x()) - return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + + if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) + ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); return ret; } diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c --- a/arch/arm/mach-omap2/omap_hwmod.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod.c 2016-05-11 13:31:53.193225201 -0400 @@ -142,6 +142,7 @@ #include #include #include +#include #include @@ -208,6 +209,9 @@ /* omap_hwmod_list contains all registered struct omap_hwmods */ static LIST_HEAD(omap_hwmod_list); +/* oh_reidle_list contains all omap_hwmods with HWMOD_NEEDS_REIDLE set */ +LIST_HEAD(oh_reidle_list); + /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; @@ -2160,12 +2164,15 @@ r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : -EINVAL; if (!r) { + if (oh->clkdm && (oh->flags & HWMOD_CLKDM_NOAUTO)) + clkdm_hwmod_prevent_hwauto(oh->clkdm, oh); + /* * Set the clockdomain to HW_AUTO only if the target is ready, * assuming that the previous state was HW_AUTO */ if (oh->clkdm && hwsup) - clkdm_allow_idle(oh->clkdm); + clkdm_hwmod_hwauto(oh->clkdm, oh); oh->_state = _HWMOD_STATE_ENABLED; @@ -2207,15 +2214,15 @@ pr_debug("omap_hwmod: %s: idling\n", oh->name); + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", oh->name); return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -2232,8 +2239,15 @@ * transition to complete properly. */ _disable_clocks(oh); - if (oh->clkdm) + + if (oh->clkdm) { + if (oh->flags & HWMOD_CLKDM_NOAUTO) { + clkdm_hwmod_allow_hwauto(oh->clkdm, oh); + clkdm_hwmod_hwauto(oh->clkdm, oh); + } + clkdm_hwmod_disable(oh->clkdm, oh); + } /* Mux pins for device idle if populated */ if (oh->mux && oh->mux->pads_dynamic) { @@ -2262,6 +2276,9 @@ int ret, i; u8 prev_state; + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", @@ -2269,9 +2286,6 @@ return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { @@ -2388,6 +2402,28 @@ } /** + * _setup_reidle- check hwmod @oh and add to reidle list + * @oh: struct omap_hwmod * + * @n: (unused) + * + * Check hwmod for HWMOD_NEEDS_REIDLE flag and add to list if + * necessary. Return 0 on success. + */ +static int _setup_reidle(struct omap_hwmod *oh, void *data) +{ + int ret; + + if (oh->flags & HWMOD_NEEDS_REIDLE) { + ret = omap_hwmod_enable_reidle(oh); + + if (!ret) + return ret; + } + + return 0; +} + +/** * _init_mpu_rt_base - populate the virtual address for a hwmod * @oh: struct omap_hwmod * to locate the virtual address * @data: (unused, caller should pass NULL) @@ -3112,6 +3148,54 @@ oh->prcm.omap4.rstst_offs); } +/** + * _reidle - enable then idle a single hwmod + * + * enables and then immediately reidles an hwmod, as certain hwmods may + * not have their sysconfig registers programmed in an idle friendly state + * by default + */ +static void _reidle(struct omap_hwmod *oh) +{ + pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); + + omap_hwmod_enable(oh); + omap_hwmod_softreset(oh); + omap_hwmod_idle(oh); +} + +/** + * _reidle_all - enable then idle all hwmods in oh_reidle_list + * + * Called by pm_notifier to make sure flagged modules do not block suspend + * after context loss. + */ +static int _reidle_all(void) +{ + struct omap_hwmod_list *oh_list_item = NULL; + + list_for_each_entry(oh_list_item, &oh_reidle_list, oh_list) { + _reidle(oh_list_item->oh); + } + + return 0; +} + +static int _omap_device_pm_notifier(struct notifier_block *self, + unsigned long action, void *dev) +{ + switch (action) { + case PM_POST_SUSPEND: + _reidle_all(); + } + + return NOTIFY_DONE; +} + +struct notifier_block pm_nb = { + .notifier_call = _omap_device_pm_notifier, +}; + /* Public functions */ u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) @@ -3323,6 +3407,52 @@ omap_core_initcall(omap_hwmod_setup_all); /** + * omap_hwmod_enable_reidle - add an omap_hwmod to reidle list + * @oh: struct omap_hwmod * + * + * Adds the omap_hwmod to the oh_reidle_list so it will gets enabled then idled + * after each suspend cycle. Returns 0 on success. + */ +int omap_hwmod_enable_reidle(struct omap_hwmod *oh) +{ + struct omap_hwmod_list *oh_list_item = NULL; + + oh_list_item = kzalloc(sizeof(*oh_list_item), GFP_KERNEL); + + if (!oh_list_item) + return -ENOMEM; + + oh_list_item->oh = oh; + list_add(&oh_list_item->oh_list, &oh_reidle_list); + + pr_debug("omap_hwmod: %s: added to reidle list\n", oh->name); + + return 0; +} + +/** + * omap_hwmod_disable_reidle - remove an omap_hwmod from reidle list + * @oh: struct omap_hwmod * + * + * Remove the omap_hwmod from the oh_reidle_list. Returns 0 on success. + */ +int omap_hwmod_disable_reidle(struct omap_hwmod *oh) +{ + struct omap_hwmod_list *li, *oh_list_item = NULL; + + list_for_each_entry_safe(oh_list_item, li, &oh_reidle_list, oh_list) { + if (oh_list_item->oh == oh) { + list_del(&oh_list_item->oh_list); + pr_debug("omap_hwmod: %s: removed from reidle list\n", + oh->name); + kfree(oh_list_item); + } + } + + return 0; +} + +/** * omap_hwmod_enable - enable an omap_hwmod * @oh: struct omap_hwmod * * @@ -3930,6 +4060,21 @@ } /** + * omap_hwmod_setup_reidle - add hwmods to reidle list and register notifier + * + * Returns 0 on success. + */ +int omap_hwmod_setup_reidle(void) +{ + omap_hwmod_for_each(_setup_reidle, NULL); + + if (!list_empty(&oh_reidle_list)) + register_pm_notifier(&pm_nb); + + return 0; +} + +/** * omap_hwmod_get_main_clk - get pointer to main clock name * @oh: struct omap_hwmod * * @@ -3943,3 +4088,70 @@ return oh->main_clk; } + +/** + * omap_hwmod_save_context - Saves the HW reset line state of submodules + * @oh: struct omap_hwmod * + * @unused: (unused, caller should pass NULL) + * + * Saves the HW reset line state of all the submodules in the hwmod + */ +static int omap_hwmod_save_context(struct omap_hwmod *oh, void *unused) +{ + int i; + + for (i = 0; i < oh->rst_lines_cnt; i++) + oh->rst_lines[i].context = + _read_hardreset(oh, oh->rst_lines[i].name); + return 0; +} + +/** + * omap_hwmod_restore_context - Restores the HW reset line state of submodules + * @oh: struct omap_hwmod * + * @unused: (unused, caller should pass NULL) + * + * Restores the HW reset line state of all the submodules in the hwmod + */ +static int omap_hwmod_restore_context(struct omap_hwmod *oh, void *unused) +{ + int i; + + for (i = 0; i < oh->rst_lines_cnt; i++) + if (oh->rst_lines[i].context) + _assert_hardreset(oh, oh->rst_lines[i].name); + else if (oh->_state == _HWMOD_STATE_ENABLED) + _deassert_hardreset(oh, oh->rst_lines[i].name); + + if (oh->_state == _HWMOD_STATE_ENABLED) { + if (soc_ops.enable_module) + soc_ops.enable_module(oh); + } else { + if (oh->flags & HWMOD_NEEDS_REIDLE) + _reidle(oh); + else if (soc_ops.disable_module) + soc_ops.disable_module(oh); + } + + return 0; +} + +/** + * omap_hwmods_save_context - Saves the HW reset line state for all hwmods + * + * Saves the HW reset line state of all the registered hwmods + */ +void omap_hwmods_save_context(void) +{ + omap_hwmod_for_each(omap_hwmod_save_context, NULL); +} + +/** + * omap_hwmods_restore_context - Restores the HW reset line state for all hwmods + * + * Restores the HW reset line state of all the registered hwmods + */ +void omap_hwmods_restore_context(void) +{ + omap_hwmod_for_each(omap_hwmod_restore_context, NULL); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h --- a/arch/arm/mach-omap2/omap_hwmod.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod.h 2016-05-11 13:31:53.193225201 -0400 @@ -106,6 +106,11 @@ #define DEBUG_TI81XXUART2_FLAGS 0 #define DEBUG_TI81XXUART3_FLAGS 0 #define DEBUG_AM33XXUART1_FLAGS 0 +#define DEBUG_AM33XXUART2_FLAGS 0 +#define DEBUG_AM33XXUART3_FLAGS 0 +#define DEBUG_AM33XXUART4_FLAGS 0 +#define DEBUG_AM33XXUART5_FLAGS 0 +#define DEBUG_AM33XXUART6_FLAGS 0 #define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET) @@ -148,6 +153,21 @@ #elif defined(CONFIG_DEBUG_AM33XXUART1) #undef DEBUG_AM33XXUART1_FLAGS #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS +#elif defined(CONFIG_DEBUG_AM33XXUART2) +#undef DEBUG_AM33XXUART2_FLAGS +#define DEBUG_AM33XXUART2_FLAGS DEBUG_OMAPUART_FLAGS +#elif defined(CONFIG_DEBUG_AM33XXUART3) +#undef DEBUG_AM33XXUART3_FLAGS +#define DEBUG_AM33XXUART3_FLAGS DEBUG_OMAPUART_FLAGS +#elif defined(CONFIG_DEBUG_AM33XXUART4) +#undef DEBUG_AM33XXUART4_FLAGS +#define DEBUG_AM33XXUART4_FLAGS DEBUG_OMAPUART_FLAGS +#elif defined(CONFIG_DEBUG_AM33XXUART5) +#undef DEBUG_AM33XXUART5_FLAGS +#define DEBUG_AM33XXUART5_FLAGS DEBUG_OMAPUART_FLAGS +#elif defined(CONFIG_DEBUG_AM33XXUART6) +#undef DEBUG_AM33XXUART6_FLAGS +#define DEBUG_AM33XXUART6_FLAGS DEBUG_OMAPUART_FLAGS #endif /** @@ -207,6 +227,7 @@ const char *name; u8 rst_shift; u8 st_shift; + u8 context; }; /** @@ -527,6 +548,10 @@ * operate and they need to be handled at the same time as the main_clk. * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain * IPs like CPSW on DRA7, where clocks to this module cannot be disabled. + * HWMOD_NEEDS_REIDLE: Some devices do not assert their MSTANDBY signal by + * default after losing context if no driver is present and using the + * hwmod. This will break subsequent suspend cycles but can be fixed by + * enabling then idling the unused hwmod after each suspend cycle. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -544,6 +569,8 @@ #define HWMOD_RECONFIG_IO_CHAIN (1 << 13) #define HWMOD_OPT_CLKS_NEEDED (1 << 14) #define HWMOD_NO_IDLE (1 << 15) +#define HWMOD_NEEDS_REIDLE (1 << 16) +#define HWMOD_CLKDM_NOAUTO (1 << 17) /* * omap_hwmod._int_flags definitions @@ -694,7 +721,7 @@ struct list_head node; struct omap_hwmod_ocp_if *_mpu_port; unsigned int (*xlate_irq)(unsigned int); - u16 flags; + u32 flags; u8 mpu_rt_idx; u8 response_lat; u8 rst_lines_cnt; @@ -708,6 +735,14 @@ struct omap_hwmod *parent_hwmod; }; +/* + * omap_hwmod_list - simple generic container for omap_hwmod lists + */ +struct omap_hwmod_list { + struct omap_hwmod *oh; + struct list_head oh_list; +}; + struct omap_hwmod *omap_hwmod_lookup(const char *name); int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), void *data); @@ -737,6 +772,10 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); +int omap_hwmod_setup_reidle(void); +int omap_hwmod_enable_reidle(struct omap_hwmod *oh); +int omap_hwmod_disable_reidle(struct omap_hwmod *oh); + int omap_hwmod_for_each_by_class(const char *classname, int (*fn)(struct omap_hwmod *oh, void *user), @@ -749,11 +788,16 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); +void omap_hwmods_save_context(void); +void omap_hwmods_restore_context(void); + /* * */ extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); +void omap_hwmod_rtc_lock(struct omap_hwmod *oh); /* * Chip variant-specific hwmod init routines - XXX should be converted diff -Naur --no-dereference a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c --- a/arch/arm/mach-omap2/omap_hwmod_reset.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c 2016-05-11 13:31:53.193225201 -0400 @@ -29,6 +29,16 @@ #include #include "omap_hwmod.h" +#include "common.h" + +#define OMAP_RTC_STATUS_REG 0x44 +#define OMAP_RTC_KICK0_REG 0x6c +#define OMAP_RTC_KICK1_REG 0x70 + +#define OMAP_RTC_KICK0_VALUE 0x83E70B13 +#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0 +#define OMAP_RTC_STATUS_BUSY BIT(0) +#define OMAP_RTC_MAX_READY_TIME 50 /** * omap_hwmod_aess_preprogram - enable AESS internal autogating @@ -51,3 +61,58 @@ return 0; } + +/** + * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag + * @oh: struct omap_hwmod * + * + * For updating certain RTC registers, the MPU must wait + * for the BUSY status in OMAP_RTC_STATUS_REG to become zero. + * Once the BUSY status is zero, there is a 15 microseconds access + * period in which the MPU can program. + */ +static void omap_rtc_wait_not_busy(struct omap_hwmod *oh) +{ + int i; + + /* BUSY may stay active for 1/32768 second (~30 usec) */ + omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG) + & OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i); + /* now we have ~15 microseconds to read/write various registers */ +} + +/** + * omap_hwmod_rtc_unlock - Unlock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * In order to write into any of the RTC registers, KICK values has te be + * written in respective KICK registers. This is needed for hwmod to write into + * sysconfig register. + */ +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} + +/** + * omap_hwmod_rtc_lock - Lock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * Once the RTC registers are written, KICK mechanism needs to be locked, + * in order to prevent any spurious writes. This function locks back the RTC + * registers once hwmod completes its write into sysconfig register. + */ +void omap_hwmod_rtc_lock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c --- a/arch/arm/mach-omap2/omap-iommu.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap-iommu.c 2016-05-11 13:31:53.193225201 -0400 @@ -1,66 +1,88 @@ /* - * omap iommu: omap device registration + * OMAP IOMMU quirks for various TI SoCs * - * Copyright (C) 2008-2009 Nokia Corporation + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna * - * Written by Hiroshi DOYU + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ -#include #include #include -#include -#include -#include "soc.h" #include "omap_hwmod.h" #include "omap_device.h" +#include "clockdomain.h" +#include "powerdomain.h" -static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused) +static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, + bool enable) { - struct platform_device *pdev; - struct iommu_platform_data *pdata; - struct omap_mmu_dev_attr *a = (struct omap_mmu_dev_attr *)oh->dev_attr; - static int i; - - pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return -ENOMEM; - - pdata->name = oh->name; - pdata->nr_tlb_entries = a->nr_tlb_entries; - - if (oh->rst_lines_cnt == 1) { - pdata->reset_name = oh->rst_lines->name; - pdata->assert_reset = omap_device_assert_hardreset; - pdata->deassert_reset = omap_device_deassert_hardreset; + static struct clockdomain *emu_clkdm; + static DEFINE_SPINLOCK(emu_lock); + static atomic_t count; + struct device_node *np = pdev->dev.of_node; + + if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) + return; + + if (!emu_clkdm) { + emu_clkdm = clkdm_lookup("emu_clkdm"); + if (WARN_ON_ONCE(!emu_clkdm)) + return; } - pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata)); + spin_lock(&emu_lock); - kfree(pdata); + if (enable && (atomic_inc_return(&count) == 1)) + clkdm_deny_idle(emu_clkdm); + else if (!enable && (atomic_dec_return(&count) == 0)) + clkdm_allow_idle(emu_clkdm); - if (IS_ERR(pdev)) { - pr_err("%s: device build err: %ld\n", __func__, PTR_ERR(pdev)); - return PTR_ERR(pdev); - } - - i++; - - return 0; + spin_unlock(&emu_lock); } -static int __init omap_iommu_init(void) +int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, + u8 *pwrst) { - /* If dtb is there, the devices will be created dynamically */ - if (of_have_populated_dt()) + struct powerdomain *pwrdm; + struct omap_device *od; + u8 next_pwrst; + int ret = 0; + + od = to_omap_device(pdev); + if (!od) return -ENODEV; - return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL); + if (od->hwmods_cnt != 1) + return -EINVAL; + + pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]); + if (!pwrdm) + return -EINVAL; + + if (request) { + *pwrst = pwrdm_read_next_pwrst(pwrdm); + omap_iommu_dra7_emu_swsup_config(pdev, true); + } + + if (*pwrst > PWRDM_POWER_RET) + goto out; + + next_pwrst = request ? PWRDM_POWER_ON : *pwrst; + + ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst); + +out: + if (!request) + omap_iommu_dra7_emu_swsup_config(pdev, false); + + return ret; } -omap_subsys_initcall(omap_iommu_init); -/* must be ready before omap3isp is probed */ diff -Naur --no-dereference a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c --- a/arch/arm/mach-omap2/omap-smp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap-smp.c 2016-05-11 13:31:53.193225201 -0400 @@ -43,7 +43,7 @@ /* SCU base address */ static void __iomem *scu_base; -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); void __iomem *omap4_get_scu_base(void) { @@ -74,8 +74,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -89,7 +89,7 @@ * Set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * Update the AuxCoreBoot0 with boot state for secondary core. @@ -166,7 +166,7 @@ * Now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return 0; } diff -Naur --no-dereference a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c --- a/arch/arm/mach-omap2/omap-wakeupgen.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/omap-wakeupgen.c 2016-05-11 13:31:53.193225201 -0400 @@ -58,6 +58,17 @@ static unsigned int max_irqs = DEFAULT_IRQS; static unsigned int omap_secure_apis; +#ifdef CONFIG_CPU_PM +static unsigned int wakeupgen_context[MAX_NR_REG_BANKS]; +#endif + +struct omap_wakeupgen_ops { + void (*save_context)(void); + void (*restore_context)(void); +}; + +static struct omap_wakeupgen_ops *wakeupgen_ops; + /* * Static helper functions. */ @@ -264,6 +275,16 @@ } +static inline void am43xx_irq_save_context(void) +{ + u32 i; + + for (i = 0; i < irq_banks; i++) { + wakeupgen_context[i] = wakeupgen_readl(i, 0); + wakeupgen_writel(0, i, CPU0_ID); + } +} + /* * Save WakeupGen interrupt context in SAR BANK3. Restore is done by * ROM code. WakeupGen IP is integrated along with GIC to manage the @@ -276,11 +297,8 @@ { if (!sar_base) sar_base = omap4_get_sar_ram_base(); - - if (soc_is_omap54xx()) - omap5_irq_save_context(); - else - omap4_irq_save_context(); + if (wakeupgen_ops && wakeupgen_ops->save_context) + wakeupgen_ops->save_context(); } /* @@ -299,6 +317,20 @@ writel_relaxed(val, sar_base + offset); } +static void am43xx_irq_restore_context(void) +{ + u32 i; + + for (i = 0; i < irq_banks; i++) + wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID); +} + +static void irq_restore_context(void) +{ + if (wakeupgen_ops && wakeupgen_ops->restore_context) + wakeupgen_ops->restore_context(); +} + /* * Save GIC and Wakeupgen interrupt context using secure API * for HS/EMU devices. @@ -312,6 +344,26 @@ if (ret != API_HAL_RET_VALUE_OK) pr_err("GIC and Wakeupgen context save failed\n"); } + +/* Define ops for context save and restore for each SoC */ +static struct omap_wakeupgen_ops omap4_wakeupgen_ops = { + .save_context = omap4_irq_save_context, + .restore_context = irq_sar_clear, +}; + +static struct omap_wakeupgen_ops omap5_wakeupgen_ops = { + .save_context = omap5_irq_save_context, + .restore_context = irq_sar_clear, +}; + +static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = { + .save_context = am43xx_irq_save_context, + .restore_context = am43xx_irq_restore_context, +}; +#else +static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {}; +static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {}; +static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {}; #endif #ifdef CONFIG_HOTPLUG_CPU @@ -356,7 +408,7 @@ break; case CPU_CLUSTER_PM_EXIT: if (omap_type() == OMAP2_DEVICE_TYPE_GP) - irq_sar_clear(); + irq_restore_context(); break; } return NOTIFY_OK; @@ -491,9 +543,13 @@ irq_banks = OMAP4_NR_BANKS; max_irqs = OMAP4_NR_IRQS; omap_secure_apis = 1; + wakeupgen_ops = &omap4_wakeupgen_ops; + } else if (soc_is_omap54xx()) { + wakeupgen_ops = &omap5_wakeupgen_ops; } else if (soc_is_am43xx()) { irq_banks = AM43XX_NR_REG_BANKS; max_irqs = AM43XX_IRQS; + wakeupgen_ops = &am43xx_wakeupgen_ops; } domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs, diff -Naur --no-dereference a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c --- a/arch/arm/mach-omap2/pdata-quirks.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/pdata-quirks.c 2016-05-11 13:31:53.193225201 -0400 @@ -22,7 +22,12 @@ #include #include +#include #include +#include +#include +#include +#include #include "common.h" #include "common-board-devices.h" @@ -32,6 +37,7 @@ #include "omap-secure.h" #include "soc.h" #include "hsmmc.h" +#include "remoteproc.h" struct pdata_init { const char *compatible; @@ -41,6 +47,25 @@ static struct of_dev_auxdata omap_auxdata_lookup[]; static struct twl4030_gpio_platform_data twl_gpio_auxdata; +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) +static struct gfx_sgx_platform_data sgx_pdata = { + .reset_name = "gfx", + .assert_reset = omap_device_assert_hardreset, + .deassert_reset = omap_device_deassert_hardreset, +}; +#endif + +#if IS_ENABLED(CONFIG_OMAP_IOMMU) +int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, + u8 *pwrst); +#else +static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, + bool request, u8 *pwrst) +{ + return 0; +} +#endif + #ifdef CONFIG_MACH_NOKIA_N8X0 static void __init omap2420_n8x0_legacy_init(void) { @@ -85,6 +110,13 @@ .reset_name = "mmu", .assert_reset = omap_device_assert_hardreset, .deassert_reset = omap_device_deassert_hardreset, + .device_enable = omap_device_enable, + .device_idle = omap_device_idle, +}; + +static struct iommu_platform_data omap3_iommu_isp_pdata = { + .device_enable = omap_device_enable, + .device_idle = omap_device_idle, }; static int omap3_sbc_t3730_twl_callback(struct device *dev, @@ -382,11 +414,29 @@ } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) +static struct omap_rproc_timer_ops omap_rproc_dmtimer_ops = { + .request_timer = omap_rproc_request_timer, + .release_timer = omap_rproc_release_timer, + .start_timer = omap_rproc_start_timer, + .stop_timer = omap_rproc_stop_timer, + .get_timer_irq = omap_rproc_get_timer_irq, + .ack_timer_irq = omap_rproc_ack_timer_irq, +}; + +static struct omap_rproc_pdata omap4_ipu_dsp_pdata = { + .device_enable = omap_rproc_device_enable, + .device_shutdown = omap_rproc_device_shutdown, + .timer_ops = &omap_rproc_dmtimer_ops, +}; + static struct iommu_platform_data omap4_iommu_pdata = { .reset_name = "mmu_cache", .assert_reset = omap_device_assert_hardreset, .deassert_reset = omap_device_deassert_hardreset, + .device_enable = omap_device_enable, + .device_idle = omap_device_idle, }; #endif @@ -396,6 +446,12 @@ .assert_reset = omap_device_assert_hardreset, .deassert_reset = omap_device_deassert_hardreset, }; + +static struct pruss_platform_data pruss_pdata = { + .reset_name = "pruss", + .assert_reset = omap_device_assert_hardreset, + .deassert_reset = omap_device_deassert_hardreset, +}; #endif #ifdef CONFIG_SOC_OMAP5 @@ -404,6 +460,22 @@ } #endif +#ifdef CONFIG_SOC_DRA7XX +static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = { + .reset_name = "mmu_cache", + .assert_reset = omap_device_assert_hardreset, + .deassert_reset = omap_device_deassert_hardreset, + .device_enable = omap_device_enable, + .device_idle = omap_device_idle, + .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, +}; + +static struct iommu_platform_data dra7_dsp_mmu_edma_pdata = { + .device_enable = omap_device_enable, + .device_idle = omap_device_idle, +}; +#endif + static struct pcs_pdata pcs_pdata; void omap_pcs_legacy_init(int irq, void (*rearm)(void)) @@ -427,6 +499,24 @@ dev->platform_data = &twl_gpio_auxdata; } +/* Dual mode timer PWM callbacks platdata */ +#if IS_ENABLED(CONFIG_OMAP_DM_TIMER) +struct pwm_omap_dmtimer_pdata pwm_dmtimer_pdata = { + .request_by_node = omap_dm_timer_request_by_node, + .free = omap_dm_timer_free, + .enable = omap_dm_timer_enable, + .disable = omap_dm_timer_disable, + .get_fclk = omap_dm_timer_get_fclk, + .start = omap_dm_timer_start, + .stop = omap_dm_timer_stop, + .set_load = omap_dm_timer_set_load, + .set_match = omap_dm_timer_set_match, + .set_pwm = omap_dm_timer_set_pwm, + .set_prescaler = omap_dm_timer_set_prescaler, + .write_counter = omap_dm_timer_write_counter, +}; +#endif + /* * Few boards still need auxdata populated before we populate * the dev entries in of_platform_populate(). @@ -455,6 +545,8 @@ OF_DEV_AUXDATA("ti,omap3-padconf", 0x48002a00, "48002a00.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu", &omap3_iommu_pdata), + OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu", + &omap3_iommu_isp_pdata), /* Only on am3517 */ OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL), OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0", @@ -463,22 +555,57 @@ #ifdef CONFIG_SOC_AM33XX OF_DEV_AUXDATA("ti,am3352-wkup-m3", 0x44d00000, "44d00000.wkup_m3", &wkup_m3_data), + OF_DEV_AUXDATA("ti,am3352-pruss", 0x4a300000, "4a300000.pruss", + &pruss_pdata), + OF_DEV_AUXDATA("ti,am3352-sgx530", 0x56000000, "56000000.sgx", + &sgx_pdata), #endif #ifdef CONFIG_ARCH_OMAP4 OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a100040, "4a100040.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap4-padconf", 0x4a31e040, "4a31e040.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap4-dsp", 0, "dsp", &omap4_ipu_dsp_pdata), + OF_DEV_AUXDATA("ti,omap4-ipu", 0x55020000, "ipu", &omap4_ipu_dsp_pdata), #endif #ifdef CONFIG_SOC_OMAP5 OF_DEV_AUXDATA("ti,omap5-padconf", 0x4a002840, "4a002840.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,omap5-padconf", 0x4ae0c840, "4ae0c840.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,omap5-dsp", 0, "dsp", &omap4_ipu_dsp_pdata), + OF_DEV_AUXDATA("ti,omap5-ipu", 0x55020000, "ipu", &omap4_ipu_dsp_pdata), #endif #ifdef CONFIG_SOC_DRA7XX OF_DEV_AUXDATA("ti,dra7-padconf", 0x4a003400, "4a003400.pinmux", &pcs_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d02000, "40d02000.mmu", + &dra7_dsp_mmu_edma_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41502000, "41502000.mmu", + &dra7_dsp_mmu_edma_pdata), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu", + &omap4_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu", + &dra7_ipu1_dsp_iommu_pdata), + OF_DEV_AUXDATA("ti,dra7-ipu", 0x55020000, "55020000.ipu", + &omap4_ipu_dsp_pdata), + OF_DEV_AUXDATA("ti,dra7-ipu", 0x58820000, "58820000.ipu", + &omap4_ipu_dsp_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp", 0x40800000, "40800000.dsp", + &omap4_ipu_dsp_pdata), + OF_DEV_AUXDATA("ti,dra7-dsp", 0x41000000, "41000000.dsp", + &omap4_ipu_dsp_pdata), #endif #ifdef CONFIG_SOC_AM43XX OF_DEV_AUXDATA("ti,am437-padconf", 0x44e10800, "44e10800.pinmux", &pcs_pdata), OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3", &wkup_m3_data), + OF_DEV_AUXDATA("ti,am4372-pruss", 0x54400000, "54400000.pruss", + &pruss_pdata), + OF_DEV_AUXDATA("ti,am4376-sgx530", 0x56000000, "56000000.sgx", + &sgx_pdata), +#endif +#if IS_ENABLED(CONFIG_OMAP_DM_TIMER) + OF_DEV_AUXDATA("ti,omap-dmtimer-pwm", 0, NULL, &pwm_dmtimer_pdata), #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", diff -Naur --no-dereference a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c --- a/arch/arm/mach-omap2/pm33xx-core.c 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/mach-omap2/pm33xx-core.c 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,284 @@ +/* + * AM33XX Arch Power Management Routines + * + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Dave Gerlach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "control.h" +#include "pm.h" +#include "cm33xx.h" +#include "prm33xx.h" +#include "common.h" +#include "clockdomain.h" +#include "powerdomain.h" +#include "soc.h" +#include "sram.h" +#include "omap_hwmod.h" +#include "iomap.h" + +static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; +static struct clockdomain *gfx_l4ls_clkdm; +static void __iomem *scu_base; +static struct omap_hwmod *rtc_oh; + +static struct pinctrl_dev *pmx_dev; + +static int __init am43xx_map_scu(void) +{ + scu_base = ioremap(scu_a9_get_base(), SZ_256); + + if (!scu_base) + return -ENOMEM; + + return 0; +} + +static int am43xx_check_off_mode_enable(void) +{ + return enable_off_mode; +} + +static int amx3_common_init(void) +{ + gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); + per_pwrdm = pwrdm_lookup("per_pwrdm"); + mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); + + if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) + return -ENODEV; + + (void)clkdm_for_each(omap_pm_clkdms_setup, NULL); + + /* CEFUSE domain can be turned off post bootup */ + cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); + if (cefuse_pwrdm) + omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); + else + pr_err("PM: Failed to get cefuse_pwrdm\n"); + + return 0; +} + +static int am33xx_suspend_init(void) +{ + int ret; + + gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); + + if (!gfx_l4ls_clkdm) { + pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); + return -ENODEV; + } + + ret = amx3_common_init(); + + return ret; +} + +static int am43xx_suspend_init(void) +{ + int ret = 0; + + pmx_dev = get_pinctrl_dev_from_devname("44e10800.pinmux"); + + ret = am43xx_map_scu(); + if (ret) { + pr_err("PM: Could not ioremap SCU\n"); + return ret; + } + + ret = amx3_common_init(); + + return ret; +} + +static void amx3_pre_suspend_common(void) +{ + omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); +} + +static void amx3_post_suspend_common(void) +{ + int status; + /* + * Because gfx_pwrdm is the only one under MPU control, + * comment on transition status + */ + status = pwrdm_read_pwrst(gfx_pwrdm); + if (status != PWRDM_POWER_OFF) + pr_err("PM: GFX domain did not transition: %x\n", status); +} + +static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long), + unsigned long args) +{ + int ret = 0; + + amx3_pre_suspend_common(); + ret = cpu_suspend(args, fn); + amx3_post_suspend_common(); + + /* + * BUG: GFX_L4LS clock domain needs to be woken up to + * ensure thet L4LS clock domain does not get stuck in + * transition. If that happens L3 module does not get + * disabled, thereby leading to PER power domain + * transition failing + */ + + clkdm_wakeup(gfx_l4ls_clkdm); + clkdm_sleep(gfx_l4ls_clkdm); + + return ret; +} + +static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), + unsigned long args) +{ + int ret = 0; + + amx3_pre_suspend_common(); + scu_power_mode(scu_base, SCU_PM_POWEROFF); + ret = cpu_suspend(args, fn); + scu_power_mode(scu_base, SCU_PM_NORMAL); + + if (!am43xx_check_off_mode_enable()) + amx3_post_suspend_common(); + + return ret; +} + +static void common_save_context(void) +{ + omap2_gpio_prepare_for_idle(1); + pinmux_save_context(pmx_dev, "am33xx_pmx_per"); + clks_save_context(); + pwrdms_save_context(); + omap_hwmods_save_context(); + clkdm_save_context(); +} + +static void common_restore_context(void) +{ + clks_restore_context(); + clkdm_restore_context(); + pwrdms_restore_context(); + omap_hwmods_restore_context(); + pinmux_restore_context(pmx_dev, "am33xx_pmx_per"); + pwrdms_lost_power(); + omap2_gpio_resume_after_idle(); +} + +static void am33xx_save_context(void) +{ + common_save_context(); + omap_intc_save_context(); + am33xx_control_save_context(); +} + +static void am33xx_restore_context(void) +{ + common_restore_context(); + am33xx_control_restore_context(); + omap_intc_restore_context(); +} + +static void am43xx_save_context(void) +{ + common_save_context(); + am43xx_control_save_context(); +} + +static void am43xx_restore_context(void) +{ + common_restore_context(); + am43xx_control_restore_context(); + /* + * HACK: restore dpll_per_clkdcoldo register contents, to avoid + * breaking suspend-resume + */ + writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14)); +} + +static void am43xx_prepare_rtc_suspend(void) +{ + omap_hwmod_enable(rtc_oh); +} + +static void am43xx_prepare_rtc_resume(void) +{ + omap_hwmod_idle(rtc_oh); +} + +void __iomem *am43xx_get_rtc_base_addr(void) +{ + rtc_oh = omap_hwmod_lookup("rtc"); + + return omap_hwmod_get_mpu_rt_va(rtc_oh); +} + +static struct am33xx_pm_platform_data am33xx_pdata = { + .init = am33xx_suspend_init, + .soc_suspend = am33xx_suspend, + .pm_sram_addr = &am33xx_pm_sram, + .save_context = am33xx_save_context, + .restore_context = am33xx_restore_context, + .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, + .prepare_rtc_resume = am43xx_prepare_rtc_resume, + .check_off_mode_enable = am43xx_check_off_mode_enable, + .get_rtc_base_addr = am43xx_get_rtc_base_addr, +}; + +static struct am33xx_pm_platform_data am43xx_pdata = { + .init = am43xx_suspend_init, + .soc_suspend = am43xx_suspend, + .pm_sram_addr = &am43xx_pm_sram, + .save_context = am43xx_save_context, + .restore_context = am43xx_restore_context, + .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, + .prepare_rtc_resume = am43xx_prepare_rtc_resume, + .check_off_mode_enable = am43xx_check_off_mode_enable, + .get_rtc_base_addr = am43xx_get_rtc_base_addr, +}; + +struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) +{ + if (soc_is_am33xx()) + return &am33xx_pdata; + else if (soc_is_am437x()) + return &am43xx_pdata; + else + return NULL; +} + +void __init amx3_common_pm_init(void) +{ + struct platform_device_info devinfo = { }; + struct am33xx_pm_platform_data *pdata; + + pdata = am33xx_pm_get_pdata(); + devinfo.name = "pm33xx"; + devinfo.data = pdata; + devinfo.size_data = sizeof(*pdata); + platform_device_register_full(&devinfo); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c --- a/arch/arm/mach-omap2/pm.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/pm.c 2016-05-11 13:31:53.193225201 -0400 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -108,7 +109,7 @@ } } -int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) +int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) { /* XXX The usecount test is racy */ if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && diff -Naur --no-dereference a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h --- a/arch/arm/mach-omap2/pm.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/pm.h 2016-05-11 13:31:53.193225201 -0400 @@ -81,6 +81,11 @@ /* ... and its pointer from SRAM after copy */ extern void (*omap3_do_wfi_sram)(void); +struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void); + +extern struct am33xx_pm_sram_addr am33xx_pm_sram; +extern struct am33xx_pm_sram_addr am43xx_pm_sram; + /* save_secure_ram_context function pointer and size, for copy to SRAM */ extern int save_secure_ram_context(u32 *addr); extern unsigned int save_secure_ram_context_sz; diff -Naur --no-dereference a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c --- a/arch/arm/mach-omap2/powerdomain.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/powerdomain.c 2016-05-11 13:31:53.193225201 -0400 @@ -1167,42 +1167,61 @@ } /** - * pwrdm_can_ever_lose_context - can this powerdomain ever lose context? - * @pwrdm: struct powerdomain * + * pwrdm_save_context - save powerdomain registers * - * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain - * can lose either memory or logic context or if @pwrdm is invalid, or - * returns 0 otherwise. This function is not concerned with how the - * powerdomain registers are programmed (i.e., to go off or not); it's - * concerned with whether it's ever possible for this powerdomain to - * go off while some other part of the chip is active. This function - * assumes that every powerdomain can go to either ON or INACTIVE. + * Register state is going to be lost due to a suspend or hibernate + * event. Save the powerdomain registers. */ -bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm) +static int pwrdm_save_context(struct powerdomain *pwrdm, void *unused) { - int i; + if (arch_pwrdm && arch_pwrdm->pwrdm_save_context) + arch_pwrdm->pwrdm_save_context(pwrdm); + return 0; +} - if (!pwrdm) { - pr_debug("powerdomain: %s: invalid powerdomain pointer\n", - __func__); - return 1; - } +/** + * pwrdm_save_context - restore powerdomain registers + * + * Restore powerdomain control registers after a suspend or resume + * event. + */ +static int pwrdm_restore_context(struct powerdomain *pwrdm, void *unused) +{ + if (arch_pwrdm && arch_pwrdm->pwrdm_restore_context) + arch_pwrdm->pwrdm_restore_context(pwrdm); + return 0; +} - if (pwrdm->pwrsts & PWRSTS_OFF) - return 1; +static int pwrdm_lost_power(struct powerdomain *pwrdm, void *unused) +{ + int state; - if (pwrdm->pwrsts & PWRSTS_RET) { - if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF) - return 1; - - for (i = 0; i < pwrdm->banks; i++) - if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF) - return 1; + /* + * Power has been lost across all powerdomains, increment the + * counter. + */ + + state = pwrdm_read_pwrst(pwrdm); + if (state != PWRDM_POWER_OFF) { + pwrdm->state_counter[state]++; + pwrdm->state_counter[PWRDM_POWER_OFF]++; } - - for (i = 0; i < pwrdm->banks; i++) - if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF) - return 1; + pwrdm->state = state; return 0; } + +void pwrdms_save_context(void) +{ + pwrdm_for_each(pwrdm_save_context, NULL); +} + +void pwrdms_restore_context(void) +{ + pwrdm_for_each(pwrdm_restore_context, NULL); +} + +void pwrdms_lost_power(void) +{ + pwrdm_for_each(pwrdm_lost_power, NULL); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h --- a/arch/arm/mach-omap2/powerdomain.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/powerdomain.h 2016-05-11 13:31:53.193225201 -0400 @@ -144,6 +144,7 @@ s64 timer; s64 state_timer[PWRDM_MAX_PWRSTS]; #endif + u32 context; }; /** @@ -198,6 +199,8 @@ int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); int (*pwrdm_has_voltdm)(void); + void (*pwrdm_save_context)(struct powerdomain *pwrdm); + void (*pwrdm_restore_context)(struct powerdomain *pwrdm); }; int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs); @@ -244,7 +247,6 @@ int pwrdm_pre_transition(struct powerdomain *pwrdm); int pwrdm_post_transition(struct powerdomain *pwrdm); int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); -bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state); @@ -273,4 +275,8 @@ extern void pwrdm_lock(struct powerdomain *pwrdm); extern void pwrdm_unlock(struct powerdomain *pwrdm); +extern void pwrdms_save_context(void); +extern void pwrdms_restore_context(void); + +extern void pwrdms_lost_power(void); #endif diff -Naur --no-dereference a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c --- a/arch/arm/mach-omap2/powerdomains7xx_data.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c 2016-05-11 13:31:53.193225201 -0400 @@ -35,7 +35,7 @@ .name = "iva_pwrdm", .prcm_offs = DRA7XX_PRM_IVA_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 4, .pwrsts_mem_ret = { @@ -45,10 +45,10 @@ [3] = PWRSTS_OFF_RET, /* tcm2_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* hwa_mem */ - [1] = PWRSTS_OFF_RET, /* sl2_mem */ - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + [0] = PWRSTS_ON, /* hwa_mem */ + [1] = PWRSTS_ON, /* sl2_mem */ + [2] = PWRSTS_ON, /* tcm1_mem */ + [3] = PWRSTS_ON, /* tcm2_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -75,7 +75,7 @@ .name = "ipu_pwrdm", .prcm_offs = DRA7XX_PRM_IPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 2, .pwrsts_mem_ret = { @@ -83,8 +83,8 @@ [1] = PWRSTS_OFF_RET, /* periphmem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* aessmem */ - [1] = PWRSTS_OFF_RET, /* periphmem */ + [0] = PWRSTS_ON, /* aessmem */ + [1] = PWRSTS_ON, /* periphmem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -94,14 +94,14 @@ .name = "dss_pwrdm", .prcm_offs = DRA7XX_PRM_DSS_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* dss_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dss_mem */ + [0] = PWRSTS_ON, /* dss_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -112,15 +112,15 @@ .prcm_offs = DRA7XX_PRM_L4PER_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* nonretained_bank */ [1] = PWRSTS_OFF_RET, /* retained_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* nonretained_bank */ - [1] = PWRSTS_OFF_RET, /* retained_bank */ + [0] = PWRSTS_ON, /* nonretained_bank */ + [1] = PWRSTS_ON, /* retained_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -136,7 +136,7 @@ [0] = PWRSTS_OFF_RET, /* gpu_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gpu_mem */ + [0] = PWRSTS_ON, /* gpu_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -160,7 +160,7 @@ .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_INA_ON, + .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { @@ -171,11 +171,11 @@ [4] = PWRSTS_OFF_RET, /* ipu_unicache */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRSTS_OFF_RET, /* core_other_bank */ - [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ - [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + [0] = PWRSTS_ON, /* core_nret_bank */ + [1] = PWRSTS_ON, /* core_ocmram */ + [2] = PWRSTS_ON, /* core_other_bank */ + [3] = PWRSTS_ON, /* ipu_l2ram */ + [4] = PWRSTS_ON, /* ipu_unicache */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -225,14 +225,14 @@ .name = "vpe_pwrdm", .prcm_offs = DRA7XX_PRM_VPE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_OFF_ON, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* vpe_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vpe_bank */ + [0] = PWRSTS_ON, /* vpe_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -250,8 +250,8 @@ [1] = PWRSTS_RET, /* mpu_ram */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* mpu_l2 */ - [1] = PWRSTS_OFF_RET, /* mpu_ram */ + [0] = PWRSTS_ON, /* mpu_l2 */ + [1] = PWRSTS_ON, /* mpu_ram */ }, }; @@ -261,7 +261,7 @@ .prcm_offs = DRA7XX_PRM_L3INIT_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* gmac_bank */ @@ -269,9 +269,9 @@ [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gmac_bank */ - [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ - [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + [0] = PWRSTS_ON, /* gmac_bank */ + [1] = PWRSTS_ON, /* l3init_bank1 */ + [2] = PWRSTS_ON, /* l3init_bank2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -287,7 +287,7 @@ [0] = PWRSTS_OFF_RET, /* eve3_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve3_bank */ + [0] = PWRSTS_ON, /* eve3_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -303,7 +303,7 @@ [0] = PWRSTS_OFF_RET, /* emu_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* emu_bank */ + [0] = PWRSTS_ON, /* emu_bank */ }, }; @@ -320,9 +320,9 @@ [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp2_edma */ - [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + [0] = PWRSTS_ON, /* dsp2_edma */ + [1] = PWRSTS_ON, /* dsp2_l1 */ + [2] = PWRSTS_ON, /* dsp2_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -340,9 +340,9 @@ [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp1_edma */ - [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + [0] = PWRSTS_ON, /* dsp1_edma */ + [1] = PWRSTS_ON, /* dsp1_l1 */ + [2] = PWRSTS_ON, /* dsp1_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -358,7 +358,7 @@ [0] = PWRSTS_OFF_RET, /* vip_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vip_bank */ + [0] = PWRSTS_ON, /* vip_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -374,7 +374,7 @@ [0] = PWRSTS_OFF_RET, /* eve4_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve4_bank */ + [0] = PWRSTS_ON, /* eve4_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -390,7 +390,7 @@ [0] = PWRSTS_OFF_RET, /* eve2_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve2_bank */ + [0] = PWRSTS_ON, /* eve2_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -406,7 +406,7 @@ [0] = PWRSTS_OFF_RET, /* eve1_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve1_bank */ + [0] = PWRSTS_ON, /* eve1_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; diff -Naur --no-dereference a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h --- a/arch/arm/mach-omap2/prcm43xx.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/prcm43xx.h 2016-05-11 13:31:53.193225201 -0400 @@ -91,6 +91,7 @@ #define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 #define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 #define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 +#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0 #define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 #define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 #define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 @@ -132,6 +133,7 @@ #define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 #define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 #define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 +#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030 #define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 #define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 #define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 diff -Naur --no-dereference a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c --- a/arch/arm/mach-omap2/prm33xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/prm33xx.c 2016-05-11 13:31:53.193225201 -0400 @@ -353,6 +353,35 @@ AM33XX_PRM_RSTCTRL_OFFSET); } +static void am33xx_pwrdm_save_context(struct powerdomain *pwrdm) +{ + pwrdm->context = am33xx_prm_read_reg(pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs); + /* + * Do not save LOWPOWERSTATECHANGE, writing a 1 indicates a request, + * reading back a 1 indicates a request in progress. + */ + pwrdm->context &= ~AM33XX_LOWPOWERSTATECHANGE_MASK; +} + +static void am33xx_pwrdm_restore_context(struct powerdomain *pwrdm) +{ + int st, ctrl; + + st = am33xx_prm_read_reg(pwrdm->prcm_offs, + pwrdm->pwrstst_offs); + + am33xx_prm_write_reg(pwrdm->context, pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs); + + /* Make sure we only wait for a transition if there is one */ + st &= OMAP_POWERSTATEST_MASK; + ctrl = OMAP_POWERSTATEST_MASK & pwrdm->context; + + if (st != ctrl) + am33xx_pwrdm_wait_transition(pwrdm); +} + struct pwrdm_ops am33xx_pwrdm_operations = { .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, @@ -369,6 +398,8 @@ .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, .pwrdm_has_voltdm = am33xx_check_vcvp, + .pwrdm_save_context = am33xx_pwrdm_save_context, + .pwrdm_restore_context = am33xx_pwrdm_restore_context, }; static struct prm_ll_data am33xx_prm_ll_data = { diff -Naur --no-dereference a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c --- a/arch/arm/mach-omap2/prm44xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/prm44xx.c 2016-05-11 13:31:53.193225201 -0400 @@ -669,6 +669,54 @@ return 0; } +/** + * omap4_pwrdm_save_context - Saves the powerdomain state + * @pwrdm: pointer to individual powerdomain + * + * The function saves the powerdomain state control information. + * This is needed in rtc+ddr modes where we lose powerdomain context. + */ +static void omap4_pwrdm_save_context(struct powerdomain *pwrdm) +{ + pwrdm->context = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, + pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs); + + /* + * Do not save LOWPOWERSTATECHANGE, writing a 1 indicates a request, + * reading back a 1 indicates a request in progress. + */ + pwrdm->context &= ~OMAP4430_LOWPOWERSTATECHANGE_MASK; +} + +/** + * omap4_pwrdm_restore_context - Restores the powerdomain state + * @pwrdm: pointer to individual powerdomain + * + * The function restores the powerdomain state control information. + * This is needed in rtc+ddr modes where we lose powerdomain context. + */ +static void omap4_pwrdm_restore_context(struct powerdomain *pwrdm) +{ + int st, ctrl; + + st = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, + pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs); + + omap4_prminst_write_inst_reg(pwrdm->context, + pwrdm->prcm_partition, + pwrdm->prcm_offs, + pwrdm->pwrstctrl_offs); + + /* Make sure we only wait for a transition if there is one */ + st &= OMAP_POWERSTATEST_MASK; + ctrl = OMAP_POWERSTATEST_MASK & pwrdm->context; + + if (st != ctrl) + omap4_pwrdm_wait_transition(pwrdm); +} + struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, @@ -687,6 +735,8 @@ .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, .pwrdm_wait_transition = omap4_pwrdm_wait_transition, .pwrdm_has_voltdm = omap4_check_vcvp, + .pwrdm_save_context = omap4_pwrdm_save_context, + .pwrdm_restore_context = omap4_pwrdm_restore_context, }; static int omap44xx_prm_late_init(void); diff -Naur --no-dereference a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h --- a/arch/arm/mach-omap2/prm7xx.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/prm7xx.h 2016-05-11 13:31:53.193225201 -0400 @@ -360,6 +360,7 @@ /* PRM.L3INIT_PRM register offsets */ #define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 #define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 #define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 #define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c #define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 diff -Naur --no-dereference a/arch/arm/mach-omap2/remoteproc.c b/arch/arm/mach-omap2/remoteproc.c --- a/arch/arm/mach-omap2/remoteproc.c 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/mach-omap2/remoteproc.c 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,236 @@ +/* + * Remote processor machine-specific module for OMAP4+ SoCs + * + * Copyright (C) 2011-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include + +#include + +#include "omap_device.h" +#include "remoteproc.h" + +/** + * omap_rproc_device_enable - enable the remoteproc device + * @pdev: the rproc platform device + * + * This function performs the necessary low-level functions to enable + * a remoteproc device to start executing. This typically includes + * releasing the reset lines, and enabling the clocks for the device. + * We do not usually expect this function to fail. + * + * Return: 0 on success, or the return code from the failed function + */ +int omap_rproc_device_enable(struct platform_device *pdev) +{ + int ret = -EINVAL; + + /* + * This reset management follows a device name check to differentiate + * DSP and IPU processor subsystems. This check is weak and is ok for + * now because of the dependencies against the pdata-quirks, where + * the devices are given specific device names that satisfy the + * criteria for the check. It can easily be replaced with a stronger + * check like device node compatibility check, if needed. + */ + if (strstr(dev_name(&pdev->dev), "dsp")) { + ret = omap_device_deassert_hardreset(pdev, "dsp"); + if (ret) + goto out; + } else if (strstr(dev_name(&pdev->dev), "ipu")) { + ret = omap_device_deassert_hardreset(pdev, "cpu0"); + if (ret) + goto out; + + ret = omap_device_deassert_hardreset(pdev, "cpu1"); + if (ret) + goto out; + } else { + pr_err("unsupported remoteproc\n"); + goto out; + } + + ret = omap_device_enable(pdev); + +out: + if (ret) + pr_err("failed for proc %s\n", dev_name(&pdev->dev)); + return ret; +} + +/** + * omap_rproc_device_shutdown - shutdown the remoteproc device + * @pdev: the rproc platform device + * + * This function performs the necessary low-level functions to shutdown + * a remoteproc device. This typically includes disabling the clocks + * for the device and asserting the associated reset lines. We do not + * usually expect this function to fail. + * + * Return: 0 on success, or the return code from the failed function + */ +int omap_rproc_device_shutdown(struct platform_device *pdev) +{ + int ret = -EINVAL; + + ret = omap_device_idle(pdev); + if (ret) + goto out; + + /* + * This reset management follows a device name check to differentiate + * DSP and IPU processor subsystems. This check is weak and is ok for + * now because of the dependencies against the pdata-quirks, where + * the devices are given specific device names that satisfy the + * criteria for the check. It can easily be replaced with a stronger + * check like device node compatibility check, if needed. + */ + if (strstr(dev_name(&pdev->dev), "dsp")) { + ret = omap_device_assert_hardreset(pdev, "dsp"); + } else if (strstr(dev_name(&pdev->dev), "ipu")) { + ret = omap_device_assert_hardreset(pdev, "cpu1"); + if (ret) + goto out; + + ret = omap_device_assert_hardreset(pdev, "cpu0"); + if (ret) + goto out; + } else { + pr_err("unsupported remoteproc\n"); + } + +out: + if (ret) + pr_err("failed for proc %s\n", dev_name(&pdev->dev)); + return ret; +} + +/** + * omap_rproc_request_timer - request a timer for a remoteproc + * @np - device node pointer to the desired timer + * + * This function is used primarily to request a timer associated with + * a remoteproc. The remoteproc driver core needs to store the returned + * handle to invoke other timer specific ops (like starting a timer either + * during device initialization or during a resume operation, or for + * stopping/freeing a timer). + * + * Returns an OMAP timer handle on success, otherwise an equivalent ERR_PTR + */ +struct omap_dm_timer *omap_rproc_request_timer(struct device_node *np) +{ + struct omap_dm_timer *timer; + int ret = 0; + + timer = omap_dm_timer_request_by_node(np); + if (!timer) { + pr_err("request for timer node %p failed\n", np); + return ERR_PTR(-EBUSY); + } + + ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); + if (ret) { + pr_err("error setting OMAP_TIMER_SRC_SYS_CLK as source for timer node %p\n", + np); + omap_dm_timer_free(timer); + return ERR_PTR(ret); + } + + /* clean counter, remoteproc code will set the value */ + omap_dm_timer_set_load(timer, 0, 0); + + return timer; +} + +/** + * omap_rproc_start_timer - start a timer for a remoteproc + * @timer - handle to a OMAP timer + * + * This function is used to start a timer associated with a remoteproc, + * obtained using the request_timer ops. The function needs to be invoked + * by the remoteproc driver core to start the timer (during device + * initialization) or to just resume the timer. + * + * Returns 0 on success, otherwise a failure as returned by DMTimer API + */ +int omap_rproc_start_timer(struct omap_dm_timer *timer) +{ + return omap_dm_timer_start(timer); +} + +/** + * omap_rproc_stop_timer - stop a timer for a remoteproc + * @timer - handle to a struct omap_dm_timer + * + * This function is used to disable a timer associated with a remoteproc, + * and needs to be called either during a device shutdown or suspend + * operation. The separate function allows the remoteproc driver core to + * just stop a timer without having to release the timer during a suspend + * operation. + * + * Returns 0 on success, otherwise a failure as returned by DMTimer API + */ +int omap_rproc_stop_timer(struct omap_dm_timer *timer) +{ + return omap_dm_timer_stop(timer); +} + +/** + * omap_rproc_release_timer - release a timer for a remoteproc + * @timer - handle to a struct omap_dm_timer + * + * This function is used primarily to release a timer associated with + * a remoteproc. The dmtimer will be available for other clients to use + * once released. + * + * Returns 0 on success, otherwise a failure as returned by DMTimer API + */ +int omap_rproc_release_timer(struct omap_dm_timer *timer) +{ + return omap_dm_timer_free(timer); +} + +/** + * omap_rproc_get_timer_irq - get the irq for a timer + * @timer - handle to a OMAP timer + * + * This function is used to get the irq associated with a timer, obtained + * using the request_timer ops. The function is called by the OMAP remoteproc + * driver to register a interrupt handler to handle watchdog events on the + * remote processor. + * + * Returns the irq id on success, otherwise a failure as returned by DMTimer API + */ +int omap_rproc_get_timer_irq(struct omap_dm_timer *timer) +{ + return omap_dm_timer_get_irq(timer); +} + +/** + * omap_rproc_ack_timer_irq - acknowledge a timer irq + * @timer - handle to a OMAP timer + * + * This function is used to clear the irq associated with a timer, obtained + * using the request_timer ops. The function is called by the OMAP remoteproc + * driver upon a watchdog event on the remote processor to clear the interrupt + * status of the watchdog timer. + * + * Returns the irq id on success, otherwise a failure as returned by DMTimer API + */ +void omap_rproc_ack_timer_irq(struct omap_dm_timer *timer) +{ + omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); +} diff -Naur --no-dereference a/arch/arm/mach-omap2/remoteproc.h b/arch/arm/mach-omap2/remoteproc.h --- a/arch/arm/mach-omap2/remoteproc.h 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/mach-omap2/remoteproc.h 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,74 @@ +/* + * Remote processor machine-specific quirks for OMAP4+ SoCs + * + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Suman Anna + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_REMOTEPROC_H +#define __ARCH_ARM_MACH_OMAP2_REMOTEPROC_H + +#include "linux/platform_device.h" + +struct omap_dm_timer; + +#if IS_ENABLED(CONFIG_OMAP_REMOTEPROC) +int omap_rproc_device_enable(struct platform_device *pdev); +int omap_rproc_device_shutdown(struct platform_device *pdev); +struct omap_dm_timer *omap_rproc_request_timer(struct device_node *np); +int omap_rproc_release_timer(struct omap_dm_timer *timer); +int omap_rproc_start_timer(struct omap_dm_timer *timer); +int omap_rproc_stop_timer(struct omap_dm_timer *timer); +int omap_rproc_get_timer_irq(struct omap_dm_timer *timer); +void omap_rproc_ack_timer_irq(struct omap_dm_timer *timer); +#else +static inline int omap_rproc_device_enable(struct platform_device *pdev) +{ + return 0; +} + +static inline int omap_rproc_device_shutdown(struct platform_device *pdev) +{ + return 0; +} + +static inline +struct omap_dm_timer *omap_rproc_request_timer(struct device_node *np) +{ + return ERR_PTR(-ENODEV); +} + +static inline int omap_rproc_release_timer(struct omap_dm_timer *timer) +{ + return -ENODEV; +} + +static inline int omap_rproc_start_timer(struct omap_dm_timer *timer) +{ + return -ENODEV; +} + +static inline int omap_rproc_stop_timer(struct omap_dm_timer *timer) +{ + return -ENODEV; +} + +static inline int omap_rproc_get_timer_irq(struct omap_dm_timer *timer) +{ + return -1; +} + +static inline void omap_rproc_ack_timer_irq(struct omap_dm_timer *timer) { } +#endif + +#endif diff -Naur --no-dereference a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S --- a/arch/arm/mach-omap2/sleep33xx.S 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/mach-omap2/sleep33xx.S 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,227 @@ +/* + * Low level suspend code for AM33XX SoCs + * + * Copyright (C) 2012-2015 Texas Instruments Incorporated - http://www.ti.com/ + * Vaibhav Bedia, Dave Gerlach + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "iomap.h" +#include "cm33xx.h" + +#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 +#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002 + + .text + .align 3 + +ENTRY(am33xx_do_wfi) + stmfd sp!, {r4 - r11, lr} @ save registers on stack + + /* + * Flush all data from the L1 and L2 data cache before disabling + * SCTLR.C bit. + */ + ldr r1, kernel_flush + blx r1 + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + /* + * Invalidate L1 and L2 data cache. + */ + ldr r1, kernel_flush + blx r1 + + ldr r1, ti_emif_save_context + blx r1 + + ldr r1, ti_emif_enter_sr + blx r1 + + /* Disable EMIF */ + ldr r1, virt_emif_clkctrl + ldr r2, [r1] + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE + str r2, [r1] + + ldr r1, virt_emif_clkctrl +wait_emif_disable: + ldr r2, [r1] + ldr r3, module_disabled_val + cmp r2, r3 + bne wait_emif_disable + + /* + * For the MPU WFI to be registered as an interrupt + * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set + * to DISABLED + */ + ldr r1, virt_mpu_clkctrl + ldr r2, [r1] + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE + str r2, [r1] + + /* + * Execute an ISB instruction to ensure that all of the + * CP15 register changes have been committed. + */ + isb + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * have completed. + */ + dsb + dmb + + /* + * Execute a WFI instruction and wait until the + * STANDBYWFI output is asserted to indicate that the + * CPU is in idle and low power state. CPU can specualatively + * prefetch the instructions so add NOPs after WFI. Thirteen + * NOPs as per Cortex-A8 pipeline. + */ + wfi + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* We come here in case of an abort due to a late interrupt */ + + /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */ + ldr r1, virt_mpu_clkctrl + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r2, [r1] + + /* Re-enable EMIF */ + ldr r1, virt_emif_clkctrl + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r2, [r1] +wait_emif_enable: + ldr r3, [r1] + cmp r2, r3 + bne wait_emif_enable + + ldr r1, ti_emif_abort_sr + blx r1 + + /* + * Set SCTLR.C bit to allow data cache allocation + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1 << 2) @ Enable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + /* Let the suspend code know about the abort */ + mov r0, #1 + ldmfd sp!, {r4 - r11, pc} @ restore regs and return +ENDPROC(am33xx_do_wfi) + + .align +ENTRY(am33xx_resume_offset) + .word . - am33xx_do_wfi + +ENTRY(am33xx_resume_from_deep_sleep) + /* Re-enable EMIF */ + ldr r0, phys_emif_clkctrl + mov r1, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r1, [r0] +wait_emif_enable1: + ldr r2, [r0] + cmp r1, r2 + bne wait_emif_enable1 + +ARM( adr sp, temp_stack ) +THUMB( adr r1, temp_stack ) +THUMB( mov sp, r1 ) + + ldr r1, ti_emif_restore_context + blx r1 + + ldr r1, ti_emif_exit_sr + blx r1 + +resume_to_ddr: + /* We are back. Branch to the common CPU resume routine */ + mov r0, #0 + ldr pc, resume_addr +ENDPROC(am33xx_resume_from_deep_sleep) + +/* + * Local variables + */ + .align +kernel_flush: + .word v7_flush_dcache_all +virt_mpu_clkctrl: + .word AM33XX_CM_MPU_MPU_CLKCTRL +virt_emif_clkctrl: + .word AM33XX_CM_PER_EMIF_CLKCTRL +phys_emif_clkctrl: + .word (AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \ + AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET) +module_disabled_val: + .word 0x30000 + +/* DDR related defines */ +am33xx_emif_sram_table: +ti_emif_save_context: + .word 0x00000000 +ti_emif_restore_context: + .word 0x00000000 +ti_emif_enter_sr: + .word 0x00000000 +ti_emif_exit_sr: + .word 0x00000000 +ti_emif_abort_sr: + .word 0x00000000 + .align 3 + .space 64 +temp_stack: + +ENTRY(am33xx_pm_sram) +.word am33xx_do_wfi +.word am33xx_do_wfi_sz +.word am33xx_resume_offset +.word am33xx_emif_sram_table +rtc_base_virt: +.word 0xdeadbeef +resume_addr: +.word cpu_resume - PAGE_OFFSET + 0x80000000 + +ENTRY(am33xx_do_wfi_sz) + .word . - am33xx_do_wfi diff -Naur --no-dereference a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S --- a/arch/arm/mach-omap2/sleep43xx.S 1969-12-31 19:00:00.000000000 -0500 +++ b/arch/arm/mach-omap2/sleep43xx.S 2016-05-11 13:31:53.193225201 -0400 @@ -0,0 +1,507 @@ +/* + * Low level suspend code for AM43XX SoCs + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Dave Gerlach + * Vaibhav Bedia + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#include "iomap.h" +#include "cm33xx.h" +#include "prm33xx.h" +#include "prcm43xx.h" + +#include "common.h" +#include "omap-secure.h" +#include "omap44xx.h" +#include + +#define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0 + +#define EMIF_POWER_MGMT_SELF_REFRESH_MODE 0x0200 +#define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700 +#define EMIF_POWER_MGMT_DELAY_PERIOD 0x1000 + +#define EMIF_LPDDR2_AM43XX_REFRESH_EN_CS0 0x40000002 +#define EMIF_LPDDR2_AM43XX_REFRESH_EN_CS1 0xC0000002 +#define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120 + +#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 +#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002 + +#define AM43XX_EMIF_POWEROFF_ENABLE 0x1 +#define AM43XX_EMIF_POWEROFF_DISABLE 0x0 + +#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1 +#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 0x3 + +#define AM43XX_CM_BASE 0x44DF0000 + +#define AM43XX_CTRL_CKE_OVERRIDE 0x44E1131C + +#define AM43XX_CM_REGADDR(inst, reg) \ + AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg)) + +#define AM43XX_PM_MPU_PWRSTCTRL AM43XX_CM_REGADDR(0x0300, 0x00) +#define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(0x8300, 0x00) +#define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(0x8300, 0x20) +#define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(0x8800, 0x0720) + +#define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 +#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x30 + +#define RTC_SECONDS_REG 0x0 +#define RTC_PMIC_REG 0x98 +#define RTC_PMIC_POWER_EN (1 << 16) +#define RTC_PMIC_EXT_WAKEUP_STS (1 << 12) +#define RTC_PMIC_EXT_WAKEUP_POL (1 << 4) +#define RTC_PMIC_EXT_WAKEUP_EN (1 << 0) + +#define WFI_FLAG_RTC_ONLY (1 << 8) + + .text + .align 3 + +ENTRY(am43xx_do_wfi) + stmfd sp!, {r4 - r11, lr} @ save registers on stack + +ARM( str r0, wfi_flags ) +THUMB( adr r1, wfi_flags ) +THUMB( str r0, [r1] ) + + /* Retrieve l2 cache virt address BEFORE we shut off EMIF */ + ldr r1, get_l2cache_base + blx r1 +ARM( str r0, l2_base_virt ) +THUMB( adr r1, l2_base_virt ) +THUMB( str r0, [r1] ) + + /* + * Flush all data from the L1 and L2 data cache before disabling + * SCTLR.C bit. + */ + ldr r1, kernel_flush + blx r1 + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + dsb + + /* + * Invalidate L1 and L2 data cache. + */ + ldr r1, kernel_flush + blx r1 + + /* + * The kernel doesn't interwork: v7_flush_dcache_all in particluar will + * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. + * This sequence switches back to ARM. Note that .align may insert a + * nop: bx pc needs to be word-aligned in order to work. + */ + THUMB( .thumb ) + THUMB( .align ) + THUMB( bx pc ) + THUMB( nop ) + .arm + +#ifdef CONFIG_CACHE_L2X0 + /* + * Clean and invalidate the L2 cache. + */ +#ifdef CONFIG_PL310_ERRATA_727915 + mov r0, #0x03 + mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX + dsb + smc #0 + dsb +#endif + ldr r0, l2_base_virt + + mov r2, r0 + ldr r0, [r2, #L2X0_AUX_CTRL] + str r0, l2_aux_ctrl_val + ldr r0, [r2, #L310_PREFETCH_CTRL] + str r0, l2_prefetch_ctrl_val + + ldr r0, l2_val + str r0, [r2, #L2X0_CLEAN_INV_WAY] +wait: + ldr r0, [r2, #L2X0_CLEAN_INV_WAY] + ldr r1, l2_val + ands r0, r0, r1 + bne wait +#ifdef CONFIG_PL310_ERRATA_727915 + mov r0, #0x00 + mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX + dsb + smc #0 + dsb +#endif +l2x_sync: + ldr r0, l2_base_virt + mov r2, r0 + mov r0, #0x0 + str r0, [r2, #L2X0_CACHE_SYNC] +sync: + ldr r0, [r2, #L2X0_CACHE_SYNC] + ands r0, r0, #0x1 + bne sync +#endif + + /* + * If we are trying to enter RTC+DDR mode we must perform + * a read from the rtc address space to ensure translation + * presence in the TLB to avoid page table walk after DDR + * is unavailable. + */ + ldr r1, wfi_flags + tst r1, #WFI_FLAG_RTC_ONLY + beq skip_rtc_va_refresh + + ldr r1, rtc_base_virt + ldr r0, [r1] + +skip_rtc_va_refresh: + mov r0, #0x1 + ldr r1, ti_emif_save_context + blx r1 + + ldr r1, ti_emif_enter_sr + blx r1 + + mov r1, #EMIF_POWER_MGMT_DELAY_PERIOD +wait_self_refresh: + subs r1, r1, #1 + bne wait_self_refresh + + /* Disable EMIF */ + ldr r1, am43xx_virt_emif_clkctrl + ldr r2, [r1] + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE + str r2, [r1] + +wait_emif_disable: + ldr r2, [r1] + ldr r3, module_disabled_val + cmp r2, r3 + bne wait_emif_disable + + ldr r1, wfi_flags + + tst r1, #WFI_FLAG_RTC_ONLY + beq am43xx_deep_sleep_suspend + + ldr r1, rtc_base_virt + + ldr r0, [r1, #RTC_PMIC_REG] + orr r0, r0, #RTC_PMIC_POWER_EN + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_STS + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_EN + orr r0, r0, #RTC_PMIC_EXT_WAKEUP_POL + str r0, [r1, #RTC_PMIC_REG] + ldr r0, [r1, #RTC_PMIC_REG] + /* Wait for 2 seconds to lose power */ + mov r3, #2 + ldr r2, [r1, #RTC_SECONDS_REG] +rtc_loop: + ldr r0, [r1, #RTC_SECONDS_REG] + cmp r0, r2 + beq rtc_loop + mov r2, r0 + subs r3, r3, #1 + bne rtc_loop + + b re_enable_emif + +am43xx_deep_sleep_suspend: + /* + * For the MPU WFI to be registered as an interrupt + * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set + * to DISABLED + */ + ldr r1, am43xx_virt_mpu_clkctrl + ldr r2, [r1] + bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE + str r2, [r1] + + /* + * Put MPU CLKDM to SW_SLEEP + */ + ldr r1, am43xx_virt_mpu_clkstctrl + mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP + str r2, [r1] + + /* + * Execute a barrier instruction to ensure that all cache, + * TLB and branch predictor maintenance operations issued + * have completed. + */ + dsb + dmb + + /* + * Execute a WFI instruction and wait until the + * STANDBYWFI output is asserted to indicate that the + * CPU is in idle and low power state. CPU can specualatively + * prefetch the instructions so add NOPs after WFI. Sixteen + * NOPs as per Cortex-A9 pipeline. + */ + wfi + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* We come here in case of an abort due to a late interrupt */ + ldr r1, am43xx_virt_mpu_clkstctrl + mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO + str r2, [r1] + + /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */ + ldr r1, am43xx_virt_mpu_clkctrl + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r2, [r1] + +re_enable_emif: + /* Re-enable EMIF */ + ldr r1, am43xx_virt_emif_clkctrl + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r2, [r1] +wait_emif_enable: + ldr r3, [r1] + cmp r2, r3 + bne wait_emif_enable + + /* + * Set SCTLR.C bit to allow data cache allocation + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #(1 << 2) @ Enable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + ldr r1, ti_emif_abort_sr + blx r1 + + /* EMIF needs some time before read/write possible */ + mov r0, #EMIF_POWER_MGMT_DELAY_PERIOD +wait_abt: + subs r0, r0, #1 + bne wait_abt + + /* Let the suspend code know about the abort */ + mov r0, #1 + ldmfd sp!, {r4 - r11, pc} @ restore regs and return +ENDPROC(am43xx_do_wfi) + + .align +ENTRY(am43xx_resume_offset) + .word . - am43xx_do_wfi + +ENTRY(am43xx_resume_from_deep_sleep) + /* Set MPU CLKSTCTRL to HW AUTO so that CPUidle works properly */ + ldr r1, am43xx_virt_mpu_clkstctrl + mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO + str r2, [r1] + + /* For AM43xx, use EMIF power down until context is restored */ + ldr r2, am43xx_phys_emif_poweroff + mov r1, #AM43XX_EMIF_POWEROFF_ENABLE + str r1, [r2, #0x0] + + /* Re-enable EMIF */ + ldr r1, am43xx_phys_emif_clkctrl + mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE + str r2, [r1] +wait_emif_enable1: + ldr r3, [r1] + cmp r2, r3 + bne wait_emif_enable1 + + adr sp, temp_stack + + mov r0, #0x1 + ldr r1, ti_emif_restore_context + blx r1 + + ldr r1, ti_emif_exit_sr + blx r1 + + ldr r2, am43xx_phys_emif_poweroff + mov r1, #AM43XX_EMIF_POWEROFF_DISABLE + str r1, [r2, #0x0] + +#ifdef CONFIG_CACHE_L2X0 + ldr r2, l2_cache_base + ldr r0, [r2, #L2X0_CTRL] + and r0, #0x0f + cmp r0, #1 + beq skip_l2en @ Skip if already enabled + ldr r0, l2_prefetch_ctrl_val + + ldr r12, l2_smc1 + dsb + smc #0 + dsb +set_aux_ctrl: + ldr r0, l2_aux_ctrl_val + ldr r12, l2_smc2 + dsb + smc #0 + dsb + + /* L2 invalidate on resume */ + ldr r0, l2_val + ldr r2, l2_cache_base + str r0, [r2, #L2X0_INV_WAY] +wait2: + ldr r0, [r2, #L2X0_INV_WAY] + ldr r1, l2_val + ands r0, r0, r1 + bne wait2 +#ifdef CONFIG_PL310_ERRATA_727915 + mov r0, #0x00 + mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX + dsb + smc #0 + dsb +#endif +l2x_sync2: + ldr r2, l2_cache_base + mov r0, #0x0 + str r0, [r2, #L2X0_CACHE_SYNC] +sync2: + ldr r0, [r2, #L2X0_CACHE_SYNC] + ands r0, r0, #0x1 + bne sync2 + + mov r0, #0x1 + ldr r12, l2_smc3 + dsb + smc #0 + dsb +#endif +skip_l2en: + /* We are back. Branch to the common CPU resume routine */ + mov r0, #0 + ldr pc, resume_addr +ENDPROC(am43xx_resume_from_deep_sleep) + +/* + * Local variables + */ + .align +get_l2cache_base: + .word omap4_get_l2cache_base +kernel_flush: + .word v7_flush_dcache_all +ddr_start: + .word PAGE_OFFSET + +wfi_flags: + .word 0 + +cke_override_virt: + .word 0xDEADBEEF +cke_override_phys: + .word AM43XX_CTRL_CKE_OVERRIDE + +am43xx_phys_emif_poweroff: + .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \ + AM43XX_PRM_EMIF_CTRL_OFFSET) +am43xx_virt_mpu_pwrstctrl: + .word (AM43XX_PM_MPU_PWRSTCTRL) +am43xx_virt_mpu_clkstctrl: + .word (AM43XX_CM_MPU_CLKSTCTRL) +am43xx_virt_mpu_clkctrl: + .word (AM43XX_CM_MPU_MPU_CLKCTRL) +am43xx_virt_emif_clkctrl: + .word (AM43XX_CM_PER_EMIF_CLKCTRL) +am43xx_phys_emif_clkctrl: + .word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \ + AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) +module_disabled_val: + .word 0x30000 + +/* L2 cache related defines for AM437x */ +l2_base_virt: + .word 0xDEADBEEF +l2_aux_ctrl_val: + .word 0xDEADBEEF +l2_prefetch_ctrl_val: + .word 0xDEADBEEF +l2_cache_base: + .word OMAP44XX_L2CACHE_BASE +l2_val: + .word 0xffff +l2_smc1: + .word OMAP4_MON_L2X0_PREFETCH_INDEX +l2_smc2: + .word OMAP4_MON_L2X0_AUXCTRL_INDEX +l2_smc3: + .word OMAP4_MON_L2X0_CTRL_INDEX + + +/* DDR related defines */ +ENTRY(am43xx_emif_sram_table) +ti_emif_save_context: + .word 0x00000000 +ti_emif_restore_context: + .word 0x00000000 +ti_emif_enter_sr: + .word 0x00000000 +ti_emif_exit_sr: + .word 0x00000000 +ti_emif_abort_sr: + .word 0x00000000 + .align 3 + .space 64 +temp_stack: + .align 3 + +ENTRY(am43xx_pm_sram) +.word am43xx_do_wfi +.word am43xx_do_wfi_sz +.word am43xx_resume_offset +.word am43xx_emif_sram_table +rtc_base_virt: +.word 0xdeadbeef +resume_addr: +.word cpu_resume - PAGE_OFFSET + 0x80000000 + +ENTRY(am43xx_do_wfi_sz) + .word . - am43xx_do_wfi diff -Naur --no-dereference a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h --- a/arch/arm/mach-omap2/soc.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/soc.h 2016-05-11 13:31:53.193225201 -0400 @@ -181,6 +181,14 @@ return (GET_TI_CLASS == (id)) ? 1 : 0; \ } +#define GET_DRA_CLASS ((omap_rev() >> 24) & 0xff) + +#define IS_DRA_CLASS(class, id) \ +static inline int is_dra ##class (void) \ +{ \ + return (GET_DRA_CLASS == (id)) ? 1 : 0; \ +} + #define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff) #define IS_OMAP_SUBCLASS(subclass, id) \ @@ -201,6 +209,12 @@ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } +#define IS_DRA_SUBCLASS(subclass, id) \ +static inline int is_dra ##subclass (void) \ +{ \ + return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ +} + IS_OMAP_CLASS(24xx, 0x24) IS_OMAP_CLASS(34xx, 0x34) IS_OMAP_CLASS(44xx, 0x44) @@ -210,6 +224,7 @@ IS_AM_CLASS(43xx, 0x43) IS_TI_CLASS(81xx, 0x81) +IS_DRA_CLASS(7xx, 0x7) IS_OMAP_SUBCLASS(242x, 0x242) IS_OMAP_SUBCLASS(243x, 0x243) @@ -224,6 +239,8 @@ IS_TI_SUBCLASS(814x, 0x814) IS_AM_SUBCLASS(335x, 0x335) IS_AM_SUBCLASS(437x, 0x437) +IS_DRA_SUBCLASS(75x, 0x75) +IS_DRA_SUBCLASS(72x, 0x72) #define soc_is_omap24xx() 0 #define soc_is_omap242x() 0 @@ -397,9 +414,9 @@ #undef soc_is_dra7xx #undef soc_is_dra74x #undef soc_is_dra72x -#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) -#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74")) -#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72")) +#define soc_is_dra7xx() is_dra7xx() +#define soc_is_dra74x() is_dra75x() +#define soc_is_dra72x() is_dra72x() #endif /* Various silicon revisions for omap2 */ @@ -471,7 +488,7 @@ #define DRA752_REV_ES1_1 (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8)) #define DRA752_REV_ES2_0 (DRA7XX_CLASS | (0x52 << 16) | (0x20 << 8)) #define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) -#define DRA722_REV_ES1_0 (DRA7XX_CLASS | (0x22 << 16) | (0x10 << 8)) +#define DRA722_REV_ES2_0 (DRA7XX_CLASS | (0x22 << 16) | (0x20 << 8)) void omap2xxx_check_revision(void); void omap3xxx_check_revision(void); diff -Naur --no-dereference a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c --- a/arch/arm/mach-omap2/timer.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-omap2/timer.c 2016-05-11 13:31:53.193225201 -0400 @@ -68,6 +68,9 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +/* Clockevent hwmod for am335x and am437x suspend */ +struct omap_hwmod *clockevent_gpt_hwmod; + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; @@ -125,6 +128,23 @@ return 0; } +static void omap_clkevt_idle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_idle(clockevent_gpt_hwmod); +} + +static void omap_clkevt_unidle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_enable(clockevent_gpt_hwmod); + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); +} + static struct clock_event_device clockevent_gpt = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, @@ -194,8 +214,8 @@ /** * omap_dmtimer_init - initialisation function when device tree is used * - * For secure OMAP3 devices, timers with device type "timer-secure" cannot - * be used by the kernel as they are reserved. Therefore, to prevent the + * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure" + * cannot be used by the kernel as they are reserved. Therefore, to prevent the * kernel registering these devices remove them dynamically from the device * tree on boot. */ @@ -203,7 +223,7 @@ { struct device_node *np; - if (!cpu_is_omap34xx()) + if (!cpu_is_omap34xx() && !soc_is_dra7xx()) return; /* If we are a secure device, remove any secure timer nodes */ @@ -357,6 +377,14 @@ 3, /* Timer internal resynch latency */ 0xffffffff); + if (soc_is_am33xx() || soc_is_am43xx()) { + clockevent_gpt.suspend = omap_clkevt_idle; + clockevent_gpt.resume = omap_clkevt_unidle; + + clockevent_gpt_hwmod = + omap_hwmod_lookup(clockevent_gpt.name); + } + pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, clkev.rate); } @@ -375,7 +403,7 @@ } static struct clocksource clocksource_gpt = { - .rating = 300, + .rating = 290, .read = clocksource_read_cycles, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, @@ -448,6 +476,38 @@ return ret; } +static unsigned omap2_gptimer_clksrc_load; + +static void omap2_gptimer_clksrc_suspend(struct clocksource *unused) +{ + struct omap_hwmod *oh; + + omap2_gptimer_clksrc_load = + __omap_dm_timer_read_counter(&clksrc, OMAP_TIMER_NONPOSTED); + + oh = omap_hwmod_lookup(clocksource_gpt.name); + if (!oh) + return; + + omap_hwmod_idle(oh); +} + +static void omap2_gptimer_clksrc_resume(struct clocksource *unused) +{ + struct omap_hwmod *oh; + + oh = omap_hwmod_lookup(clocksource_gpt.name); + if (!oh) + return; + + omap_hwmod_enable(oh); + + __omap_dm_timer_load_start(&clksrc, + OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, + omap2_gptimer_clksrc_load, + OMAP_TIMER_NONPOSTED); +} + static void __init omap2_gptimer_clocksource_init(int gptimer_id, const char *fck_source, const char *property) @@ -457,6 +517,11 @@ clksrc.id = gptimer_id; clksrc.errata = omap_dm_timer_get_errata(); + if (soc_is_am43xx()) { + clocksource_gpt.suspend = omap2_gptimer_clksrc_suspend; + clocksource_gpt.resume = omap2_gptimer_clksrc_resume; + } + res = omap_dm_timer_init_one(&clksrc, fck_source, property, &clocksource_gpt.name, OMAP_TIMER_NONPOSTED); diff -Naur --no-dereference a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c --- a/arch/arm/mach-prima2/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-prima2/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -22,7 +22,7 @@ static void __iomem *clk_base; -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); static void sirfsoc_secondary_init(unsigned int cpu) { @@ -36,8 +36,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } static const struct of_device_id clk_ids[] = { @@ -75,7 +75,7 @@ /* make sure write buffer is drained */ mb(); - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from @@ -107,7 +107,7 @@ * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; } diff -Naur --no-dereference a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c --- a/arch/arm/mach-qcom/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-qcom/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -46,7 +46,7 @@ extern void secondary_startup_arm(void); -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); #ifdef CONFIG_HOTPLUG_CPU static void qcom_cpu_die(unsigned int cpu) @@ -60,8 +60,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } static int scss_release_secondary(unsigned int cpu) @@ -284,7 +284,7 @@ * set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * Send the secondary CPU a soft interrupt, thereby causing @@ -297,7 +297,7 @@ * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return ret; } diff -Naur --no-dereference a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c --- a/arch/arm/mach-spear/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-spear/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -32,7 +32,7 @@ sync_cache_w(&pen_release); } -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); static void __iomem *scu_base = IOMEM(VA_SCU_BASE); @@ -47,8 +47,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -59,7 +59,7 @@ * set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from @@ -84,7 +84,7 @@ * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; } diff -Naur --no-dereference a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c --- a/arch/arm/mach-sti/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mach-sti/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -35,7 +35,7 @@ sync_cache_w(&pen_release); } -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); static void sti_secondary_init(unsigned int cpu) { @@ -48,8 +48,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -60,7 +60,7 @@ * set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * The secondary processor is waiting to be released from @@ -91,7 +91,7 @@ * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; } diff -Naur --no-dereference a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c --- a/arch/arm/mm/fault.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mm/fault.c 2016-05-11 13:31:53.193225201 -0400 @@ -430,6 +430,9 @@ if (addr < TASK_SIZE) return do_page_fault(addr, fsr, regs); + if (interrupts_enabled(regs)) + local_irq_enable(); + if (user_mode(regs)) goto bad_area; @@ -497,6 +500,9 @@ static int do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { + if (interrupts_enabled(regs)) + local_irq_enable(); + do_bad_area(addr, fsr, regs); return 0; } diff -Naur --no-dereference a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c --- a/arch/arm/mm/highmem.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mm/highmem.c 2016-05-11 13:31:53.193225201 -0400 @@ -34,6 +34,11 @@ return *ptep; } +static unsigned int fixmap_idx(int type) +{ + return FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); +} + void *kmap(struct page *page) { might_sleep(); @@ -54,12 +59,13 @@ void *kmap_atomic(struct page *page) { + pte_t pte = mk_pte(page, kmap_prot); unsigned int idx; unsigned long vaddr; void *kmap; int type; - preempt_disable(); + preempt_disable_nort(); pagefault_disable(); if (!PageHighMem(page)) return page_address(page); @@ -79,7 +85,7 @@ type = kmap_atomic_idx_push(); - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); + idx = fixmap_idx(type); vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM /* @@ -93,7 +99,10 @@ * in place, so the contained TLB flush ensures the TLB is updated * with the new mapping. */ - set_fixmap_pte(idx, mk_pte(page, kmap_prot)); +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = pte; +#endif + set_fixmap_pte(idx, pte); return (void *)vaddr; } @@ -106,44 +115,75 @@ if (kvaddr >= (void *)FIXADDR_START) { type = kmap_atomic_idx(); - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); + idx = fixmap_idx(type); if (cache_is_vivt()) __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = __pte(0); +#endif #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(vaddr != __fix_to_virt(idx)); - set_fixmap_pte(idx, __pte(0)); #else (void) idx; /* to kill a warning */ #endif + set_fixmap_pte(idx, __pte(0)); kmap_atomic_idx_pop(); } else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) { /* this address was obtained through kmap_high_get() */ kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)])); } pagefault_enable(); - preempt_enable(); + preempt_enable_nort(); } EXPORT_SYMBOL(__kunmap_atomic); void *kmap_atomic_pfn(unsigned long pfn) { + pte_t pte = pfn_pte(pfn, kmap_prot); unsigned long vaddr; int idx, type; struct page *page = pfn_to_page(pfn); - preempt_disable(); + preempt_disable_nort(); pagefault_disable(); if (!PageHighMem(page)) return page_address(page); type = kmap_atomic_idx_push(); - idx = FIX_KMAP_BEGIN + type + KM_TYPE_NR * smp_processor_id(); + idx = fixmap_idx(type); vaddr = __fix_to_virt(idx); #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(!pte_none(get_fixmap_pte(vaddr))); #endif - set_fixmap_pte(idx, pfn_pte(pfn, kmap_prot)); +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = pte; +#endif + set_fixmap_pte(idx, pte); return (void *)vaddr; } +#if defined CONFIG_PREEMPT_RT_FULL +void switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p) +{ + int i; + + /* + * Clear @prev's kmap_atomic mappings + */ + for (i = 0; i < prev_p->kmap_idx; i++) { + int idx = fixmap_idx(i); + + set_fixmap_pte(idx, __pte(0)); + } + /* + * Restore @next_p's kmap_atomic mappings + */ + for (i = 0; i < next_p->kmap_idx; i++) { + int idx = fixmap_idx(i); + + if (!pte_none(next_p->kmap_pte[i])) + set_fixmap_pte(idx, next_p->kmap_pte[i]); + } +} +#endif diff -Naur --no-dereference a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c --- a/arch/arm/mm/ioremap.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mm/ioremap.c 2016-05-11 13:31:53.193225201 -0400 @@ -399,6 +399,20 @@ * clocks that would affect normal memory for example. Please see * CONFIG_GENERIC_ALLOCATOR for allocating external memory. */ +void __iomem *ioremap_exec(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RWX, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_exec); + +void __iomem *ioremap_exec_nocache(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RWX_NONCACHED, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_exec_nocache); + void __iomem * __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached) { diff -Naur --no-dereference a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c --- a/arch/arm/mm/nommu.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/mm/nommu.c 2016-05-11 13:31:53.193225201 -0400 @@ -380,6 +380,20 @@ } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_exec(resource_size_t res_cookie, size_t size) +{ + return __arm_ioremap_caller(res_cookie, size, 0, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_exec); + +void __iomem *ioremap_exec_nocache(resource_size_t res_cookie, size_t size) +{ + return __arm_ioremap_caller(res_cookie, size, 0, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_exec_nocache); + void __iounmap(volatile void __iomem *addr) { } diff -Naur --no-dereference a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c --- a/arch/arm/plat-omap/dmtimer.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/plat-omap/dmtimer.c 2016-05-11 13:31:53.193225201 -0400 @@ -36,6 +36,7 @@ */ #include +#include #include #include #include @@ -504,6 +505,12 @@ if (IS_ERR(timer->fclk)) return -EINVAL; +#if defined(CONFIG_COMMON_CLK) + /* Check if the clock has configurable parents */ + if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) + return 0; +#endif + switch (source) { case OMAP_TIMER_SRC_SYS_CLK: parent_name = "timer_sys_ck"; diff -Naur --no-dereference a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c --- a/arch/arm/plat-versatile/platsmp.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm/plat-versatile/platsmp.c 2016-05-11 13:31:53.193225201 -0400 @@ -30,7 +30,7 @@ sync_cache_w(&pen_release); } -static DEFINE_SPINLOCK(boot_lock); +static DEFINE_RAW_SPINLOCK(boot_lock); void versatile_secondary_init(unsigned int cpu) { @@ -43,8 +43,8 @@ /* * Synchronise with the boot thread. */ - spin_lock(&boot_lock); - spin_unlock(&boot_lock); + raw_spin_lock(&boot_lock); + raw_spin_unlock(&boot_lock); } int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) @@ -55,7 +55,7 @@ * Set synchronisation state between this boot processor * and the secondary one */ - spin_lock(&boot_lock); + raw_spin_lock(&boot_lock); /* * This is really belt and braces; we hold unintended secondary @@ -85,7 +85,7 @@ * now the secondary core is starting up let it run its * calibrations, then wait for it to finish */ - spin_unlock(&boot_lock); + raw_spin_unlock(&boot_lock); return pen_release != -1 ? -ENOSYS : 0; } diff -Naur --no-dereference a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h --- a/arch/arm64/include/asm/thread_info.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm64/include/asm/thread_info.h 2016-05-11 13:31:53.193225201 -0400 @@ -49,6 +49,7 @@ mm_segment_t addr_limit; /* address limit */ struct task_struct *task; /* main task structure */ int preempt_count; /* 0 => preemptable, <0 => bug */ + int preempt_lazy_count; /* 0 => preemptable, <0 => bug */ int cpu; /* cpu */ }; @@ -103,6 +104,7 @@ #define TIF_NEED_RESCHED 1 #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ #define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */ +#define TIF_NEED_RESCHED_LAZY 4 #define TIF_NOHZ 7 #define TIF_SYSCALL_TRACE 8 #define TIF_SYSCALL_AUDIT 9 @@ -118,6 +120,7 @@ #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) #define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) #define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE) +#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) #define _TIF_NOHZ (1 << TIF_NOHZ) #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) @@ -126,7 +129,8 @@ #define _TIF_32BIT (1 << TIF_32BIT) #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \ - _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE) + _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \ + _TIF_NEED_RESCHED_LAZY) #define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \ _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \ diff -Naur --no-dereference a/arch/arm64/Kconfig b/arch/arm64/Kconfig --- a/arch/arm64/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm64/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -76,6 +76,7 @@ select HAVE_PERF_REGS select HAVE_PERF_USER_STACK_DUMP select HAVE_RCU_TABLE_FREE + select HAVE_PREEMPT_LAZY select HAVE_SYSCALL_TRACEPOINTS select IOMMU_DMA if IOMMU_SUPPORT select IRQ_DOMAIN @@ -562,7 +563,7 @@ config XEN bool "Xen guest support on ARM64" - depends on ARM64 && OF + depends on ARM64 && OF && !PREEMPT_RT_FULL select SWIOTLB_XEN help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. diff -Naur --no-dereference a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c --- a/arch/arm64/kernel/asm-offsets.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm64/kernel/asm-offsets.c 2016-05-11 13:31:53.193225201 -0400 @@ -35,6 +35,7 @@ BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TI_PREEMPT_LAZY, offsetof(struct thread_info, preempt_lazy_count)); DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); diff -Naur --no-dereference a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S --- a/arch/arm64/kernel/entry.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/arm64/kernel/entry.S 2016-05-11 13:31:53.193225201 -0400 @@ -363,11 +363,16 @@ #ifdef CONFIG_PREEMPT get_thread_info tsk ldr w24, [tsk, #TI_PREEMPT] // get preempt count - cbnz w24, 1f // preempt count != 0 + cbnz w24, 2f // preempt count != 0 ldr x0, [tsk, #TI_FLAGS] // get flags - tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? - bl el1_preempt + tbnz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? + + ldr w24, [tsk, #TI_PREEMPT_LAZY] // get preempt lazy count + cbnz w24, 2f // preempt lazy count != 0 + tbz x0, #TIF_NEED_RESCHED_LAZY, 2f // needs rescheduling? 1: + bl el1_preempt +2: #endif #ifdef CONFIG_TRACE_IRQFLAGS bl trace_hardirqs_on @@ -381,6 +386,7 @@ 1: bl preempt_schedule_irq // irq en/disable is done inside ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling? + tbnz x0, #TIF_NEED_RESCHED_LAZY, 1b // needs rescheduling? ret x24 #endif @@ -625,6 +631,7 @@ */ work_pending: tbnz x1, #TIF_NEED_RESCHED, work_resched + tbnz x1, #TIF_NEED_RESCHED_LAZY, work_resched /* TIF_SIGPENDING, TIF_NOTIFY_RESUME or TIF_FOREIGN_FPSTATE case */ ldr x2, [sp, #S_PSTATE] mov x0, sp // 'regs' diff -Naur --no-dereference a/arch/Kconfig b/arch/Kconfig --- a/arch/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/Kconfig 2016-05-11 13:31:53.189225170 -0400 @@ -9,6 +9,7 @@ tristate "OProfile system profiling" depends on PROFILING depends on HAVE_OPROFILE + depends on !PREEMPT_RT_FULL select RING_BUFFER select RING_BUFFER_ALLOW_SWAP help @@ -52,6 +53,7 @@ config JUMP_LABEL bool "Optimize very unlikely/likely branches" depends on HAVE_ARCH_JUMP_LABEL + depends on (!INTERRUPT_OFF_HIST && !PREEMPT_OFF_HIST && !WAKEUP_LATENCY_HIST && !MISSED_TIMER_OFFSETS_HIST) help This option enables a transparent branch optimization that makes certain almost-always-true or almost-always-false branch diff -Naur --no-dereference a/arch/mips/Kconfig b/arch/mips/Kconfig --- a/arch/mips/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/mips/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -2410,7 +2410,7 @@ # config HIGHMEM bool "High Memory Support" - depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA + depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA && !PREEMPT_RT_FULL config CPU_SUPPORTS_HIGHMEM bool diff -Naur --no-dereference a/arch/mips/kvm/mips.c b/arch/mips/kvm/mips.c --- a/arch/mips/kvm/mips.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/mips/kvm/mips.c 2016-05-11 13:31:53.193225201 -0400 @@ -445,8 +445,8 @@ dvcpu->arch.wait = 0; - if (waitqueue_active(&dvcpu->wq)) - wake_up_interruptible(&dvcpu->wq); + if (swait_active(&dvcpu->wq)) + swake_up(&dvcpu->wq); return 0; } @@ -1174,8 +1174,8 @@ kvm_mips_callbacks->queue_timer_int(vcpu); vcpu->arch.wait = 0; - if (waitqueue_active(&vcpu->wq)) - wake_up_interruptible(&vcpu->wq); + if (swait_active(&vcpu->wq)) + swake_up(&vcpu->wq); } /* low level hrtimer wake routine */ diff -Naur --no-dereference a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h --- a/arch/powerpc/include/asm/kvm_host.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/include/asm/kvm_host.h 2016-05-11 13:31:53.193225201 -0400 @@ -286,7 +286,7 @@ struct list_head runnable_threads; struct list_head preempt_list; spinlock_t lock; - wait_queue_head_t wq; + struct swait_queue_head wq; spinlock_t stoltb_lock; /* protects stolen_tb and preempt_tb */ u64 stolen_tb; u64 preempt_tb; @@ -626,7 +626,7 @@ u8 prodded; u32 last_inst; - wait_queue_head_t *wqp; + struct swait_queue_head *wqp; struct kvmppc_vcore *vcore; int ret; int trap; diff -Naur --no-dereference a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h --- a/arch/powerpc/include/asm/thread_info.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/include/asm/thread_info.h 2016-05-11 13:31:53.193225201 -0400 @@ -42,6 +42,8 @@ int cpu; /* cpu we're on */ int preempt_count; /* 0 => preemptable, <0 => BUG */ + int preempt_lazy_count; /* 0 => preemptable, + <0 => BUG */ unsigned long local_flags; /* private flags for thread */ /* low level flags - has atomic operations done on it */ @@ -82,8 +84,7 @@ #define TIF_SYSCALL_TRACE 0 /* syscall trace active */ #define TIF_SIGPENDING 1 /* signal pending */ #define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling - TIF_NEED_RESCHED */ +#define TIF_NEED_RESCHED_LAZY 3 /* lazy rescheduling necessary */ #define TIF_32BIT 4 /* 32 bit binary */ #define TIF_RESTORE_TM 5 /* need to restore TM FP/VEC/VSX */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ @@ -101,6 +102,8 @@ #if defined(CONFIG_PPC64) #define TIF_ELF2ABI 18 /* function descriptors must die! */ #endif +#define TIF_POLLING_NRFLAG 19 /* true if poll_idle() is polling + TIF_NEED_RESCHED */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1<flags) set_bits(irqtp->flags, &curtp->flags); } +#endif irq_hw_number_t virq_to_hw(unsigned int virq) { diff -Naur --no-dereference a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S --- a/arch/powerpc/kernel/misc_32.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/kernel/misc_32.S 2016-05-11 13:31:53.193225201 -0400 @@ -40,6 +40,7 @@ * We store the saved ksp_limit in the unused part * of the STACK_FRAME_OVERHEAD */ +#ifndef CONFIG_PREEMPT_RT_FULL _GLOBAL(call_do_softirq) mflr r0 stw r0,4(r1) @@ -56,6 +57,7 @@ stw r10,THREAD+KSP_LIMIT(r2) mtlr r0 blr +#endif /* * void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp); diff -Naur --no-dereference a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S --- a/arch/powerpc/kernel/misc_64.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/kernel/misc_64.S 2016-05-11 13:31:53.193225201 -0400 @@ -30,6 +30,7 @@ .text +#ifndef CONFIG_PREEMPT_RT_FULL _GLOBAL(call_do_softirq) mflr r0 std r0,16(r1) @@ -40,6 +41,7 @@ ld r0,16(r1) mtlr r0 blr +#endif _GLOBAL(call_do_irq) mflr r0 diff -Naur --no-dereference a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c --- a/arch/powerpc/kvm/book3s_hv.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/kvm/book3s_hv.c 2016-05-11 13:31:53.193225201 -0400 @@ -114,11 +114,11 @@ static void kvmppc_fast_vcpu_kick_hv(struct kvm_vcpu *vcpu) { int cpu; - wait_queue_head_t *wqp; + struct swait_queue_head *wqp; wqp = kvm_arch_vcpu_wq(vcpu); - if (waitqueue_active(wqp)) { - wake_up_interruptible(wqp); + if (swait_active(wqp)) { + swake_up(wqp); ++vcpu->stat.halt_wakeup; } @@ -707,8 +707,8 @@ tvcpu->arch.prodded = 1; smp_mb(); if (vcpu->arch.ceded) { - if (waitqueue_active(&vcpu->wq)) { - wake_up_interruptible(&vcpu->wq); + if (swait_active(&vcpu->wq)) { + swake_up(&vcpu->wq); vcpu->stat.halt_wakeup++; } } @@ -1447,7 +1447,7 @@ INIT_LIST_HEAD(&vcore->runnable_threads); spin_lock_init(&vcore->lock); spin_lock_init(&vcore->stoltb_lock); - init_waitqueue_head(&vcore->wq); + init_swait_queue_head(&vcore->wq); vcore->preempt_tb = TB_NIL; vcore->lpcr = kvm->arch.lpcr; vcore->first_vcpuid = core * threads_per_subcore; @@ -2519,10 +2519,9 @@ { struct kvm_vcpu *vcpu; int do_sleep = 1; + DECLARE_SWAITQUEUE(wait); - DEFINE_WAIT(wait); - - prepare_to_wait(&vc->wq, &wait, TASK_INTERRUPTIBLE); + prepare_to_swait(&vc->wq, &wait, TASK_INTERRUPTIBLE); /* * Check one last time for pending exceptions and ceded state after @@ -2536,7 +2535,7 @@ } if (!do_sleep) { - finish_wait(&vc->wq, &wait); + finish_swait(&vc->wq, &wait); return; } @@ -2544,7 +2543,7 @@ trace_kvmppc_vcore_blocked(vc, 0); spin_unlock(&vc->lock); schedule(); - finish_wait(&vc->wq, &wait); + finish_swait(&vc->wq, &wait); spin_lock(&vc->lock); vc->vcore_state = VCORE_INACTIVE; trace_kvmppc_vcore_blocked(vc, 1); @@ -2600,7 +2599,7 @@ kvmppc_start_thread(vcpu, vc); trace_kvm_guest_enter(vcpu); } else if (vc->vcore_state == VCORE_SLEEPING) { - wake_up(&vc->wq); + swake_up(&vc->wq); } } diff -Naur --no-dereference a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig --- a/arch/powerpc/kvm/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/kvm/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -172,6 +172,7 @@ config KVM_MPIC bool "KVM in-kernel MPIC emulation" depends on KVM && E500 + depends on !PREEMPT_RT_FULL select HAVE_KVM_IRQCHIP select HAVE_KVM_IRQFD select HAVE_KVM_IRQ_ROUTING diff -Naur --no-dereference a/arch/powerpc/platforms/ps3/device-init.c b/arch/powerpc/platforms/ps3/device-init.c --- a/arch/powerpc/platforms/ps3/device-init.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/powerpc/platforms/ps3/device-init.c 2016-05-11 13:31:53.193225201 -0400 @@ -752,7 +752,7 @@ } pr_debug("%s:%u: notification %s issued\n", __func__, __LINE__, op); - res = wait_event_interruptible(dev->done.wait, + res = swait_event_interruptible(dev->done.wait, dev->done.done || kthread_should_stop()); if (kthread_should_stop()) res = -EINTR; diff -Naur --no-dereference a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h --- a/arch/s390/include/asm/kvm_host.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/s390/include/asm/kvm_host.h 2016-05-11 13:31:53.193225201 -0400 @@ -427,7 +427,7 @@ struct kvm_s390_local_interrupt { spinlock_t lock; struct kvm_s390_float_interrupt *float_int; - wait_queue_head_t *wq; + struct swait_queue_head *wq; atomic_t *cpuflags; DECLARE_BITMAP(sigp_emerg_pending, KVM_MAX_VCPUS); struct kvm_s390_irq_payload irq; diff -Naur --no-dereference a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c --- a/arch/s390/kvm/interrupt.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/s390/kvm/interrupt.c 2016-05-11 13:31:53.193225201 -0400 @@ -868,13 +868,13 @@ void kvm_s390_vcpu_wakeup(struct kvm_vcpu *vcpu) { - if (waitqueue_active(&vcpu->wq)) { + if (swait_active(&vcpu->wq)) { /* * The vcpu gave up the cpu voluntarily, mark it as a good * yield-candidate. */ vcpu->preempted = true; - wake_up_interruptible(&vcpu->wq); + swake_up(&vcpu->wq); vcpu->stat.halt_wakeup++; } } diff -Naur --no-dereference a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c --- a/arch/sh/kernel/irq.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/sh/kernel/irq.c 2016-05-11 13:31:53.193225201 -0400 @@ -147,6 +147,7 @@ hardirq_ctx[cpu] = NULL; } +#ifndef CONFIG_PREEMPT_RT_FULL void do_softirq_own_stack(void) { struct thread_info *curctx; @@ -174,6 +175,7 @@ "r5", "r6", "r7", "r8", "r9", "r15", "t", "pr" ); } +#endif #else static inline void handle_one_irq(unsigned int irq) { diff -Naur --no-dereference a/arch/sparc/Kconfig b/arch/sparc/Kconfig --- a/arch/sparc/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/sparc/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -189,12 +189,10 @@ source kernel/Kconfig.hz config RWSEM_GENERIC_SPINLOCK - bool - default y if SPARC32 + def_bool PREEMPT_RT_FULL config RWSEM_XCHGADD_ALGORITHM - bool - default y if SPARC64 + def_bool !RWSEM_GENERIC_SPINLOCK && !PREEMPT_RT_FULL config GENERIC_HWEIGHT bool diff -Naur --no-dereference a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c --- a/arch/sparc/kernel/irq_64.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/sparc/kernel/irq_64.c 2016-05-11 13:31:53.193225201 -0400 @@ -854,6 +854,7 @@ set_irq_regs(old_regs); } +#ifndef CONFIG_PREEMPT_RT_FULL void do_softirq_own_stack(void) { void *orig_sp, *sp = softirq_stack[smp_processor_id()]; @@ -868,6 +869,7 @@ __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp)); } +#endif #ifdef CONFIG_HOTPLUG_CPU void fixup_irqs(void) diff -Naur --no-dereference a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c --- a/arch/x86/crypto/aesni-intel_glue.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/crypto/aesni-intel_glue.c 2016-05-11 13:31:53.197225234 -0400 @@ -383,14 +383,14 @@ err = blkcipher_walk_virt(desc, &walk); desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { + kernel_fpu_begin(); aesni_ecb_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr, - nbytes & AES_BLOCK_MASK); + nbytes & AES_BLOCK_MASK); + kernel_fpu_end(); nbytes &= AES_BLOCK_SIZE - 1; err = blkcipher_walk_done(desc, &walk, nbytes); } - kernel_fpu_end(); return err; } @@ -407,14 +407,14 @@ err = blkcipher_walk_virt(desc, &walk); desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { + kernel_fpu_begin(); aesni_ecb_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr, nbytes & AES_BLOCK_MASK); + kernel_fpu_end(); nbytes &= AES_BLOCK_SIZE - 1; err = blkcipher_walk_done(desc, &walk, nbytes); } - kernel_fpu_end(); return err; } @@ -431,14 +431,14 @@ err = blkcipher_walk_virt(desc, &walk); desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { + kernel_fpu_begin(); aesni_cbc_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr, nbytes & AES_BLOCK_MASK, walk.iv); + kernel_fpu_end(); nbytes &= AES_BLOCK_SIZE - 1; err = blkcipher_walk_done(desc, &walk, nbytes); } - kernel_fpu_end(); return err; } @@ -455,14 +455,14 @@ err = blkcipher_walk_virt(desc, &walk); desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - kernel_fpu_begin(); while ((nbytes = walk.nbytes)) { + kernel_fpu_begin(); aesni_cbc_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr, nbytes & AES_BLOCK_MASK, walk.iv); + kernel_fpu_end(); nbytes &= AES_BLOCK_SIZE - 1; err = blkcipher_walk_done(desc, &walk, nbytes); } - kernel_fpu_end(); return err; } @@ -514,18 +514,20 @@ err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE); desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; - kernel_fpu_begin(); while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) { + kernel_fpu_begin(); aesni_ctr_enc_tfm(ctx, walk.dst.virt.addr, walk.src.virt.addr, nbytes & AES_BLOCK_MASK, walk.iv); + kernel_fpu_end(); nbytes &= AES_BLOCK_SIZE - 1; err = blkcipher_walk_done(desc, &walk, nbytes); } if (walk.nbytes) { + kernel_fpu_begin(); ctr_crypt_final(ctx, &walk); + kernel_fpu_end(); err = blkcipher_walk_done(desc, &walk, 0); } - kernel_fpu_end(); return err; } diff -Naur --no-dereference a/arch/x86/crypto/cast5_avx_glue.c b/arch/x86/crypto/cast5_avx_glue.c --- a/arch/x86/crypto/cast5_avx_glue.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/crypto/cast5_avx_glue.c 2016-05-11 13:31:53.197225234 -0400 @@ -59,7 +59,7 @@ static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk, bool enc) { - bool fpu_enabled = false; + bool fpu_enabled; struct cast5_ctx *ctx = crypto_blkcipher_ctx(desc->tfm); const unsigned int bsize = CAST5_BLOCK_SIZE; unsigned int nbytes; @@ -75,7 +75,7 @@ u8 *wsrc = walk->src.virt.addr; u8 *wdst = walk->dst.virt.addr; - fpu_enabled = cast5_fpu_begin(fpu_enabled, nbytes); + fpu_enabled = cast5_fpu_begin(false, nbytes); /* Process multi-block batch */ if (nbytes >= bsize * CAST5_PARALLEL_BLOCKS) { @@ -103,10 +103,9 @@ } while (nbytes >= bsize); done: + cast5_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, walk, nbytes); } - - cast5_fpu_end(fpu_enabled); return err; } @@ -227,7 +226,7 @@ static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes) { - bool fpu_enabled = false; + bool fpu_enabled; struct blkcipher_walk walk; int err; @@ -236,12 +235,11 @@ desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; while ((nbytes = walk.nbytes)) { - fpu_enabled = cast5_fpu_begin(fpu_enabled, nbytes); + fpu_enabled = cast5_fpu_begin(false, nbytes); nbytes = __cbc_decrypt(desc, &walk); + cast5_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, &walk, nbytes); } - - cast5_fpu_end(fpu_enabled); return err; } @@ -311,7 +309,7 @@ static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes) { - bool fpu_enabled = false; + bool fpu_enabled; struct blkcipher_walk walk; int err; @@ -320,13 +318,12 @@ desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP; while ((nbytes = walk.nbytes) >= CAST5_BLOCK_SIZE) { - fpu_enabled = cast5_fpu_begin(fpu_enabled, nbytes); + fpu_enabled = cast5_fpu_begin(false, nbytes); nbytes = __ctr_crypt(desc, &walk); + cast5_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, &walk, nbytes); } - cast5_fpu_end(fpu_enabled); - if (walk.nbytes) { ctr_crypt_final(desc, &walk); err = blkcipher_walk_done(desc, &walk, 0); diff -Naur --no-dereference a/arch/x86/crypto/glue_helper.c b/arch/x86/crypto/glue_helper.c --- a/arch/x86/crypto/glue_helper.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/crypto/glue_helper.c 2016-05-11 13:31:53.197225234 -0400 @@ -39,7 +39,7 @@ void *ctx = crypto_blkcipher_ctx(desc->tfm); const unsigned int bsize = 128 / 8; unsigned int nbytes, i, func_bytes; - bool fpu_enabled = false; + bool fpu_enabled; int err; err = blkcipher_walk_virt(desc, walk); @@ -49,7 +49,7 @@ u8 *wdst = walk->dst.virt.addr; fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit, - desc, fpu_enabled, nbytes); + desc, false, nbytes); for (i = 0; i < gctx->num_funcs; i++) { func_bytes = bsize * gctx->funcs[i].num_blocks; @@ -71,10 +71,10 @@ } done: + glue_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, walk, nbytes); } - glue_fpu_end(fpu_enabled); return err; } @@ -194,7 +194,7 @@ struct scatterlist *src, unsigned int nbytes) { const unsigned int bsize = 128 / 8; - bool fpu_enabled = false; + bool fpu_enabled; struct blkcipher_walk walk; int err; @@ -203,12 +203,12 @@ while ((nbytes = walk.nbytes)) { fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit, - desc, fpu_enabled, nbytes); + desc, false, nbytes); nbytes = __glue_cbc_decrypt_128bit(gctx, desc, &walk); + glue_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, &walk, nbytes); } - glue_fpu_end(fpu_enabled); return err; } EXPORT_SYMBOL_GPL(glue_cbc_decrypt_128bit); @@ -277,7 +277,7 @@ struct scatterlist *src, unsigned int nbytes) { const unsigned int bsize = 128 / 8; - bool fpu_enabled = false; + bool fpu_enabled; struct blkcipher_walk walk; int err; @@ -286,13 +286,12 @@ while ((nbytes = walk.nbytes) >= bsize) { fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit, - desc, fpu_enabled, nbytes); + desc, false, nbytes); nbytes = __glue_ctr_crypt_128bit(gctx, desc, &walk); + glue_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, &walk, nbytes); } - glue_fpu_end(fpu_enabled); - if (walk.nbytes) { glue_ctr_crypt_final_128bit( gctx->funcs[gctx->num_funcs - 1].fn_u.ctr, desc, &walk); @@ -347,7 +346,7 @@ void *tweak_ctx, void *crypt_ctx) { const unsigned int bsize = 128 / 8; - bool fpu_enabled = false; + bool fpu_enabled; struct blkcipher_walk walk; int err; @@ -360,21 +359,21 @@ /* set minimum length to bsize, for tweak_fn */ fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit, - desc, fpu_enabled, + desc, false, nbytes < bsize ? bsize : nbytes); - /* calculate first value of T */ tweak_fn(tweak_ctx, walk.iv, walk.iv); + glue_fpu_end(fpu_enabled); while (nbytes) { + fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit, + desc, false, nbytes); nbytes = __glue_xts_crypt_128bit(gctx, crypt_ctx, desc, &walk); + glue_fpu_end(fpu_enabled); err = blkcipher_walk_done(desc, &walk, nbytes); nbytes = walk.nbytes; } - - glue_fpu_end(fpu_enabled); - return err; } EXPORT_SYMBOL_GPL(glue_xts_crypt_128bit); diff -Naur --no-dereference a/arch/x86/entry/common.c b/arch/x86/entry/common.c --- a/arch/x86/entry/common.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/entry/common.c 2016-05-11 13:31:53.197225234 -0400 @@ -220,7 +220,7 @@ #define EXIT_TO_USERMODE_LOOP_FLAGS \ (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_UPROBE | \ - _TIF_NEED_RESCHED | _TIF_USER_RETURN_NOTIFY) + _TIF_NEED_RESCHED_MASK | _TIF_USER_RETURN_NOTIFY) static void exit_to_usermode_loop(struct pt_regs *regs, u32 cached_flags) { @@ -236,9 +236,16 @@ /* We have work to do. */ local_irq_enable(); - if (cached_flags & _TIF_NEED_RESCHED) + if (cached_flags & _TIF_NEED_RESCHED_MASK) schedule(); +#ifdef ARCH_RT_DELAYS_SIGNAL_SEND + if (unlikely(current->forced_info.si_signo)) { + struct task_struct *t = current; + force_sig_info(t->forced_info.si_signo, &t->forced_info, t); + t->forced_info.si_signo = 0; + } +#endif if (cached_flags & _TIF_UPROBE) uprobe_notify_resume(regs); diff -Naur --no-dereference a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S --- a/arch/x86/entry/entry_32.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/entry/entry_32.S 2016-05-11 13:31:53.197225234 -0400 @@ -278,8 +278,24 @@ ENTRY(resume_kernel) DISABLE_INTERRUPTS(CLBR_ANY) need_resched: + # preempt count == 0 + NEED_RS set? cmpl $0, PER_CPU_VAR(__preempt_count) +#ifndef CONFIG_PREEMPT_LAZY jnz restore_all +#else + jz test_int_off + + # atleast preempt count == 0 ? + cmpl $_PREEMPT_ENABLED,PER_CPU_VAR(__preempt_count) + jne restore_all + + cmpl $0,TI_preempt_lazy_count(%ebp) # non-zero preempt_lazy_count ? + jnz restore_all + + testl $_TIF_NEED_RESCHED_LAZY, TI_flags(%ebp) + jz restore_all +test_int_off: +#endif testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? jz restore_all call preempt_schedule_irq diff -Naur --no-dereference a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S --- a/arch/x86/entry/entry_64.S 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/entry/entry_64.S 2016-05-11 13:31:53.197225234 -0400 @@ -579,7 +579,23 @@ bt $9, EFLAGS(%rsp) /* were interrupts off? */ jnc 1f 0: cmpl $0, PER_CPU_VAR(__preempt_count) +#ifndef CONFIG_PREEMPT_LAZY jnz 1f +#else + jz do_preempt_schedule_irq + + # atleast preempt count == 0 ? + cmpl $_PREEMPT_ENABLED,PER_CPU_VAR(__preempt_count) + jnz 1f + + GET_THREAD_INFO(%rcx) + cmpl $0, TI_preempt_lazy_count(%rcx) + jnz 1f + + bt $TIF_NEED_RESCHED_LAZY,TI_flags(%rcx) + jnc 1f +do_preempt_schedule_irq: +#endif call preempt_schedule_irq jmp 0b 1: @@ -867,6 +883,7 @@ jmp 2b .previous +#ifndef CONFIG_PREEMPT_RT_FULL /* Call softirq on interrupt stack. Interrupts are off. */ ENTRY(do_softirq_own_stack) pushq %rbp @@ -879,6 +896,7 @@ decl PER_CPU_VAR(irq_count) ret END(do_softirq_own_stack) +#endif #ifdef CONFIG_XEN idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 diff -Naur --no-dereference a/arch/x86/include/asm/preempt.h b/arch/x86/include/asm/preempt.h --- a/arch/x86/include/asm/preempt.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/preempt.h 2016-05-11 13:31:53.197225234 -0400 @@ -79,17 +79,33 @@ * a decrement which hits zero means we have no preempt_count and should * reschedule. */ -static __always_inline bool __preempt_count_dec_and_test(void) +static __always_inline bool ____preempt_count_dec_and_test(void) { GEN_UNARY_RMWcc("decl", __preempt_count, __percpu_arg(0), "e"); } +static __always_inline bool __preempt_count_dec_and_test(void) +{ + if (____preempt_count_dec_and_test()) + return true; +#ifdef CONFIG_PREEMPT_LAZY + return test_thread_flag(TIF_NEED_RESCHED_LAZY); +#else + return false; +#endif +} + /* * Returns true when we need to resched and can (barring IRQ state). */ static __always_inline bool should_resched(int preempt_offset) { +#ifdef CONFIG_PREEMPT_LAZY + return unlikely(raw_cpu_read_4(__preempt_count) == preempt_offset || + test_thread_flag(TIF_NEED_RESCHED_LAZY)); +#else return unlikely(raw_cpu_read_4(__preempt_count) == preempt_offset); +#endif } #ifdef CONFIG_PREEMPT diff -Naur --no-dereference a/arch/x86/include/asm/signal.h b/arch/x86/include/asm/signal.h --- a/arch/x86/include/asm/signal.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/signal.h 2016-05-11 13:31:53.197225234 -0400 @@ -23,6 +23,19 @@ unsigned long sig[_NSIG_WORDS]; } sigset_t; +/* + * Because some traps use the IST stack, we must keep preemption + * disabled while calling do_trap(), but do_trap() may call + * force_sig_info() which will grab the signal spin_locks for the + * task, which in PREEMPT_RT_FULL are mutexes. By defining + * ARCH_RT_DELAYS_SIGNAL_SEND the force_sig_info() will set + * TIF_NOTIFY_RESUME and set up the signal to be sent on exit of the + * trap. + */ +#if defined(CONFIG_PREEMPT_RT_FULL) +#define ARCH_RT_DELAYS_SIGNAL_SEND +#endif + #ifndef CONFIG_COMPAT typedef sigset_t compat_sigset_t; #endif diff -Naur --no-dereference a/arch/x86/include/asm/stackprotector.h b/arch/x86/include/asm/stackprotector.h --- a/arch/x86/include/asm/stackprotector.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/stackprotector.h 2016-05-11 13:31:53.197225234 -0400 @@ -59,7 +59,7 @@ */ static __always_inline void boot_init_stack_canary(void) { - u64 canary; + u64 uninitialized_var(canary); u64 tsc; #ifdef CONFIG_X86_64 @@ -70,8 +70,15 @@ * of randomness. The TSC only matters for very early init, * there it already has some randomness on most systems. Later * on during the bootup the random pool has true entropy too. + * + * For preempt-rt we need to weaken the randomness a bit, as + * we can't call into the random generator from atomic context + * due to locking constraints. We just leave canary + * uninitialized and use the TSC based randomness on top of it. */ +#ifndef CONFIG_PREEMPT_RT_FULL get_random_bytes(&canary, sizeof(canary)); +#endif tsc = rdtsc(); canary += tsc + (tsc << 32UL); diff -Naur --no-dereference a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h --- a/arch/x86/include/asm/thread_info.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/thread_info.h 2016-05-11 13:31:53.197225234 -0400 @@ -58,6 +58,8 @@ __u32 status; /* thread synchronous flags */ __u32 cpu; /* current CPU */ mm_segment_t addr_limit; + int preempt_lazy_count; /* 0 => lazy preemptable + <0 => BUG */ unsigned int sig_on_uaccess_error:1; unsigned int uaccess_err:1; /* uaccess failed */ }; @@ -95,6 +97,7 @@ #define TIF_SYSCALL_EMU 6 /* syscall emulation active */ #define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */ #define TIF_SECCOMP 8 /* secure computing */ +#define TIF_NEED_RESCHED_LAZY 9 /* lazy rescheduling necessary */ #define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */ #define TIF_UPROBE 12 /* breakpointed or singlestepping */ #define TIF_NOTSC 16 /* TSC is not accessible in userland */ @@ -119,6 +122,7 @@ #define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU) #define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT) #define _TIF_SECCOMP (1 << TIF_SECCOMP) +#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY) #define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY) #define _TIF_UPROBE (1 << TIF_UPROBE) #define _TIF_NOTSC (1 << TIF_NOTSC) @@ -152,6 +156,8 @@ #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY) #define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW) +#define _TIF_NEED_RESCHED_MASK (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY) + #define STACK_WARN (THREAD_SIZE/8) /* diff -Naur --no-dereference a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h --- a/arch/x86/include/asm/uv/uv_bau.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/uv/uv_bau.h 2016-05-11 13:31:53.197225234 -0400 @@ -615,9 +615,9 @@ cycles_t send_message; cycles_t period_end; cycles_t period_time; - spinlock_t uvhub_lock; - spinlock_t queue_lock; - spinlock_t disable_lock; + raw_spinlock_t uvhub_lock; + raw_spinlock_t queue_lock; + raw_spinlock_t disable_lock; /* tunables */ int max_concurr; int max_concurr_const; @@ -776,15 +776,15 @@ * to be lowered below the current 'v'. atomic_add_unless can only stop * on equal. */ -static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u) +static inline int atomic_inc_unless_ge(raw_spinlock_t *lock, atomic_t *v, int u) { - spin_lock(lock); + raw_spin_lock(lock); if (atomic_read(v) >= u) { - spin_unlock(lock); + raw_spin_unlock(lock); return 0; } atomic_inc(v); - spin_unlock(lock); + raw_spin_unlock(lock); return 1; } diff -Naur --no-dereference a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h --- a/arch/x86/include/asm/uv/uv_hub.h 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/include/asm/uv/uv_hub.h 2016-05-11 13:31:53.197225234 -0400 @@ -492,7 +492,7 @@ unsigned short nr_online_cpus; unsigned short pnode; short memory_nid; - spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */ + raw_spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */ unsigned long nmi_count; /* obsolete, see uv_hub_nmi */ }; extern struct uv_blade_info *uv_blade_info; diff -Naur --no-dereference a/arch/x86/Kconfig b/arch/x86/Kconfig --- a/arch/x86/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/Kconfig 2016-05-11 13:31:53.193225201 -0400 @@ -17,6 +17,7 @@ ### Arch settings config X86 def_bool y + select HAVE_PREEMPT_LAZY select ACPI_LEGACY_TABLES_LOOKUP if ACPI select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI select ANON_INODES @@ -212,8 +213,11 @@ def_bool y depends on ISA_DMA_API +config RWSEM_GENERIC_SPINLOCK + def_bool PREEMPT_RT_FULL + config RWSEM_XCHGADD_ALGORITHM - def_bool y + def_bool !RWSEM_GENERIC_SPINLOCK && !PREEMPT_RT_FULL config GENERIC_CALIBRATE_DELAY def_bool y @@ -848,7 +852,7 @@ config MAXSMP bool "Enable Maximum number of SMP Processors and NUMA Nodes" depends on X86_64 && SMP && DEBUG_KERNEL - select CPUMASK_OFFSTACK + select CPUMASK_OFFSTACK if !PREEMPT_RT_FULL ---help--- Enable maximum number of CPUS and NUMA Nodes for this architecture. If unsure, say N. diff -Naur --no-dereference a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c --- a/arch/x86/kernel/apic/io_apic.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/apic/io_apic.c 2016-05-11 13:31:53.197225234 -0400 @@ -1711,7 +1711,8 @@ static inline bool ioapic_irqd_mask(struct irq_data *data) { /* If we are moving the irq we need to mask it */ - if (unlikely(irqd_is_setaffinity_pending(data))) { + if (unlikely(irqd_is_setaffinity_pending(data) && + !irqd_irq_inprogress(data))) { mask_ioapic_irq(data); return true; } diff -Naur --no-dereference a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c --- a/arch/x86/kernel/apic/x2apic_uv_x.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/apic/x2apic_uv_x.c 2016-05-11 13:31:53.197225234 -0400 @@ -947,7 +947,7 @@ uv_blade_info[blade].pnode = pnode; uv_blade_info[blade].nr_possible_cpus = 0; uv_blade_info[blade].nr_online_cpus = 0; - spin_lock_init(&uv_blade_info[blade].nmi_lock); + raw_spin_lock_init(&uv_blade_info[blade].nmi_lock); min_pnode = min(pnode, min_pnode); max_pnode = max(pnode, max_pnode); blade++; diff -Naur --no-dereference a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c --- a/arch/x86/kernel/asm-offsets.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/asm-offsets.c 2016-05-11 13:31:53.197225234 -0400 @@ -32,6 +32,7 @@ OFFSET(TI_flags, thread_info, flags); OFFSET(TI_status, thread_info, status); OFFSET(TI_addr_limit, thread_info, addr_limit); + OFFSET(TI_preempt_lazy_count, thread_info, preempt_lazy_count); BLANK(); OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx); @@ -89,4 +90,5 @@ BLANK(); DEFINE(PTREGS_SIZE, sizeof(struct pt_regs)); + DEFINE(_PREEMPT_ENABLED, PREEMPT_ENABLED); } diff -Naur --no-dereference a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c --- a/arch/x86/kernel/cpu/mcheck/mce.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/cpu/mcheck/mce.c 2016-05-11 13:31:53.197225234 -0400 @@ -41,6 +41,8 @@ #include #include #include +#include +#include #include #include @@ -1236,7 +1238,7 @@ static unsigned long check_interval = INITIAL_CHECK_INTERVAL; static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ -static DEFINE_PER_CPU(struct timer_list, mce_timer); +static DEFINE_PER_CPU(struct hrtimer, mce_timer); static unsigned long mce_adjust_timer_default(unsigned long interval) { @@ -1245,32 +1247,18 @@ static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; -static void __restart_timer(struct timer_list *t, unsigned long interval) +static enum hrtimer_restart __restart_timer(struct hrtimer *timer, unsigned long interval) { - unsigned long when = jiffies + interval; - unsigned long flags; - - local_irq_save(flags); - - if (timer_pending(t)) { - if (time_before(when, t->expires)) - mod_timer_pinned(t, when); - } else { - t->expires = round_jiffies(when); - add_timer_on(t, smp_processor_id()); - } - - local_irq_restore(flags); + if (!interval) + return HRTIMER_NORESTART; + hrtimer_forward_now(timer, ns_to_ktime(jiffies_to_nsecs(interval))); + return HRTIMER_RESTART; } -static void mce_timer_fn(unsigned long data) +static enum hrtimer_restart mce_timer_fn(struct hrtimer *timer) { - struct timer_list *t = this_cpu_ptr(&mce_timer); - int cpu = smp_processor_id(); unsigned long iv; - WARN_ON(cpu != data); - iv = __this_cpu_read(mce_next_interval); if (mce_available(this_cpu_ptr(&cpu_info))) { @@ -1293,7 +1281,7 @@ done: __this_cpu_write(mce_next_interval, iv); - __restart_timer(t, iv); + return __restart_timer(timer, iv); } /* @@ -1301,7 +1289,7 @@ */ void mce_timer_kick(unsigned long interval) { - struct timer_list *t = this_cpu_ptr(&mce_timer); + struct hrtimer *t = this_cpu_ptr(&mce_timer); unsigned long iv = __this_cpu_read(mce_next_interval); __restart_timer(t, interval); @@ -1316,7 +1304,7 @@ int cpu; for_each_online_cpu(cpu) - del_timer_sync(&per_cpu(mce_timer, cpu)); + hrtimer_cancel(&per_cpu(mce_timer, cpu)); } static void mce_do_trigger(struct work_struct *work) @@ -1326,6 +1314,56 @@ static DECLARE_WORK(mce_trigger_work, mce_do_trigger); +static void __mce_notify_work(struct swork_event *event) +{ + /* Not more than two messages every minute */ + static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); + + /* wake processes polling /dev/mcelog */ + wake_up_interruptible(&mce_chrdev_wait); + + /* + * There is no risk of missing notifications because + * work_pending is always cleared before the function is + * executed. + */ + if (mce_helper[0] && !work_pending(&mce_trigger_work)) + schedule_work(&mce_trigger_work); + + if (__ratelimit(&ratelimit)) + pr_info(HW_ERR "Machine check events logged\n"); +} + +#ifdef CONFIG_PREEMPT_RT_FULL +static bool notify_work_ready __read_mostly; +static struct swork_event notify_work; + +static int mce_notify_work_init(void) +{ + int err; + + err = swork_get(); + if (err) + return err; + + INIT_SWORK(¬ify_work, __mce_notify_work); + notify_work_ready = true; + return 0; +} + +static void mce_notify_work(void) +{ + if (notify_work_ready) + swork_queue(¬ify_work); +} +#else +static void mce_notify_work(void) +{ + __mce_notify_work(NULL); +} +static inline int mce_notify_work_init(void) { return 0; } +#endif + /* * Notify the user(s) about new machine check events. * Can be called from interrupt context, but not from machine check/NMI @@ -1333,19 +1371,8 @@ */ int mce_notify_irq(void) { - /* Not more than two messages every minute */ - static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); - if (test_and_clear_bit(0, &mce_need_notify)) { - /* wake processes polling /dev/mcelog */ - wake_up_interruptible(&mce_chrdev_wait); - - if (mce_helper[0]) - schedule_work(&mce_trigger_work); - - if (__ratelimit(&ratelimit)) - pr_info(HW_ERR "Machine check events logged\n"); - + mce_notify_work(); return 1; } return 0; @@ -1639,7 +1666,7 @@ } } -static void mce_start_timer(unsigned int cpu, struct timer_list *t) +static void mce_start_timer(unsigned int cpu, struct hrtimer *t) { unsigned long iv = check_interval * HZ; @@ -1648,16 +1675,17 @@ per_cpu(mce_next_interval, cpu) = iv; - t->expires = round_jiffies(jiffies + iv); - add_timer_on(t, cpu); + hrtimer_start_range_ns(t, ns_to_ktime(jiffies_to_usecs(iv) * 1000ULL), + 0, HRTIMER_MODE_REL_PINNED); } static void __mcheck_cpu_init_timer(void) { - struct timer_list *t = this_cpu_ptr(&mce_timer); + struct hrtimer *t = this_cpu_ptr(&mce_timer); unsigned int cpu = smp_processor_id(); - setup_timer(t, mce_timer_fn, cpu); + hrtimer_init(t, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + t->function = mce_timer_fn; mce_start_timer(cpu, t); } @@ -2376,6 +2404,8 @@ if (!mce_available(raw_cpu_ptr(&cpu_info))) return; + hrtimer_cancel(this_cpu_ptr(&mce_timer)); + if (!(action & CPU_TASKS_FROZEN)) cmci_clear(); @@ -2398,6 +2428,7 @@ if (b->init) wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); } + __mcheck_cpu_init_timer(); } /* Get notified when a cpu comes on/off. Be hotplug friendly. */ @@ -2405,7 +2436,6 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; - struct timer_list *t = &per_cpu(mce_timer, cpu); switch (action & ~CPU_TASKS_FROZEN) { case CPU_ONLINE: @@ -2425,11 +2455,9 @@ break; case CPU_DOWN_PREPARE: smp_call_function_single(cpu, mce_disable_cpu, &action, 1); - del_timer_sync(t); break; case CPU_DOWN_FAILED: smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); - mce_start_timer(cpu, t); break; } @@ -2468,6 +2496,10 @@ goto err_out; } + err = mce_notify_work_init(); + if (err) + goto err_out; + if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { err = -ENOMEM; goto err_out; diff -Naur --no-dereference a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c --- a/arch/x86/kernel/dumpstack_32.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/dumpstack_32.c 2016-05-11 13:31:53.197225234 -0400 @@ -42,7 +42,7 @@ unsigned long *stack, unsigned long bp, const struct stacktrace_ops *ops, void *data) { - const unsigned cpu = get_cpu(); + const unsigned cpu = get_cpu_light(); int graph = 0; u32 *prev_esp; @@ -86,7 +86,7 @@ break; touch_nmi_watchdog(); } - put_cpu(); + put_cpu_light(); } EXPORT_SYMBOL(dump_trace); diff -Naur --no-dereference a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c --- a/arch/x86/kernel/dumpstack_64.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/dumpstack_64.c 2016-05-11 13:31:53.197225234 -0400 @@ -152,7 +152,7 @@ unsigned long *stack, unsigned long bp, const struct stacktrace_ops *ops, void *data) { - const unsigned cpu = get_cpu(); + const unsigned cpu = get_cpu_light(); struct thread_info *tinfo; unsigned long *irq_stack = (unsigned long *)per_cpu(irq_stack_ptr, cpu); unsigned long dummy; @@ -241,7 +241,7 @@ * This handles the process stack: */ bp = ops->walk_stack(tinfo, stack, bp, ops, data, NULL, &graph); - put_cpu(); + put_cpu_light(); } EXPORT_SYMBOL(dump_trace); @@ -255,7 +255,7 @@ int cpu; int i; - preempt_disable(); + migrate_disable(); cpu = smp_processor_id(); irq_stack_end = (unsigned long *)(per_cpu(irq_stack_ptr, cpu)); @@ -291,7 +291,7 @@ pr_cont(" %016lx", *stack++); touch_nmi_watchdog(); } - preempt_enable(); + migrate_enable(); pr_cont("\n"); show_trace_log_lvl(task, regs, sp, bp, log_lvl); diff -Naur --no-dereference a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c --- a/arch/x86/kernel/irq_32.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/irq_32.c 2016-05-11 13:31:53.197225234 -0400 @@ -128,6 +128,7 @@ cpu, per_cpu(hardirq_stack, cpu), per_cpu(softirq_stack, cpu)); } +#ifndef CONFIG_PREEMPT_RT_FULL void do_softirq_own_stack(void) { struct thread_info *curstk; @@ -146,6 +147,7 @@ call_on_stack(__do_softirq, isp); } +#endif bool handle_irq(struct irq_desc *desc, struct pt_regs *regs) { diff -Naur --no-dereference a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c --- a/arch/x86/kernel/kvm.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/kvm.c 2016-05-11 13:31:53.197225234 -0400 @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -91,14 +92,14 @@ struct kvm_task_sleep_node { struct hlist_node link; - wait_queue_head_t wq; + struct swait_queue_head wq; u32 token; int cpu; bool halted; }; static struct kvm_task_sleep_head { - spinlock_t lock; + raw_spinlock_t lock; struct hlist_head list; } async_pf_sleepers[KVM_TASK_SLEEP_HASHSIZE]; @@ -122,17 +123,17 @@ u32 key = hash_32(token, KVM_TASK_SLEEP_HASHBITS); struct kvm_task_sleep_head *b = &async_pf_sleepers[key]; struct kvm_task_sleep_node n, *e; - DEFINE_WAIT(wait); + DECLARE_SWAITQUEUE(wait); rcu_irq_enter(); - spin_lock(&b->lock); + raw_spin_lock(&b->lock); e = _find_apf_task(b, token); if (e) { /* dummy entry exist -> wake up was delivered ahead of PF */ hlist_del(&e->link); kfree(e); - spin_unlock(&b->lock); + raw_spin_unlock(&b->lock); rcu_irq_exit(); return; @@ -141,13 +142,13 @@ n.token = token; n.cpu = smp_processor_id(); n.halted = is_idle_task(current) || preempt_count() > 1; - init_waitqueue_head(&n.wq); + init_swait_queue_head(&n.wq); hlist_add_head(&n.link, &b->list); - spin_unlock(&b->lock); + raw_spin_unlock(&b->lock); for (;;) { if (!n.halted) - prepare_to_wait(&n.wq, &wait, TASK_UNINTERRUPTIBLE); + prepare_to_swait(&n.wq, &wait, TASK_UNINTERRUPTIBLE); if (hlist_unhashed(&n.link)) break; @@ -166,7 +167,7 @@ } } if (!n.halted) - finish_wait(&n.wq, &wait); + finish_swait(&n.wq, &wait); rcu_irq_exit(); return; @@ -178,8 +179,8 @@ hlist_del_init(&n->link); if (n->halted) smp_send_reschedule(n->cpu); - else if (waitqueue_active(&n->wq)) - wake_up(&n->wq); + else if (swait_active(&n->wq)) + swake_up(&n->wq); } static void apf_task_wake_all(void) @@ -189,14 +190,14 @@ for (i = 0; i < KVM_TASK_SLEEP_HASHSIZE; i++) { struct hlist_node *p, *next; struct kvm_task_sleep_head *b = &async_pf_sleepers[i]; - spin_lock(&b->lock); + raw_spin_lock(&b->lock); hlist_for_each_safe(p, next, &b->list) { struct kvm_task_sleep_node *n = hlist_entry(p, typeof(*n), link); if (n->cpu == smp_processor_id()) apf_task_wake_one(n); } - spin_unlock(&b->lock); + raw_spin_unlock(&b->lock); } } @@ -212,7 +213,7 @@ } again: - spin_lock(&b->lock); + raw_spin_lock(&b->lock); n = _find_apf_task(b, token); if (!n) { /* @@ -225,17 +226,17 @@ * Allocation failed! Busy wait while other cpu * handles async PF. */ - spin_unlock(&b->lock); + raw_spin_unlock(&b->lock); cpu_relax(); goto again; } n->token = token; n->cpu = smp_processor_id(); - init_waitqueue_head(&n->wq); + init_swait_queue_head(&n->wq); hlist_add_head(&n->link, &b->list); } else apf_task_wake_one(n); - spin_unlock(&b->lock); + raw_spin_unlock(&b->lock); return; } EXPORT_SYMBOL_GPL(kvm_async_pf_task_wake); @@ -486,7 +487,7 @@ paravirt_ops_setup(); register_reboot_notifier(&kvm_pv_reboot_nb); for (i = 0; i < KVM_TASK_SLEEP_HASHSIZE; i++) - spin_lock_init(&async_pf_sleepers[i].lock); + raw_spin_lock_init(&async_pf_sleepers[i].lock); if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF)) x86_init.irqs.trap_init = kvm_apf_trap_init; diff -Naur --no-dereference a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c --- a/arch/x86/kernel/nmi.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/nmi.c 2016-05-11 13:31:53.197225234 -0400 @@ -231,7 +231,7 @@ #endif if (panic_on_unrecovered_nmi) - panic("NMI: Not continuing"); + nmi_panic(regs, "NMI: Not continuing"); pr_emerg("Dazed and confused, but trying to continue\n"); @@ -255,8 +255,16 @@ reason, smp_processor_id()); show_regs(regs); - if (panic_on_io_nmi) - panic("NMI IOCK error: Not continuing"); + if (panic_on_io_nmi) { + nmi_panic(regs, "NMI IOCK error: Not continuing"); + + /* + * If we end up here, it means we have received an NMI while + * processing panic(). Simply return without delaying and + * re-enabling NMIs. + */ + return; + } /* Re-enable the IOCK line, wait for a few seconds */ reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK; @@ -297,7 +305,7 @@ pr_emerg("Do you have a strange power saving mode enabled?\n"); if (unknown_nmi_panic || panic_on_unrecovered_nmi) - panic("NMI: Not continuing"); + nmi_panic(regs, "NMI: Not continuing"); pr_emerg("Dazed and confused, but trying to continue\n"); } diff -Naur --no-dereference a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c --- a/arch/x86/kernel/process_32.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/process_32.c 2016-05-11 13:31:53.197225234 -0400 @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -210,6 +211,35 @@ } EXPORT_SYMBOL_GPL(start_thread); +#ifdef CONFIG_PREEMPT_RT_FULL +static void switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p) +{ + int i; + + /* + * Clear @prev's kmap_atomic mappings + */ + for (i = 0; i < prev_p->kmap_idx; i++) { + int idx = i + KM_TYPE_NR * smp_processor_id(); + pte_t *ptep = kmap_pte - idx; + + kpte_clear_flush(ptep, __fix_to_virt(FIX_KMAP_BEGIN + idx)); + } + /* + * Restore @next_p's kmap_atomic mappings + */ + for (i = 0; i < next_p->kmap_idx; i++) { + int idx = i + KM_TYPE_NR * smp_processor_id(); + + if (!pte_none(next_p->kmap_pte[i])) + set_pte(kmap_pte - idx, next_p->kmap_pte[i]); + } +} +#else +static inline void +switch_kmaps(struct task_struct *prev_p, struct task_struct *next_p) { } +#endif + /* * switch_to(x,y) should switch tasks from x to y. @@ -286,6 +316,8 @@ task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT)) __switch_to_xtra(prev_p, next_p, tss); + switch_kmaps(prev_p, next_p); + /* * Leave lazy mode, flushing any hypercalls made here. * This must be done before restoring TLS segments so diff -Naur --no-dereference a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c --- a/arch/x86/kernel/reboot.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kernel/reboot.c 2016-05-11 13:31:53.197225234 -0400 @@ -726,6 +726,7 @@ static nmi_shootdown_cb shootdown_callback; static atomic_t waiting_for_crash_ipi; +static int crash_ipi_issued; static int crash_nmi_callback(unsigned int val, struct pt_regs *regs) { @@ -788,6 +789,9 @@ smp_send_nmi_allbutself(); + /* Kick CPUs looping in NMI context. */ + WRITE_ONCE(crash_ipi_issued, 1); + msecs = 1000; /* Wait at most a second for the other cpus to stop */ while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) { mdelay(1); @@ -796,6 +800,22 @@ /* Leave the nmi callback set */ } + +/* Override the weak function in kernel/panic.c */ +void nmi_panic_self_stop(struct pt_regs *regs) +{ + while (1) { + /* + * Wait for the crash dumping IPI to be issued, and then + * call its callback directly. + */ + if (READ_ONCE(crash_ipi_issued)) + crash_nmi_callback(0, regs); /* Don't return */ + + cpu_relax(); + } +} + #else /* !CONFIG_SMP */ void nmi_shootdown_cpus(nmi_shootdown_cb callback) { diff -Naur --no-dereference a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c --- a/arch/x86/kvm/lapic.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kvm/lapic.c 2016-05-11 13:31:53.197225234 -0400 @@ -1195,7 +1195,7 @@ static void apic_timer_expired(struct kvm_lapic *apic) { struct kvm_vcpu *vcpu = apic->vcpu; - wait_queue_head_t *q = &vcpu->wq; + struct swait_queue_head *q = &vcpu->wq; struct kvm_timer *ktimer = &apic->lapic_timer; if (atomic_read(&apic->lapic_timer.pending)) @@ -1204,8 +1204,8 @@ atomic_inc(&apic->lapic_timer.pending); kvm_set_pending_timer(vcpu); - if (waitqueue_active(q)) - wake_up_interruptible(q); + if (swait_active(q)) + swake_up(q); if (apic_lvtt_tscdeadline(apic)) ktimer->expired_tscdeadline = ktimer->tscdeadline; @@ -1801,6 +1801,7 @@ hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); apic->lapic_timer.timer.function = apic_timer_fn; + apic->lapic_timer.timer.irqsafe = 1; /* * APIC is created enabled. This will prevent kvm_lapic_set_base from diff -Naur --no-dereference a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c --- a/arch/x86/kvm/x86.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/kvm/x86.c 2016-05-11 13:31:53.197225234 -0400 @@ -5788,6 +5788,13 @@ goto out; } +#ifdef CONFIG_PREEMPT_RT_FULL + if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { + printk(KERN_ERR "RT requires X86_FEATURE_CONSTANT_TSC\n"); + return -EOPNOTSUPP; + } +#endif + r = kvm_mmu_module_init(); if (r) goto out_free_percpu; diff -Naur --no-dereference a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c --- a/arch/x86/mm/highmem_32.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/mm/highmem_32.c 2016-05-11 13:31:53.197225234 -0400 @@ -32,10 +32,11 @@ */ void *kmap_atomic_prot(struct page *page, pgprot_t prot) { + pte_t pte = mk_pte(page, prot); unsigned long vaddr; int idx, type; - preempt_disable(); + preempt_disable_nort(); pagefault_disable(); if (!PageHighMem(page)) @@ -45,7 +46,10 @@ idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); BUG_ON(!pte_none(*(kmap_pte-idx))); - set_pte(kmap_pte-idx, mk_pte(page, prot)); +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = pte; +#endif + set_pte(kmap_pte-idx, pte); arch_flush_lazy_mmu_mode(); return (void *)vaddr; @@ -88,6 +92,9 @@ * is a bad idea also, in case the page changes cacheability * attributes or becomes a protected page in a hypervisor. */ +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = __pte(0); +#endif kpte_clear_flush(kmap_pte-idx, vaddr); kmap_atomic_idx_pop(); arch_flush_lazy_mmu_mode(); @@ -100,7 +107,7 @@ #endif pagefault_enable(); - preempt_enable(); + preempt_enable_nort(); } EXPORT_SYMBOL(__kunmap_atomic); diff -Naur --no-dereference a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c --- a/arch/x86/mm/iomap_32.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/mm/iomap_32.c 2016-05-11 13:31:53.197225234 -0400 @@ -56,6 +56,7 @@ void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot) { + pte_t pte = pfn_pte(pfn, prot); unsigned long vaddr; int idx, type; @@ -65,7 +66,12 @@ type = kmap_atomic_idx_push(); idx = type + KM_TYPE_NR * smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); - set_pte(kmap_pte - idx, pfn_pte(pfn, prot)); + WARN_ON(!pte_none(*(kmap_pte - idx))); + +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = pte; +#endif + set_pte(kmap_pte - idx, pte); arch_flush_lazy_mmu_mode(); return (void *)vaddr; @@ -113,6 +119,9 @@ * is a bad idea also, in case the page changes cacheability * attributes or becomes a protected page in a hypervisor. */ +#ifdef CONFIG_PREEMPT_RT_FULL + current->kmap_pte[type] = __pte(0); +#endif kpte_clear_flush(kmap_pte-idx, vaddr); kmap_atomic_idx_pop(); } diff -Naur --no-dereference a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c --- a/arch/x86/platform/uv/tlb_uv.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/platform/uv/tlb_uv.c 2016-05-11 13:31:53.197225234 -0400 @@ -714,9 +714,9 @@ quiesce_local_uvhub(hmaster); - spin_lock(&hmaster->queue_lock); + raw_spin_lock(&hmaster->queue_lock); reset_with_ipi(&bau_desc->distribution, bcp); - spin_unlock(&hmaster->queue_lock); + raw_spin_unlock(&hmaster->queue_lock); end_uvhub_quiesce(hmaster); @@ -736,9 +736,9 @@ quiesce_local_uvhub(hmaster); - spin_lock(&hmaster->queue_lock); + raw_spin_lock(&hmaster->queue_lock); reset_with_ipi(&bau_desc->distribution, bcp); - spin_unlock(&hmaster->queue_lock); + raw_spin_unlock(&hmaster->queue_lock); end_uvhub_quiesce(hmaster); @@ -759,7 +759,7 @@ cycles_t tm1; hmaster = bcp->uvhub_master; - spin_lock(&hmaster->disable_lock); + raw_spin_lock(&hmaster->disable_lock); if (!bcp->baudisabled) { stat->s_bau_disabled++; tm1 = get_cycles(); @@ -772,7 +772,7 @@ } } } - spin_unlock(&hmaster->disable_lock); + raw_spin_unlock(&hmaster->disable_lock); } static void count_max_concurr(int stat, struct bau_control *bcp, @@ -835,7 +835,7 @@ */ static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) { - spinlock_t *lock = &hmaster->uvhub_lock; + raw_spinlock_t *lock = &hmaster->uvhub_lock; atomic_t *v; v = &hmaster->active_descriptor_count; @@ -968,7 +968,7 @@ struct bau_control *hmaster; hmaster = bcp->uvhub_master; - spin_lock(&hmaster->disable_lock); + raw_spin_lock(&hmaster->disable_lock); if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) { stat->s_bau_reenabled++; for_each_present_cpu(tcpu) { @@ -980,10 +980,10 @@ tbcp->period_giveups = 0; } } - spin_unlock(&hmaster->disable_lock); + raw_spin_unlock(&hmaster->disable_lock); return 0; } - spin_unlock(&hmaster->disable_lock); + raw_spin_unlock(&hmaster->disable_lock); return -1; } @@ -1901,9 +1901,9 @@ bcp->cong_reps = congested_reps; bcp->disabled_period = sec_2_cycles(disabled_period); bcp->giveup_limit = giveup_limit; - spin_lock_init(&bcp->queue_lock); - spin_lock_init(&bcp->uvhub_lock); - spin_lock_init(&bcp->disable_lock); + raw_spin_lock_init(&bcp->queue_lock); + raw_spin_lock_init(&bcp->uvhub_lock); + raw_spin_lock_init(&bcp->disable_lock); } } diff -Naur --no-dereference a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c --- a/arch/x86/platform/uv/uv_time.c 2016-05-04 17:50:15.000000000 -0400 +++ b/arch/x86/platform/uv/uv_time.c 2016-05-11 13:31:53.197225234 -0400 @@ -57,7 +57,7 @@ /* There is one of these allocated per node */ struct uv_rtc_timer_head { - spinlock_t lock; + raw_spinlock_t lock; /* next cpu waiting for timer, local node relative: */ int next_cpu; /* number of cpus on this node: */ @@ -177,7 +177,7 @@ uv_rtc_deallocate_timers(); return -ENOMEM; } - spin_lock_init(&head->lock); + raw_spin_lock_init(&head->lock); head->ncpus = uv_blade_nr_possible_cpus(bid); head->next_cpu = -1; blade_info[bid] = head; @@ -231,7 +231,7 @@ unsigned long flags; int next_cpu; - spin_lock_irqsave(&head->lock, flags); + raw_spin_lock_irqsave(&head->lock, flags); next_cpu = head->next_cpu; *t = expires; @@ -243,12 +243,12 @@ if (uv_setup_intr(cpu, expires)) { *t = ULLONG_MAX; uv_rtc_find_next_timer(head, pnode); - spin_unlock_irqrestore(&head->lock, flags); + raw_spin_unlock_irqrestore(&head->lock, flags); return -ETIME; } } - spin_unlock_irqrestore(&head->lock, flags); + raw_spin_unlock_irqrestore(&head->lock, flags); return 0; } @@ -267,7 +267,7 @@ unsigned long flags; int rc = 0; - spin_lock_irqsave(&head->lock, flags); + raw_spin_lock_irqsave(&head->lock, flags); if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force) rc = 1; @@ -279,7 +279,7 @@ uv_rtc_find_next_timer(head, pnode); } - spin_unlock_irqrestore(&head->lock, flags); + raw_spin_unlock_irqrestore(&head->lock, flags); return rc; } @@ -299,13 +299,18 @@ static cycle_t uv_read_rtc(struct clocksource *cs) { unsigned long offset; + cycle_t cycles; + preempt_disable(); if (uv_get_min_hub_revision_id() == 1) offset = 0; else offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE; - return (cycle_t)uv_read_local_mmr(UVH_RTC | offset); + cycles = (cycle_t)uv_read_local_mmr(UVH_RTC | offset); + preempt_enable(); + + return cycles; } /* diff -Naur --no-dereference a/block/blk-core.c b/block/blk-core.c --- a/block/blk-core.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-core.c 2016-05-11 13:31:53.197225234 -0400 @@ -125,6 +125,9 @@ INIT_LIST_HEAD(&rq->queuelist); INIT_LIST_HEAD(&rq->timeout_list); +#ifdef CONFIG_PREEMPT_RT_FULL + INIT_WORK(&rq->work, __blk_mq_complete_request_remote_work); +#endif rq->cpu = -1; rq->q = q; rq->__sector = (sector_t) -1; @@ -233,7 +236,7 @@ **/ void blk_start_queue(struct request_queue *q) { - WARN_ON(!irqs_disabled()); + WARN_ON_NONRT(!irqs_disabled()); queue_flag_clear(QUEUE_FLAG_STOPPED, q); __blk_run_queue(q); @@ -657,7 +660,7 @@ if (!gfpflags_allow_blocking(gfp)) return -EBUSY; - ret = wait_event_interruptible(q->mq_freeze_wq, + ret = swait_event_interruptible(q->mq_freeze_wq, !atomic_read(&q->mq_freeze_depth) || blk_queue_dying(q)); if (blk_queue_dying(q)) @@ -677,7 +680,7 @@ struct request_queue *q = container_of(ref, struct request_queue, q_usage_counter); - wake_up_all(&q->mq_freeze_wq); + swake_up_all(&q->mq_freeze_wq); } struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) @@ -739,7 +742,7 @@ q->bypass_depth = 1; __set_bit(QUEUE_FLAG_BYPASS, &q->queue_flags); - init_waitqueue_head(&q->mq_freeze_wq); + init_swait_queue_head(&q->mq_freeze_wq); /* * Init percpu_ref in atomic mode so that it's faster to shutdown. @@ -3198,7 +3201,7 @@ blk_run_queue_async(q); else __blk_run_queue(q); - spin_unlock(q->queue_lock); + spin_unlock_irq(q->queue_lock); } static void flush_plug_callbacks(struct blk_plug *plug, bool from_schedule) @@ -3246,7 +3249,6 @@ void blk_flush_plug_list(struct blk_plug *plug, bool from_schedule) { struct request_queue *q; - unsigned long flags; struct request *rq; LIST_HEAD(list); unsigned int depth; @@ -3266,11 +3268,6 @@ q = NULL; depth = 0; - /* - * Save and disable interrupts here, to avoid doing it for every - * queue lock we have to take. - */ - local_irq_save(flags); while (!list_empty(&list)) { rq = list_entry_rq(list.next); list_del_init(&rq->queuelist); @@ -3283,7 +3280,7 @@ queue_unplugged(q, depth, from_schedule); q = rq->q; depth = 0; - spin_lock(q->queue_lock); + spin_lock_irq(q->queue_lock); } /* @@ -3310,8 +3307,6 @@ */ if (q) queue_unplugged(q, depth, from_schedule); - - local_irq_restore(flags); } void blk_finish_plug(struct blk_plug *plug) diff -Naur --no-dereference a/block/blk-ioc.c b/block/blk-ioc.c --- a/block/blk-ioc.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-ioc.c 2016-05-11 13:31:53.197225234 -0400 @@ -7,6 +7,7 @@ #include #include #include +#include #include "blk.h" @@ -109,7 +110,7 @@ spin_unlock(q->queue_lock); } else { spin_unlock_irqrestore(&ioc->lock, flags); - cpu_relax(); + cpu_chill(); spin_lock_irqsave_nested(&ioc->lock, flags, 1); } } @@ -187,7 +188,7 @@ spin_unlock(icq->q->queue_lock); } else { spin_unlock_irqrestore(&ioc->lock, flags); - cpu_relax(); + cpu_chill(); goto retry; } } diff -Naur --no-dereference a/block/blk-iopoll.c b/block/blk-iopoll.c --- a/block/blk-iopoll.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-iopoll.c 2016-05-11 13:31:53.197225234 -0400 @@ -35,6 +35,7 @@ list_add_tail(&iop->list, this_cpu_ptr(&blk_cpu_iopoll)); __raise_softirq_irqoff(BLOCK_IOPOLL_SOFTIRQ); local_irq_restore(flags); + preempt_check_resched_rt(); } EXPORT_SYMBOL(blk_iopoll_sched); @@ -132,6 +133,7 @@ __raise_softirq_irqoff(BLOCK_IOPOLL_SOFTIRQ); local_irq_enable(); + preempt_check_resched_rt(); } /** @@ -201,6 +203,7 @@ this_cpu_ptr(&blk_cpu_iopoll)); __raise_softirq_irqoff(BLOCK_IOPOLL_SOFTIRQ); local_irq_enable(); + preempt_check_resched_rt(); } return NOTIFY_OK; diff -Naur --no-dereference a/block/blk-mq.c b/block/blk-mq.c --- a/block/blk-mq.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-mq.c 2016-05-11 13:31:53.197225234 -0400 @@ -92,7 +92,7 @@ static void blk_mq_freeze_queue_wait(struct request_queue *q) { - wait_event(q->mq_freeze_wq, percpu_ref_is_zero(&q->q_usage_counter)); + swait_event(q->mq_freeze_wq, percpu_ref_is_zero(&q->q_usage_counter)); } /* @@ -130,7 +130,7 @@ WARN_ON_ONCE(freeze_depth < 0); if (!freeze_depth) { percpu_ref_reinit(&q->q_usage_counter); - wake_up_all(&q->mq_freeze_wq); + swake_up_all(&q->mq_freeze_wq); } } EXPORT_SYMBOL_GPL(blk_mq_unfreeze_queue); @@ -149,7 +149,7 @@ * dying, we need to ensure that processes currently waiting on * the queue are notified as well. */ - wake_up_all(&q->mq_freeze_wq); + swake_up_all(&q->mq_freeze_wq); } bool blk_mq_can_queue(struct blk_mq_hw_ctx *hctx) @@ -196,6 +196,9 @@ rq->resid_len = 0; rq->sense = NULL; +#ifdef CONFIG_PREEMPT_RT_FULL + INIT_WORK(&rq->work, __blk_mq_complete_request_remote_work); +#endif INIT_LIST_HEAD(&rq->timeout_list); rq->timeout = 0; @@ -325,6 +328,17 @@ } EXPORT_SYMBOL(blk_mq_end_request); +#ifdef CONFIG_PREEMPT_RT_FULL + +void __blk_mq_complete_request_remote_work(struct work_struct *work) +{ + struct request *rq = container_of(work, struct request, work); + + rq->q->softirq_done_fn(rq); +} + +#else + static void __blk_mq_complete_request_remote(void *data) { struct request *rq = data; @@ -332,6 +346,8 @@ rq->q->softirq_done_fn(rq); } +#endif + static void blk_mq_ipi_complete_request(struct request *rq) { struct blk_mq_ctx *ctx = rq->mq_ctx; @@ -343,19 +359,23 @@ return; } - cpu = get_cpu(); + cpu = get_cpu_light(); if (!test_bit(QUEUE_FLAG_SAME_FORCE, &rq->q->queue_flags)) shared = cpus_share_cache(cpu, ctx->cpu); if (cpu != ctx->cpu && !shared && cpu_online(ctx->cpu)) { +#ifdef CONFIG_PREEMPT_RT_FULL + schedule_work_on(ctx->cpu, &rq->work); +#else rq->csd.func = __blk_mq_complete_request_remote; rq->csd.info = rq; rq->csd.flags = 0; smp_call_function_single_async(ctx->cpu, &rq->csd); +#endif } else { rq->q->softirq_done_fn(rq); } - put_cpu(); + put_cpu_light(); } static void __blk_mq_complete_request(struct request *rq) @@ -862,14 +882,14 @@ return; if (!async) { - int cpu = get_cpu(); + int cpu = get_cpu_light(); if (cpumask_test_cpu(cpu, hctx->cpumask)) { __blk_mq_run_hw_queue(hctx); - put_cpu(); + put_cpu_light(); return; } - put_cpu(); + put_cpu_light(); } kblockd_schedule_delayed_work_on(blk_mq_hctx_next_cpu(hctx), @@ -1617,7 +1637,7 @@ { struct blk_mq_hw_ctx *hctx = data; - if (action == CPU_DEAD || action == CPU_DEAD_FROZEN) + if (action == CPU_POST_DEAD) return blk_mq_hctx_cpu_offline(hctx, cpu); /* diff -Naur --no-dereference a/block/blk-mq-cpu.c b/block/blk-mq-cpu.c --- a/block/blk-mq-cpu.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-mq-cpu.c 2016-05-11 13:31:53.197225234 -0400 @@ -16,7 +16,7 @@ #include "blk-mq.h" static LIST_HEAD(blk_mq_cpu_notify_list); -static DEFINE_RAW_SPINLOCK(blk_mq_cpu_notify_lock); +static DEFINE_SPINLOCK(blk_mq_cpu_notify_lock); static int blk_mq_main_cpu_notify(struct notifier_block *self, unsigned long action, void *hcpu) @@ -25,7 +25,10 @@ struct blk_mq_cpu_notifier *notify; int ret = NOTIFY_OK; - raw_spin_lock(&blk_mq_cpu_notify_lock); + if (action != CPU_POST_DEAD) + return NOTIFY_OK; + + spin_lock(&blk_mq_cpu_notify_lock); list_for_each_entry(notify, &blk_mq_cpu_notify_list, list) { ret = notify->notify(notify->data, action, cpu); @@ -33,7 +36,7 @@ break; } - raw_spin_unlock(&blk_mq_cpu_notify_lock); + spin_unlock(&blk_mq_cpu_notify_lock); return ret; } @@ -41,16 +44,16 @@ { BUG_ON(!notifier->notify); - raw_spin_lock(&blk_mq_cpu_notify_lock); + spin_lock(&blk_mq_cpu_notify_lock); list_add_tail(¬ifier->list, &blk_mq_cpu_notify_list); - raw_spin_unlock(&blk_mq_cpu_notify_lock); + spin_unlock(&blk_mq_cpu_notify_lock); } void blk_mq_unregister_cpu_notifier(struct blk_mq_cpu_notifier *notifier) { - raw_spin_lock(&blk_mq_cpu_notify_lock); + spin_lock(&blk_mq_cpu_notify_lock); list_del(¬ifier->list); - raw_spin_unlock(&blk_mq_cpu_notify_lock); + spin_unlock(&blk_mq_cpu_notify_lock); } void blk_mq_init_cpu_notifier(struct blk_mq_cpu_notifier *notifier, diff -Naur --no-dereference a/block/blk-mq.h b/block/blk-mq.h --- a/block/blk-mq.h 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-mq.h 2016-05-11 13:31:53.197225234 -0400 @@ -74,7 +74,10 @@ static inline struct blk_mq_ctx *__blk_mq_get_ctx(struct request_queue *q, unsigned int cpu) { - return per_cpu_ptr(q->queue_ctx, cpu); + struct blk_mq_ctx *ctx; + + ctx = per_cpu_ptr(q->queue_ctx, cpu); + return ctx; } /* @@ -85,12 +88,12 @@ */ static inline struct blk_mq_ctx *blk_mq_get_ctx(struct request_queue *q) { - return __blk_mq_get_ctx(q, get_cpu()); + return __blk_mq_get_ctx(q, get_cpu_light()); } static inline void blk_mq_put_ctx(struct blk_mq_ctx *ctx) { - put_cpu(); + put_cpu_light(); } struct blk_mq_alloc_data { diff -Naur --no-dereference a/block/blk-softirq.c b/block/blk-softirq.c --- a/block/blk-softirq.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/blk-softirq.c 2016-05-11 13:31:53.197225234 -0400 @@ -51,6 +51,7 @@ raise_softirq_irqoff(BLOCK_SOFTIRQ); local_irq_restore(flags); + preempt_check_resched_rt(); } /* @@ -93,6 +94,7 @@ this_cpu_ptr(&blk_cpu_done)); raise_softirq_irqoff(BLOCK_SOFTIRQ); local_irq_enable(); + preempt_check_resched_rt(); } return NOTIFY_OK; @@ -150,6 +152,7 @@ goto do_local; local_irq_restore(flags); + preempt_check_resched_rt(); } /** diff -Naur --no-dereference a/block/bounce.c b/block/bounce.c --- a/block/bounce.c 2016-05-04 17:50:15.000000000 -0400 +++ b/block/bounce.c 2016-05-11 13:31:53.197225234 -0400 @@ -55,11 +55,11 @@ unsigned long flags; unsigned char *vto; - local_irq_save(flags); + local_irq_save_nort(flags); vto = kmap_atomic(to->bv_page); memcpy(vto + to->bv_offset, vfrom, to->bv_len); kunmap_atomic(vto); - local_irq_restore(flags); + local_irq_restore_nort(flags); } #else /* CONFIG_HIGHMEM */ diff -Naur --no-dereference a/build_deb_in_arm_chroot.sh b/build_deb_in_arm_chroot.sh --- a/build_deb_in_arm_chroot.sh 1969-12-31 19:00:00.000000000 -0500 +++ b/build_deb_in_arm_chroot.sh 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,79 @@ +#!/bin/bash +CHROOT_DIR=/tmp/arm-chroot +VERSION=jessie +CHROOT_ARCH=armhf +MIRROR=http://httpredir.debian.org/debian +GUEST_DEPENDENCIES="build-essential git sudo lzop" +DEBOOT="1.0.80" + +function run_build { + cd ${CHROOT_DIR}/${TRAVIS_BUILD_DIR} + make bb.org_defconfig + make -s -j4 CROSS_COMPILE=arm-linux-gnueabihf- +} + +function run_package { +if [ ! true ] ; then + make KBUILD_DEBARCH=armhf KDEB_SOURCENAME=linux KDEB_CHANGELOG_DIST=unstable +else + echo "Not running this time" +fi +} + +function setup_arm_chroot { + pushd /tmp + wget https://beagleboard.org/static/arm-debian-jessie.rootfs.tgz + popd + + sudo mkdir ${CHROOT_DIR} + sudo tar xzf /tmp/arm-debian-jessie.rootfs.tgz -C ${CHROOT_DIR} + + echo "export ARCH=${ARCH}" > envvars.sh + echo "export TRAVIS_BUILD_DIR=${TRAVIS_BUILD_DIR}" >> envvars.sh + chmod a+x envvars.sh + + sudo chroot ${CHROOT_DIR} apt-get update + sudo chroot ${CHROOT_DIR} apt-get --allow-unauthenticated install \ + -qq -y ${GUEST_DEPENDENCIES} + sudo mkdir -p ${CHROOT_DIR}/${TRAVIS_BUILD_DIR} + sudo rsync -a ${TRAVIS_BUILD_DIR}/ ${CHROOT_DIR}/${TRAVIS_BUILD_DIR}/ + + sudo touch ${CHROOT_DIR}/.chroot_is_done +} + +function setup_arm_chroot_orig { + wget -c https://rcn-ee.net/mirror/debootstrap/debootstrap_${DEBOOT}_all.deb + if [ -f debootstrap_${DEBOOT}_all.deb ] ; then + sudo dpkg -i debootstrap_${DEBOOT}_all.deb + rm -rf debootstrap_${DEBOOT}_all.deb + fi + sudo mkdir ${CHROOT_DIR} + sudo debootstrap --foreign --no-check-gpg --include=fakeroot,build-essential \ + --arch=${CHROOT_ARCH} ${VERSION} ${CHROOT_DIR} ${MIRROR} + sudo cp /usr/bin/qemu-arm-static ${CHROOT_DIR}/usr/bin/ + sudo chroot ${CHROOT_DIR} ./debootstrap/debootstrap --second-stage + sudo sbuild-createchroot --arch=${CHROOT_ARCH} --foreign --setup-only \ + ${VERSION} ${CHROOT_DIR} ${MIRROR} + + echo "export ARCH=${ARCH}" > envvars.sh + echo "export TRAVIS_BUILD_DIR=${TRAVIS_BUILD_DIR}" >> envvars.sh + chmod a+x envvars.sh + + sudo chroot ${CHROOT_DIR} apt-get update + sudo chroot ${CHROOT_DIR} apt-get --allow-unauthenticated install \ + -qq -y ${GUEST_DEPENDENCIES} + sudo mkdir -p ${CHROOT_DIR}/${TRAVIS_BUILD_DIR} + sudo rsync -a ${TRAVIS_BUILD_DIR}/ ${CHROOT_DIR}/${TRAVIS_BUILD_DIR}/ + + sudo touch ${CHROOT_DIR}/.chroot_is_done +} + +if [ -e "/.chroot_is_done" ]; then + . ./envvars.sh + run_package +else + echo "Setting up chrooted ARM environment" + setup_arm_chroot + run_build + sudo chroot ${CHROOT_DIR} bash -c "cd ${TRAVIS_BUILD_DIR} && bash -ex build_deb_in_arm_chroot.sh" +fi diff -Naur --no-dereference a/crypto/algapi.c b/crypto/algapi.c --- a/crypto/algapi.c 2016-05-04 17:50:15.000000000 -0400 +++ b/crypto/algapi.c 2016-05-11 13:31:53.197225234 -0400 @@ -719,13 +719,13 @@ int crypto_register_notifier(struct notifier_block *nb) { - return blocking_notifier_chain_register(&crypto_chain, nb); + return srcu_notifier_chain_register(&crypto_chain, nb); } EXPORT_SYMBOL_GPL(crypto_register_notifier); int crypto_unregister_notifier(struct notifier_block *nb) { - return blocking_notifier_chain_unregister(&crypto_chain, nb); + return srcu_notifier_chain_unregister(&crypto_chain, nb); } EXPORT_SYMBOL_GPL(crypto_unregister_notifier); diff -Naur --no-dereference a/crypto/api.c b/crypto/api.c --- a/crypto/api.c 2016-05-04 17:50:15.000000000 -0400 +++ b/crypto/api.c 2016-05-11 13:31:53.197225234 -0400 @@ -31,7 +31,7 @@ DECLARE_RWSEM(crypto_alg_sem); EXPORT_SYMBOL_GPL(crypto_alg_sem); -BLOCKING_NOTIFIER_HEAD(crypto_chain); +SRCU_NOTIFIER_HEAD(crypto_chain); EXPORT_SYMBOL_GPL(crypto_chain); static struct crypto_alg *crypto_larval_wait(struct crypto_alg *alg); @@ -236,10 +236,10 @@ { int ok; - ok = blocking_notifier_call_chain(&crypto_chain, val, v); + ok = srcu_notifier_call_chain(&crypto_chain, val, v); if (ok == NOTIFY_DONE) { request_module("cryptomgr"); - ok = blocking_notifier_call_chain(&crypto_chain, val, v); + ok = srcu_notifier_call_chain(&crypto_chain, val, v); } return ok; diff -Naur --no-dereference a/crypto/internal.h b/crypto/internal.h --- a/crypto/internal.h 2016-05-04 17:50:15.000000000 -0400 +++ b/crypto/internal.h 2016-05-11 13:31:53.197225234 -0400 @@ -47,7 +47,7 @@ extern struct list_head crypto_alg_list; extern struct rw_semaphore crypto_alg_sem; -extern struct blocking_notifier_head crypto_chain; +extern struct srcu_notifier_head crypto_chain; #ifdef CONFIG_PROC_FS void __init crypto_init_proc(void); @@ -143,7 +143,7 @@ static inline void crypto_notify(unsigned long val, void *v) { - blocking_notifier_call_chain(&crypto_chain, val, v); + srcu_notifier_call_chain(&crypto_chain, val, v); } #endif /* _CRYPTO_INTERNAL_H */ diff -Naur --no-dereference a/Documentation/ABI/testing/debugfs-aufs b/Documentation/ABI/testing/debugfs-aufs --- a/Documentation/ABI/testing/debugfs-aufs 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/ABI/testing/debugfs-aufs 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,50 @@ +What: /debug/aufs/si_/ +Date: March 2009 +Contact: J. R. Okajima +Description: + Under /debug/aufs, a directory named si_ is created + per aufs mount, where is a unique id generated + internally. + +What: /debug/aufs/si_/plink +Date: Apr 2013 +Contact: J. R. Okajima +Description: + It has three lines and shows the information about the + pseudo-link. The first line is a single number + representing a number of buckets. The second line is a + number of pseudo-links per buckets (separated by a + blank). The last line is a single number representing a + total number of psedo-links. + When the aufs mount option 'noplink' is specified, it + will show "1\n0\n0\n". + +What: /debug/aufs/si_/xib +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xib (External Inode Number + Bitmap), its block size and file size. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see the aufs manual. + +What: /debug/aufs/si_/xino0, xino1 ... xinoN +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xino (External Inode Number + Translation Table), its link count, block size and file + size. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see the aufs manual. + +What: /debug/aufs/si_/xigen +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the consumed blocks by xigen (External Inode + Generation Table), its block size and file size. + If CONFIG_AUFS_EXPORT is disabled, this entry will not + be created. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see the aufs manual. diff -Naur --no-dereference a/Documentation/ABI/testing/sysfs-aufs b/Documentation/ABI/testing/sysfs-aufs --- a/Documentation/ABI/testing/sysfs-aufs 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/ABI/testing/sysfs-aufs 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,31 @@ +What: /sys/fs/aufs/si_/ +Date: March 2009 +Contact: J. R. Okajima +Description: + Under /sys/fs/aufs, a directory named si_ is created + per aufs mount, where is a unique id generated + internally. + +What: /sys/fs/aufs/si_/br0, br1 ... brN +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the abolute path of a member directory (which + is called branch) in aufs, and its permission. + +What: /sys/fs/aufs/si_/brid0, brid1 ... bridN +Date: July 2013 +Contact: J. R. Okajima +Description: + It shows the id of a member directory (which is called + branch) in aufs. + +What: /sys/fs/aufs/si_/xi_path +Date: March 2009 +Contact: J. R. Okajima +Description: + It shows the abolute path of XINO (External Inode Number + Bitmap, Translation Table and Generation Table) file + even if it is the default path. + When the aufs mount option 'noxino' is specified, it + will be empty. About XINO files, see the aufs manual. diff -Naur --no-dereference a/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x b/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x --- a/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/ABI/testing/sysfs-bus-iio-health-afe440x 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,54 @@ +What: /sys/bus/iio/devices/iio:deviceX/tia_resistanceY + /sys/bus/iio/devices/iio:deviceX/tia_capacitanceY +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Get and set the resistance and the capacitance settings for the + Transimpedance Amplifier. Y is 1 for Rf1 and Cf1, Y is 2 for + Rf2 and Cf2 values. + +What: /sys/bus/iio/devices/iio:deviceX/tia_separate_en +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Enable or disable separate settings for the TransImpedance + Amplifier above, when disabled both values are set by the + first channel. + +What: /sys/bus/iio/devices/iio:deviceX/in_intensity_ledY_raw + /sys/bus/iio/devices/iio:deviceX/in_intensity_ledY_ambient_raw +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Get measured values from the ADC for these stages. Y is the + specific LED number. The values are expressed in 24-bit twos + complement. + +What: /sys/bus/iio/devices/iio:deviceX/in_intensity_ledY-ledY_ambient_raw +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Get differential values from the ADC for these stages. Y is the + specific LED number. The values are expressed in 24-bit twos + complement for the specified LEDs. + +What: /sys/bus/iio/devices/iio:deviceX/out_current_ledY_offset + /sys/bus/iio/devices/iio:deviceX/out_current_ledY_ambient_offset +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Get and set the offset cancellation DAC setting for these + stages. The values are expressed in 5-bit sign-magnitude. + +What: /sys/bus/iio/devices/iio:deviceX/out_current_ledY_raw +Date: December 2015 +KernelVersion: +Contact: Andrew F. Davis +Description: + Get and set the LED current for the specified LED. Y is the + specific LED number. diff -Naur --no-dereference a/Documentation/ABI/testing/sysfs-devices-platform-bone_capemgr b/Documentation/ABI/testing/sysfs-devices-platform-bone_capemgr --- a/Documentation/ABI/testing/sysfs-devices-platform-bone_capemgr 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/ABI/testing/sysfs-devices-platform-bone_capemgr 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,63 @@ +What: /sys/devices/platform/bone_capemgr/slots +Date: May 2015 +KernelVersion: 4.0 +Contact: Pantelis Antoniou +Description: + READ: + Describe the state of all the slots of the beaglebone capemgr. + Each line of the output describes a slot: + The slot format is as following: + : [P-][F-][O-][l-][L-][D-] \ + ,, + , + + Where the flags are: + P: Slot has been probed + F: Slot has failed probing (i.e. no EEPROM detected) + O: Slot has been overridden by the user + l: Slot is current loading + L: Slot has completed loading and is ready + D: Slot has been disabled + + Example: + 0: P---L- -1 BeagleBone RS232 CAPE,00A1,Beagleboardtoys,BB-BONE-SERL-03 + 1: PF---- -1 + 2: PF---- -1 + 3: PF---- -1 + + WRITE: + Writing a string of the form [:version] issues a request to + load a firmware blob containing an overlay. The name of the firmware blob + is -[version|00A0].dtbo. This act is defined as a slot override. + + Writing a negative slot id removes the slot if it was an overridden one, or + unloads a slot that was probed. + +What: /sys/devices/platform/bone_capemgr/baseboard/ +Date: May 2015 +KernelVersion: 4.0 +Contact: Pantelis Antoniou +Description: Contains the probed base board EEPROM field; one of: + board-name - board-name as stored in cape EEPROM + dc-supplied - whether the cape draws or supplies DC + eeprom-format-revision - EEPROM format rev, only 00A0 supported + header - header; should be 'aa 55 33 ee' + manufacturer - manufacturer string + part-number - part-number of the cape + serial-number - serial number of the cape + version - version of the cape, i.e. 00A0 + number-of-pins - displayed but ignored + pin-usage - displayed but ignored + sys-5v - displayed but ignored + vdd-3v3exp - displayed but ignored + vdd-5v - displayed but ignored +What: /sys/devices/platform/bone_capemgr/slot-/ +Date: May 2015 +KernelVersion: 4.0 +Contact: Pantelis Antoniou +Description: Contains the probed cape's EEPROM field; the field is one of: + board-name - baseboard name i.e. A335BNLT + header - header; should be 'aa 55 33 ee' + revision - baseboard revision + serial-number - baseboard serial number + config-option - displayed but ignored diff -Naur --no-dereference a/Documentation/ABI/testing/sysfs-firmware-devicetree-overlays b/Documentation/ABI/testing/sysfs-firmware-devicetree-overlays --- a/Documentation/ABI/testing/sysfs-firmware-devicetree-overlays 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/ABI/testing/sysfs-firmware-devicetree-overlays 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,52 @@ +What: /sys/firmware/devicetree/overlays/ +Date: October 2015 +Contact: Pantelis Antoniou +Description: + This directory contains the applied device tree overlays of + the running system, as directories of the overlay id. + +What: /sys/firmware/devicetree/overlays/enable +Date: October 2015 +Contact: Pantelis Antoniou +Description: + The master enable switch, by default is 1, and when + set to 0 it cannot be re-enabled for security reasons. + + The discussion about this switch takes place in: + http://comments.gmane.org/gmane.linux.drivers.devicetree/101871 + + Kees Cook: + "Coming from the perspective of drawing a bright line between + kernel and the root user (which tends to start with disabling + kernel module loading), I would say that there at least needs + to be a high-level one-way "off" switch for the interface so + that systems that have this interface can choose to turn it off + during initial boot, etc." + +What: /sys/firmware/devicetree/overlays/ +Date: October 2015 +Contact: Pantelis Antoniou +Description: + Each directory represents an applied overlay, containing + the following attribute files. + +What: /sys/firmware/devicetree/overlays//can_remove +Date: October 2015 +Contact: Pantelis Antoniou +Description: + The attribute set to 1 means that the overlay can be removed, + while 0 means that the overlay is being overlapped therefore + removal is prohibited. + +What: /sys/firmware/devicetree/overlays/// +Date: October 2015 +Contact: Pantelis Antoniou +Description: + Each of these directories contain information about of the + particular overlay fragment. + +What: /sys/firmware/devicetree/overlays///target +Date: October 2015 +Contact: Pantelis Antoniou +Description: + The full-path of the target of the fragment diff -Naur --no-dereference a/Documentation/arm/keystone/netcp-pa.txt b/Documentation/arm/keystone/netcp-pa.txt --- a/Documentation/arm/keystone/netcp-pa.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/arm/keystone/netcp-pa.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,384 @@ + Keystone NETCP Packet Accelarator (PA and PA2) Device Driver + ------------------------------------------------------------ + +This document describes the Keystone NetCP PA device driver. To Know more +details on the hardware, please refers to the following hardware documents:- + +Packet Accelerator (PA) for KeyStone Devices User's Guide +http://www.ti.com/lit/ug/sprugs4a/sprugs4a.pdf + +KeyStone Architecture II Packet Accelerator 2 (PA2) for K2E and K2L Devices +User's Guide +http://www.ti.com/lit/ug/spruhz2/spruhz2.pdf + +Here is a description of the PA hardware as given in the above UG. + +The packet accelerator (PA) is one of the main components of the network +coprocessor (NETCP) peripheral. The PA works together with the security +accelerator (SA) and the gigabit Ethernet switch subsystem to form a +network processing solution. The purpose of PA in the NETCP is to perform +packet processing operations such as packet header classification, checksum +generation, and multi-queue routing. + +The below section shows the packet flow in the hardware and the hardware +resources associated with the same. + + (Resource map and Packet flow diagram) + -------------------------------------- + + Packet flow --------------------------- + | Linux NetCP PA device | + Ingress (CPSW port x) --------------------------- + | | | | | | + V | | | | | + CPSW | | | | | + | commands | | | ---- + | Packet Parse to LUT1 | ---- ^ + V -------- | ^ | + ----------Cluster 0-------------- | Chan 0 | | queue + | PDSP0 | L2 Classify Engine | <----| 640 <---| | for + | | Pass 1 LUT 0 | --------- | | flow 31 + --------------------------------- | | (Command + Match | | fail route to flow (22 to 25) | | Response) + | ----> xxxx | | + | | | + | commands | Per port Queue + | exception route to PDSP5 | Mapped to flows + V Packet Parse to L3 LUT2 | (22 to 25) + ----------Cluster 1-------------- --------- | for data packets + | | | | | + | | | | Chan 1 | + | PDSP1 | L3 Classify Engine 0 | <----| 641 <---| + | | Pass 1 LUT 1 | --------- | + | | classifcation of | | + | | packet using IP/L3 hdr| | + --------------------------------- | + Match | | fail route to flow | + V -----> (22 to 25)----> xxxx | + ----------Cluster 2-------------- | + | PDSP2 | L3 Classify Engine 1 | | + | | Pass 1 LUT 2 | (not used by | + | | classification of | Linux driver) | + | | IPSec packet using | | + | | inner IP header | | + --------------------------------- | + Match | | fail route to flow | + V ------> (22 to 25)----> xxxx | + ----------Cluster 3-------------- | + | PDSP3 | L4 Classify Engine | (not used by | + | | Pass 2 LUT 2 | Linux driver) | + | | classification of IP | | + | | packet using L4 hdr | | + | | TCP/UDP/Custom | | + --------------------------------- | + | + | + ----------Cluster 4-------------- | + | PDSP4 | Modify/Multi route | | + | | Engine 0 | (not used by | + | | | Linux driver) | + --------------------------------- | + | + ----------Cluster 5-------------- flows | + | PDSP5 | Modify/Multi route | 22 to 25 | + | | Engine 1 |---> xxxx | + | | | | + --------------------------------- (Not used by | + Linux driver) | + ---------- | + | Chan 4 | + |-----------------------| Queue 644 | + V ----------- | + ----------Cluster 4------------- | + | PDSP4 | Modify/Multi route | | + ---| | Engine | | + | | | (Generate L4 | commands | + | | | checksum - UDP/TCP/ | tx checksum/crc | + | | | SCTP) | | + | --------------------------------- Data packets | + | ---------- | + | | Chan 5 | + | |-----------------------| Queue 645<-| + | V ----------- + | ----------Cluster 5------------- + | | PDSP5 | Modify/Multi route | + | | | Engine | + | | | (Generate L4 | + | | | checksum - UDP/ | + | | | TCP/SCTP) | + | --------------------------------- + | | + |---------------->| + | + V + CPSW + | + V + Egress (CPSW port x) + | + V + +HW Queues 640-645 are for PA cluster 0-5 +Tx chan 0-5 are associated with the above queues +Rx flows 31 for command response +Rx flows 22-25 for rx data from each ethernet port + +Design Notes +------------ + +PA driver PA PDSP interface code re-uses code from PA LLD and it is +necessary to keep this code as close to PA LLD as possible for ease +of maintenance. + +The driver sends commands to L2 (cluster 0) and L3 engines (cluster 1) +to add MAC address and IP address in the respective LUTs. In the Egress +path, it receives packet from NetCP core driver through tx_hook and format +the commands to do tx checksums and add the command to PS Data field of +the hw descriptor that is then queued to the Modify/Multi route Engine +1 for PA on K2HK SoC (cluster 6 on PA on K2E/L SoC). On the Ingress path, +PA driver configures the streaming switch to route the packets to cluster +0 for processng which then travels through other clusters based on rules +setup in the LUT. + +PA resources such as LUT tables are shared resources across ARM and DSP +applications. It is expected that Linux PA driver adds entries to pre +defined indices in the table and others are used by other applications. +Generally packets are matched and routed to specific applicaitions and +rest of the packets fail back to Linux netcp PA device for handling. + +Other notes:- + +Cluster 5 (Modify/Multi route Engine) + - Configuration command for exception processing in all stages + - PDSP5 is the least busy PDSP and chosen for this + +Ingress + - Added entries in IP LUT to match UDP/TCP and forward the same + to L4 LUT2 + - IP checksum & SCTP crc verified at L3 Engine 0 + - UDP/TCP checksum verified at L4 Engine +Egress + - IP/UDP/TCP/SCTP checksum calculated in Modify or Multi route + Keystone NETCP PA Device for K2E/L + (resource map and packet flow diagram) + +=============================================================================== + Keystone NETCP PA Device Driver for K2E/L SoC + (Resource map and Packet flow diagram) + --------------------------------------------- + + Packet flow --------------------------- + | Linux NetCP PA device | + Ingress (CPSW port x) --------------------------- + | | | | | | + V | | | | | + CPSW | | | | | + | commands | | | ---- + | Packet parse to LUT1 | ---- ^ + V | ^ | + --------cluster 0 --------------- | | Queue + | Ingress 0 | |--------- | | for + |-------------------------------| | Chan 8 | | flow 31 + | PDSP0 | LUT1_0 (MAC classify) | <--| Queue 904<---| | (Command + | PDSP1 | LUT1_1 (Outer IP ACL) | --------- | | Response) + | | | | | + --------------------------------- | | + Match | | fail route to flow( 22 to 29) | | + | ----> | | + | commands | | + | exception route to cluster 5 | | + | Packet Parse to L3 Ingress | | + V 1, LUT1_0 | Per port Queues + --------cluster 1 --------------- | Mapped to flows + | Ingress 1 | | 22..30 + |--------------------------------| | (data) + | PDSP0 | LUT1_0 (Outer IP | ------------ | + | | classify, | | Chan 9 | + | PDSP1 | Custom header) |<---| Queue 905<--| + | | LUT1_1 (IPSEC NAT-T) | ------------ | + | | (IPSEC classify | | + | | first pass) | | + --------------------------------- | + Match | | + V | + --------Cluster 2 --------------| | + | Ingress 2 | | + |-------------------------------| | + | PDSP0 | LUT1_0 (IPSEC classify| | + | | second pass) | | + --------------------------------- | + | | + V | + --------Cluster 3---------------- | + | Ingress 3 | | + |-------------------------------- | + | PDSP0 | LUT1_0(Inner IP | | + | | firewall (ACL) | | + | | Reassembly Prep)| | + | | L3/L4 Header | | + | | Parse | | + --------------------------------- | + | | + V | + --------Cluster 4---------------- | + | Ingress 4 | | + |-------------------------------- | + | PDSP0 | LUT1_0(Inner IP | | + | | classify,L4 | | + | | checksum) | | + | PDSP1 | LUT2 | | + | | (TCP/UDP) | | + --------------------------------- | + | | + V | + --------Cluster 5---------------- | + | Post Classification | | + |-------------------------------- | + | PDSP0 | Packet patch | | + | | | | + | | | | + | PDSP1 | Packet patch | | + | | | | + --------------------------------- | + | + ------------ | + | Chan 14 | + |---------------------| Queue 910<---| + V ----------- + ---------Cluster 6--------------| + | Egress 0 | + |-------------------------------| + | PDSP0 | Flow Cache lookup | + | | using L3/L4 header | + | PDSP1 | Inner L3/L4 header | + | | Update (Checksum) | + | | Tx command processing| + | PDSP2 | Outer IP update | + | | IPSec pre-process | + | | Inner IP Fragment | + | | Tx command processing| + --------------------------------- + | + | + V + ---------Cluster 7--------------| + | Egress 1 | + |-------------------------------| + | PDSP0 | NAT-T header insert | + | | second IPSEC | + | | pre-processing | + --------------------------------- + | + | + V + ---------Cluster 8--------------| + | Egress 2 | + |-------------------------------| + | PDSP0 | L2 header insertion | + | | /update and Outer IP | + | | fragmentation | + --------------------------------- + | + V + CPSW + | + V + Egress (CPSW port x) + + +HW Queues 904-912 are for PA cluster 0-8 +Tx chan 8-16 are associated with the above queues +Rx flows 31 for command response +Rx flows 22-25, 27-30 for rx data from each ethernet port + +driver files and functional description +========================================== +drivers/net/ethernet/ti/netcp_pa_core.{c|h} + - file used by both PA and PA2 drivers to implement netcp + core module functions and common functions + - pa_core_ops - provide misc functions that are common across + both PA modules. + - hw ops - PA and PA2 module register hw functions as callbacks + to the core module during init. Core module invoke these functions + to pass control to the hw module (PA and PA2) +drivers/net/ethernet/ti/netcp_pa_host.h + - common host specific message header format definitions/macros + across PA and PA2 drivers +drivers/net/ethernet/ti/netcp_pa.c + - PA driver module. PA has multiple clusters (1 PDSP per cluster). + - PA driver configures L2 (cluster 0) and L3 engines for MAC and IP + rules in the Ingress paths. IP packets are forwarded to Modify/ + Multi route Engine 1 for Tx checksum calculation. The commands + to PA for doing this are added to data packets send to PA PDSP + associated with Modify/Multi route Engine 1. These gets added + to data packets as part of tx hooks. Rx hook checks the checksum + status and report the same to the stack. + - Provide Timestamps to tx and rx packets. + +drivers/net/ethernet/ti/netcp_pa_fw.h + - PA firmware interface definitions. All command message structures + are defined in this file. These are to be kept in sync with + TI's PA Low Level Design (LLD). +drivers/net/ethernet/ti/netcp_pa2_host.h + - PA2 specific message header format definitions/macros +drivers/net/ethernet/ti/netcp_pa2_fw.h + - PA2 firmware interface definitions +drivers/net/ethernet/ti/netcp_pa2.c + - PA2 driver module + +Firmware required by the drivers +================================ + +PA driver is responsible for loading and running the PA PDSP available in +each cluster. Following firmwares are required + +PA firmwares:- + ks2_pa_pdsp0_classify1.bin + ks2_pa_pdsp1_classify1.bin + ks2_pa_pdsp2_classify1.bin + ks2_pa_pdsp3_classify2.bin + ks2_pa_pdsp4_pam.bin + ks2_pa_pdsp5_pam.bin +PA2 firmwares:- + ks2_pa_in0_pdsp0.bin + ks2_pa_in0_pdsp1.bin + ks2_pa_in1_pdsp0.bin + ks2_pa_in1_pdsp1.bin + ks2_pa_in2_pdsp0.bin + ks2_pa_in3_pdsp0.bin + ks2_pa_in4_pdsp0.bin + ks2_pa_in4_pdsp1.bin + ks2_pa_post_pdsp0.bin + ks2_pa_post_pdsp1.bin + ks2_pa_eg0_pdsp0.bin + ks2_pa_eg0_pdsp1.bin + ks2_pa_eg0_pdsp2.bin + ks2_pa_eg1_pdsp0.bin + ks2_pa_eg2_pdsp0.bin + +Format: + The firmware image file contains firmware blob with a header. + The format of the image is as follows:- + +----------------------------------+ + | 16 chars of version string | + +----------------------------------+ + | 4 Constants(32 bits) for PA | + | OR | + | 32 Constants(32 bits) for PA2 | + +----------------------------------+ + | Firmware blob | + +----------------------------------+ + +DT Specifications at + + +Limitations +========== + +Currently when PA driver is built as a dynamically loadable module, +autoprobe doesn't work correctly. A Work around is to blacklist the +PA modules in the filesystem and then load them manually using +the following steps:- + - Bring down the interface (if interface is already up) + - insmod PA module .ko file + - Bring up the interface. diff -Naur --no-dereference a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt 2016-05-11 13:31:53.189225170 -0400 @@ -22,6 +22,8 @@ compatible = "ti,k2l", "ti,keystone" - Keystone 2 Edison compatible = "ti,k2e", "ti,keystone" +- K2G + compatible = "ti,k2g", "ti,keystone" Boards: - Keystone 2 Hawking/Kepler EVM @@ -32,3 +34,6 @@ - Keystone 2 Edison EVM compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" + +- K2G EVM + compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" diff -Naur --no-dereference a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,58 @@ +Texas Instruments System Control Interface (TI-SCI) Message Protocol +------------------------------------------------------------------- + +Texas Instrument's processors including those belonging to Keystone generation +of processors have separate hardware entity which is now responsible for the +management of the System on Chip (SoC) system. These include various system +level functions as well. + +TI-SCI controller Device Node: +============================= + +Required properties: +-------------------- +- compatible: should be "ti,k2g-sci" +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details +about the generic mailbox controller and client driver bindings. Also see +Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical +controller that is used to communicate with this System controllers. + +Optional Properties: +-------------------- +- reg-names: + debug_messages - Map the Debug message region +- reg: register space corresponding to the debug_messages + +Example (K2G): +-------- + pmmc: pmmc { + compatible = "ti,k2g-sci"; + mbox-names = "rx", "tx"; + mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>, + <&msgmgr &msgmgr_proxy_pmmc_tx>; + reg-names = "debug_messages"; + reg = <0x02921800 0x800>; + }; + + +TI-SCI Client Device Node: +======================== + +Client nodes refer to the required TI-SCI device using the "ti,sci" property. + +Example (K2G): +------------- + my_dev_node: dev_node { + ... + ti,sci = <&pmmc>; + ... + } diff -Naur --no-dereference a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt --- a/Documentation/devicetree/bindings/arm/omap/dmm.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/arm/omap/dmm.txt 2016-05-11 13:31:53.189225170 -0400 @@ -8,7 +8,8 @@ Required properties: - compatible: Should contain "ti,omap4-dmm" for OMAP4 family - Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family + Should contain "ti,omap5-dmm" for OMAP5 family + Should contain "ti,dra7-dmm" for DRA7x family - reg: Contains DMM register address range (base address and length) - interrupts: Should contain an interrupt-specifier for DMM_IRQ. - ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" diff -Naur --no-dereference a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt --- a/Documentation/devicetree/bindings/arm/omap/omap.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt 2016-05-11 13:31:53.189225170 -0400 @@ -143,7 +143,7 @@ compatible = "ti,omap5-evm", "ti,omap5" - AM43x EPOS EVM - compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" + compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x" - AM437x GP EVM compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" @@ -151,6 +151,15 @@ - AM437x SK EVM: AM437x StarterKit Evaluation Module compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43" +- AM5728 GPEVM + compatible = "ti,am5728-evm", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5728 IDK + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + +- AM5718 IDK + compatible = "ti,am5718-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + - DRA742 EVM: Software Development Board for DRA742 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" diff -Naur --no-dereference a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt --- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt 1969-12-31 19:00:00.000000000 -0500 @@ -1,130 +0,0 @@ -Device tree bindings for OMAP general purpose memory controllers (GPMC) - -The actual devices are instantiated from the child nodes of a GPMC node. - -Required properties: - - - compatible: Should be set to one of the following: - - ti,omap2420-gpmc (omap2420) - ti,omap2430-gpmc (omap2430) - ti,omap3430-gpmc (omap3430 & omap3630) - ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) - ti,am3352-gpmc (am335x devices) - - - reg: A resource specifier for the register space - (see the example below) - - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is - completed. - - #address-cells: Must be set to 2 to allow memory address translation - - #size-cells: Must be set to 1 to allow CS address passing - - gpmc,num-cs: The maximum number of chip-select lines that controller - can support. - - gpmc,num-waitpins: The maximum number of wait pins that controller can - support. - - ranges: Must be set up to reflect the memory layout with four - integer values for each chip-select line in use: - - 0 - - Currently, calculated values derived from the contents - of the per-CS register GPMC_CONFIG7 (as set up by the - bootloader) are used for the physical address decoding. - As this will change in the future, filling correct - values here is a requirement. - -Timing properties for child nodes. All are optional and default to 0. - - - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: - - gpmc,cs-on-ns: Assertion time - - gpmc,cs-rd-off-ns: Read deassertion time - - gpmc,cs-wr-off-ns: Write deassertion time - - ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: - - gpmc,adv-on-ns: Assertion time - - gpmc,adv-rd-off-ns: Read deassertion time - - gpmc,adv-wr-off-ns: Write deassertion time - - WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,we-on-ns Assertion time - - gpmc,we-off-ns: Deassertion time - - OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: - - gpmc,oe-on-ns: Assertion time - - gpmc,oe-off-ns: Deassertion time - - Access time and cycle time timings (in nanoseconds) corresponding to - GPMC_CONFIG5: - - gpmc,page-burst-access-ns: Multiple access word delay - - gpmc,access-ns: Start-cycle to first data valid delay - - gpmc,rd-cycle-ns: Total read cycle time - - gpmc,wr-cycle-ns: Total write cycle time - - gpmc,bus-turnaround-ns: Turn-around time between successive accesses - - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses - - gpmc,clk-activation-ns: GPMC clock activation time - - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid - data - -Boolean timing parameters. If property is present parameter enabled and -disabled if omitted: - - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock - - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock - - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive - accesses to a different CS - - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive - accesses to the same CS - - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock - - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock - - gpmc,time-para-granularity: Multiply all access times by 2 - -The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access-ns: In synchronous write mode, for single or - burst accesses, defines the number of - GPMC_FCLK cycles from start access time - to the GPMC_CLK rising edge used by the - memory device for the first data capture. - - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies - the time when the first data is driven on - the address-data bus. - -GPMC chip-select settings properties for child nodes. All are optional. - -- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. -- gpmc,burst-wrap Enables wrap bursting -- gpmc,burst-read Enables read page/burst mode -- gpmc,burst-write Enables write page/burst mode -- gpmc,device-width Total width of device(s) connected to a GPMC - chip-select in bytes. The GPMC supports 8-bit - and 16-bit devices and so this property must be - 1 or 2. -- gpmc,mux-add-data Address and data multiplexing configuration. - Valid values are 1 for address-address-data - multiplexing mode and 2 for address-data - multiplexing mode. -- gpmc,sync-read Enables synchronous read. Defaults to asynchronous - is this is not set. -- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous - is this is not set. -- gpmc,wait-pin Wait-pin used by client. Must be less than - "gpmc,num-waitpins". -- gpmc,wait-on-read Enables wait monitoring on reads. -- gpmc,wait-on-write Enables wait monitoring on writes. - -Example for an AM33xx board: - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - interrupts = <100>; - - gpmc,num-cs = <8>; - gpmc,num-waitpins = <2>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ - - /* child nodes go here */ - }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt --- a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,46 @@ +Texas Instruments TI-SCI Clocks + +All clocks on Texas Instruments' SoCs that contain a System Controller +core, are only controlled by this entity. Communication between a +host processor running an OS and the System Controller happens through a +protocol known as TI SCI. This clock implementation plugs into the +common clock framework and makes use of the TI SCI protocol on clock +API requests. + +Required properties: +- compatible: Must be "ti,sci-clk" +- #clock-cells: Shall be 2. + In clock consumers, this cell represents the device ID and clock ID + exposed by the PM firmware. The assignments can be found in the header + files .h> (which covers the device IDs) and + .h> (which covers the clock IDs), where + is the SoC involved, for example 'k2g'. +- ti,sci: Phandle to the TI SCI device to use for managing the clocks + +Optional properties: +- ti,ssc-clocks: Array of phandle clocks that shall enable spread spectrum + clocking while enabled +- ti,allow-freq-change-clocks: Array of phandle clocks that shall allow + dynamic clock frequency changes by firmware +- ti,input-term-clocks: Array of phandle clocks that shall enable input + termination + +Examples: + +k2g_clks: k2g_clks { + compatible = "ti,sci-clk"; + ti,sci = <&pmmc>; + #clock-cells = <2>; +}; + +dummy_node@1234 { + clocks = <&k2g_clks K2G_DEV_DUMMY K2G_DEV_DUMMY_FCK>; +}; + +dummy_node2@2345 { + clocks = <&k2g_clks K2G_DEV_DUMMY2 K2G_DEV_DUMMY_X1_CLK>; +}; + +&k2g_clks { + ti,ssc-clocks = <&k2g_clks K2G_DEV_DUMMY K2G_DEV_DUMMY_FCK>; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/display/bridge/tda998x.txt b/Documentation/devicetree/bindings/display/bridge/tda998x.txt --- a/Documentation/devicetree/bindings/display/bridge/tda998x.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/display/bridge/tda998x.txt 2016-05-11 13:31:53.189225170 -0400 @@ -17,8 +17,19 @@ - video-ports: 24 bits value which defines how the video controller output is wired to the TDA998x input - default: <0x230145> + - audio-ports: array of 8-bit values, 2 values per one DAI[1]. + The first value defines the DAI type: TDA998x_SPDIF or TDA998x_I2S[2]. + The second value defines the tda998x AP_ENA reg content when the DAI + in question is used. The implementation allows one or two DAIs. If two + DAIs are defined, they must be of different type. + +[1] Documentation/sound/alsa/soc/DAI.txt +[2] include/dt-bindings/display/tda998x.h + Example: +#include + tda998x: hdmi-encoder { compatible = "nxp,tda998x"; reg = <0x70>; @@ -26,4 +37,11 @@ interrupts = <27 2>; /* falling edge */ pinctrl-0 = <&pmx_camera>; pinctrl-names = "default"; + video-ports = <0x230145>; + + #sound-dai-cells = <2>; + /* DAI-format AP_ENA reg value */ + audio-ports = < TDA998x_SPDIF 0x04 + TDA998x_I2S 0x03>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/display/simple-framebuffer.txt b/Documentation/devicetree/bindings/display/simple-framebuffer.txt --- a/Documentation/devicetree/bindings/display/simple-framebuffer.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/display/simple-framebuffer.txt 2016-05-11 13:31:53.189225170 -0400 @@ -47,10 +47,14 @@ - a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). Optional properties: -- clocks : List of clocks used by the framebuffer. Clocks listed here - are expected to already be configured correctly. The OS must - ensure these clocks are not modified or disabled while the - simple framebuffer remains active. +- clocks : List of clocks used by the framebuffer. +- *-supply : Any number of regulators used by the framebuffer. These should + be named according to the names in the device's design. + + The above resources are expected to already be configured correctly. + The OS must ensure they are not modified or disabled while the simple + framebuffer remains active. + - display : phandle pointing to the primary display hardware node Example: @@ -68,6 +72,7 @@ stride = <(1600 * 2)>; format = "r5g6b5"; clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; + lcd-supply = <®_dc1sw>; display = <&lcdc0>; }; stdout-path = "display0"; diff -Naur --no-dereference a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt --- a/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt 2016-05-11 13:31:53.189225170 -0400 @@ -14,6 +14,10 @@ Optional properties: - ti,dma-safe-map: Safe routing value for unused request lines +- ti,reserved-dma-request-ranges: DMA request ranges which should not be used + when mapping xbar input to DMA request, they are either + allocated to be used by for example the DSP or they are used as + memcpy channels in eDMA. Notes: When requesting channel via ti,dra7-dma-crossbar, the DMA clinet must request @@ -46,6 +50,8 @@ #dma-cells = <1>; dma-requests = <205>; ti,dma-safe-map = <0>; + /* Protect the sDMA request ranges: 10-14 and 100-126 */ + ti,reserved-dma-request-ranges = <10 5>, <100 27>; dma-masters = <&sdma>; }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/edac/keystone-mc-edac.txt b/Documentation/devicetree/bindings/edac/keystone-mc-edac.txt --- a/Documentation/devicetree/bindings/edac/keystone-mc-edac.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/edac/keystone-mc-edac.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,23 @@ +* Keystone DDR3 Memory Controller EDAC device bindings + +Keystone MC EDAC node is defined to describe the DDR3 memory controller +ECC error detection hardware. The hardware is capable of auto correcting +1 bit ECC errors. 2 bit ECC errors are uncorrectable and triggers an +interrupt and handled by the edac ecc error driver which currently enables +only interrupt for uncorrectable errors. + +The following section describes the EDAC DT node binding. + +Required properties: +- compatible : Shall be "ti,keystone-ddr3-mc-edac" +- reg : DDR3 MC base address +- interrupts : ECC error interrupt +- interrupt-parent : Interrupt controller node + +Example: + ddr3edac { + compatible = "ti,keystone-ddr3-mc-edac"; + reg = <0x21010000 0x200>; + interrupts = ; + interrupt-parent = <&gic>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt --- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt 2016-05-11 13:31:53.189225170 -0400 @@ -1,7 +1,7 @@ Davinci/Keystone GPIO controller bindings Required Properties: -- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio" +- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio", "ti,k2g-gpio" - reg: Physical base address of the controller and the size of memory mapped registers. diff -Naur --no-dereference a/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt b/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt --- a/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/gpio/gpio-pisosr.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,34 @@ +Generic Parallel-in/Serial-out Shift Register GPIO Driver + +This binding describes generic parallel-in/serial-out shift register +devices that can be used for GPI (General Purpose Input). This includes +SN74165 serial-out shift registers and the SN65HVS88x series of +industrial serializers. + +Required properties: + - compatible : Should be "pisosr-gpio". + - gpio-controller : Marks the device node as a GPIO controller. + - #gpio-cells : Should be two. For consumer use see gpio.txt. + +Optional properties: + - ngpios : Number of GPIO lines, default is 8. + - load-gpios : GPIO pin specifier attached to load enable, this + pin is pulsed before reading from the device to + load input pin values into the the device. + +For other required and optional properties of SPI slave +nodes please refer to ../spi/spi-bus.txt. + +Example: + + gpio@0 { + compatible = "ti,sn65hvs882", "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt b/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt --- a/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,16 @@ +TPIC2810 GPIO controller bindings + +Required properties: + - compatible : Should be "ti,tpic2810". + - reg : The I2C address of the device + - gpio-controller : Marks the device node as a GPIO controller. + - #gpio-cells : Should be two. For consumer use see gpio.txt. + +Example: + + gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/gpu/ti-sgx.txt b/Documentation/devicetree/bindings/gpu/ti-sgx.txt --- a/Documentation/devicetree/bindings/gpu/ti-sgx.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/gpu/ti-sgx.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,34 @@ +Texas Instruments SGX 3D Graphics Processing Unit + +SGX is a 3D Graphics Processing Unit from Imagination Technologies. SGX is +codename for 5th generation / Series 5 of PowerVR chipset family. This binding +describes PowerVR SGX GPU integrated in Texas Instrument SoCs. + +Required properties: + - compatible : value should take the following format: + "ti,-", "img," + + accepted values: + (a) "ti,dra7-sgx544", "img,sgx544" for TI DRA7xx / AM57x + (b) "ti,am4376-sgx530", "img,sgx530" for TI AM43x + (c) "ti,am3352-sgx530", "img,sgx530" for TI AM33x + - reg: base address and length of the SGX registers + - interrupts : SGX interrupt number + - ti,hwmods: Name of the hwmod associated with the SGX + - clocks : from SoC clock binding + +Optional properties: + - reg-names : names of registers listed in reg property in same order + - clock-names : names of clocks listed in clocks property in the same order + +Example: + sgx@0x56000000 { + compatible = "ti,dra7-sgx544", "img,sgx544"; + reg = <0x5600fe00 0x200>; + reg-names = "gpu_ocp_base"; + interrupts = ; + ti,hwmods = "gpu"; + clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>, + <&gpu_hyd_gclk_mux>; + clock-names = "iclk", "fclk1", "fclk2"; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/iio/health/afe4403.txt b/Documentation/devicetree/bindings/iio/health/afe4403.txt --- a/Documentation/devicetree/bindings/iio/health/afe4403.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/iio/health/afe4403.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,34 @@ +Texas Instruments AFE4403 Heart rate and Pulse Oximeter + +Required properties: + - compatible : Should be "ti,afe4403". + - reg : SPI chip select address of device. + - tx-supply : Regulator supply to transmitting LEDs. + - interrupt-parent : Phandle to he parent interrupt controller. + - interrupts : The interrupt line the device ADC_RDY pin is + connected to. For details refer to, + ../../interrupt-controller/interrupts.txt. + +Optional properties: + - reset-gpios : GPIO used to reset the device. + For details refer to, ../../gpio/gpio.txt. + +For other required and optional properties of SPI slave nodes +please refer to ../../spi/spi-bus.txt. + +Example: + +&spi0 { + heart_mon@0 { + compatible = "ti,afe4403"; + reg = <0>; + spi-max-frequency = <10000000>; + + tx-supply = <&vbat>; + + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_RISING>; + + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/iio/health/afe4404.txt b/Documentation/devicetree/bindings/iio/health/afe4404.txt --- a/Documentation/devicetree/bindings/iio/health/afe4404.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/iio/health/afe4404.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,30 @@ +Texas Instruments AFE4404 Heart rate and Pulse Oximeter + +Required properties: + - compatible : Should be "ti,afe4404". + - reg : I2C address of the device. + - tx-supply : Regulator supply to transmitting LEDs. + - interrupt-parent : Phandle to he parent interrupt controller. + - interrupts : The interrupt line the device ADC_RDY pin is + connected to. For details refer to, + ../interrupt-controller/interrupts.txt. + +Optional properties: + - reset-gpios : GPIO used to reset the device. + For details refer to, ../gpio/gpio.txt. + +Example: + +&i2c2 { + heart_mon@58 { + compatible = "ti,afe4404"; + reg = <0x58>; + + tx-supply = <&vbat>; + + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_RISING>; + + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt --- a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,50 @@ +Texas Instruments' Message Manager Driver +======================================== + +The Texas Instruments' Message Manager is a mailbox controller that has +configurable queues selectable at SoC(System on Chip) integration. The Message +manager is broken up into queues in different address regions that are called +"proxies" - each instance is unidirectional and is instantiated at SoC +integration level to indicate receive or transmit path. + +Message Manager Device Node: +=========================== +Required properties: +-------------------- +- compatible: Shall be: "ti,k2g-message-manager" +- reg-names queue_proxy_region - Map the queue proxy region. + queue_state_debug_region - Map the queue state debug + region. +- reg: Contains the register map per reg-names. +- #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that + order referring to the transfer path. +- interrupt-names: Contains interrupt names matching the rx transfer path + for a given SoC. Receive interrupts shall be of the + format: "rx__". + For ti,k2g-message-manager, this shall contain: + "rx_005_002", "rx_057_002" +- interrupts: Contains the interrupt information corresponding to + interrupt-names property. + +Example(K2G): +------------ + + msgmgr: msgmgr@02a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", "rx_057"; + interrupts = , + ; + }; + + pmmc: pmmc { + [...] + mbox-names = "rx", "tx"; + # RX queue ID is 5, proxy ID is 2 + # TX queue ID is 0, proxy ID is 0 + mboxes= <&msgmgr 5 2>, + <&msgmgr 0 0>; + [...] + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/i2c/mt9t11x.txt b/Documentation/devicetree/bindings/media/i2c/mt9t11x.txt --- a/Documentation/devicetree/bindings/media/i2c/mt9t11x.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/media/i2c/mt9t11x.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,49 @@ +* Aptina 1/4-Inch QXGA CMOS Digital Image Sensor + +The Aptina MT9T111 is a 1/4-inch CMOS active pixel digital image sensor with +an active array size of 2048H x 1536V. It is programmable through a simple +two-wire serial interface. + +Required Properties: + +- compatible: value should be either one among the following + (a) "aptina,mt9t111" for MT9T111 color sensor + (b) "aptina,mt9t112" for MT9T112 color sensor + +- input-clock-freq: Source clock freqquency (Hz) +- pixel-clock-freq: Target pixel clock freqquency (Hz) + +Optional Properties: + +- reset-gpios: Toggle when the module is enabled or disabled. +- powerdown-gpios: Toggle when the module is enabled or disabled. +- oscen-gpios: Enabled once at probe time. +- bufen-gpios: Enabled once at probe time. +- camen-gpios: Enabled once at probe time. + +For further reading on port node refer to +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + + mt9t111@3C { + compatible = "aptina,mt9t111"; + reg = <0x3C>; + + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + oscen-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + bufen-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + camen-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + + port { + cam: endpoint { + remote-endpoint = <&vin3a>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <1>; + input-clock-freq = <32000000>; + pixel-clock-freq = <96000000>; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/i2c/ov1063x.txt b/Documentation/devicetree/bindings/media/i2c/ov1063x.txt --- a/Documentation/devicetree/bindings/media/i2c/ov1063x.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/media/i2c/ov1063x.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,40 @@ +* OmniVision 8/10 bit digital camera + +The Omnivision digital camera is a 720p camera which is configurable at 8/10bit +YUYV output and can be configured for various resolutions. + +Required Properties: +- compatible : Must be one of the following + - "ovti,ov10633": For OV10633 camera + - "ovti,ov10635": For OV10635 camera + +Optional Properties: +- gpios : A list of gpios with active high/low flags for enabling the sensor. + This may contain gpios for power, board muxes, etc. Driver would + set all of them as specified by the active high/low flag + + There are no custom optional properties supported for this device. + Although all the endpoint properties documented in + Documentation/devicetree/bindings/media/video-interfaces.txt are supported. + +Example: + + &i2c2 { + ... + ... + ovcamera@30 { + compatible = "ovti,ov10635"; + reg = <0x30>; + + mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; + + port { + onboard_cam: endpoint { + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <1>; + }; + }; + }; + ... + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/ti-cal.txt b/Documentation/devicetree/bindings/media/ti-cal.txt --- a/Documentation/devicetree/bindings/media/ti-cal.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/media/ti-cal.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,72 @@ +Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) +------------------------------------------------------ + +The Camera Adaptation Layer (CAL) is a key component for image capture +applications. The capture module provides the system interface and the +processing capability to connect CSI2 image-sensor modules to the +DRA72x device. + +Required properties: +- compatible: must be "ti,dra72-cal" +- reg: CAL Top level, Receiver Core #0, Receiver Core #1 and Camera RX + control address space +- reg-names: cal_top, cal_rx_core0, cal_rx_core1, and camerrx_control + registers +- interrupts: should contain IRQ line for the CAL; + +CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes +should contain a 'port' child node with child 'endpoint' node. Please +refer to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + cal: cal@4845b000 { + compatible = "ti,dra72-cal"; + ti,hwmods = "cal"; + reg = <0x4845B000 0x400>, + <0x4845B800 0x40>, + <0x4845B900 0x40>, + <0x4A002e94 0x4>; + reg-names = "cal_top", + "cal_rx_core0", + "cal_rx_core1", + "camerrx_control"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_0: port@0 { + reg = <0>; + endpoint { + slave-mode; + remote-endpoint = <&ar0330_1>; + }; + }; + csi2_1: port@1 { + reg = <1>; + }; + }; + }; + + i2c5: i2c@4807c000 { + ar0330@10 { + compatible = "ti,ar0330"; + reg = <0x10>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ar0330_1: endpoint { + reg = <0>; + clock-lanes = <1>; + data-lanes = <0 2 3 4>; + remote-endpoint = <&csi2_0>; + }; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/ti-vip.txt b/Documentation/devicetree/bindings/media/ti-vip.txt --- a/Documentation/devicetree/bindings/media/ti-vip.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/media/ti-vip.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,94 @@ +Texas Instruments DRA7x VIDEO INPUT PORT (VIP) +---------------------------------------------- + +The Video Input Port (VIP) is a key component for image capture +applications. The capture module provides the system interface and the +processing capability to connect parallel image-sensor as well as +BT.656/1120 capable encoder chip. + +Required properties: +- compatible: must be "ti,vip1", "ti,vip2" or "ti,vip3". +- reg: VIP top level, parser, colorspace converter, scaler for slice 0 and 1 + and vpdma memory address space; +- reg-names: vip, parser0, csc0, sc0, parser1, csc1, sc1 and vpdma registers; +- interrupts: should contain IRQ line for VIP; +- syscon-pol: phandle to the device control module; + +VIP supports 2 slices. Each slice can handle up to 2 camera port nodes. +Each port nodes should contain a 'port' child node with child 'endpoint' +node. Please refer to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + vip1: vip@0x48970000 { + compatible = "ti,vip1"; + reg = <0x48970000 0x114>, + <0x48975500 0xD8>, + <0x48975700 0x18>, + <0x48975800 0x80>, + <0x48975a00 0xD8>, + <0x48975c00 0x18>, + <0x48975d00 0x80>, + <0x4897d000 0x400>; + reg-names = "vip", + "parser0", + "csc0", + "sc0", + "parser1", + "csc1", + "sc1", + "vpdma"; + ti,hwmods = "vip1"; + interrupts = , + ; + /* CTRL_CORE_SMA_SW_1 */ + syscon-pol = <&scm_conf 0x534>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + vin1a: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + endpoint@0 { + slave-mode; + remote-endpoint = <&camera1>; + }; + }; + vin2a: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + }; + vin1b: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + status = "disabled"; + }; + vin2b: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + status = "disabled"; + }; + }; + + i2c5: i2c@4807c000 { + ov10633@37 { + compatible = "ovti,ov10633"; + reg = <0x37>; + + mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; + port { + camera1: endpoint { + remote-endpoint = <&vin1a>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/ti-vpe.txt b/Documentation/devicetree/bindings/media/ti-vpe.txt --- a/Documentation/devicetree/bindings/media/ti-vpe.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/media/ti-vpe.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,41 @@ +Texas Instruments DRA7x VIDEO PROCESSING ENGINE (VPE) +------------------------------------------------------ + +The Video Processing Engine (VPE) is a key component for image post +processing applications. VPE consist of a single memory to memory +path which can perform chroma up/down sampling, deinterlacing, +scaling and color space conversion. + +Required properties: +- compatible: must be "ti,vpe" +- reg: physical base address and length of the registers set for the 8 + memory regions required; +- reg-names: name associated with the memory regions described is ; +- interrupts: should contain IRQ line for VPE; + +Example: + vpe { + compatible = "ti,vpe"; + ti,hwmods = "vpe"; + clocks = <&dpll_core_h23x2_ck>; + clock-names = "fck"; + reg = <0x489d0000 0x120>, + <0x489d0300 0x20>, + <0x489d0400 0x20>, + <0x489d0500 0x20>, + <0x489d0600 0x3c>, + <0x489d0700 0x80>, + <0x489d5700 0x18>, + <0x489dd000 0x400>; + reg-names = "vpe_top", + "vpe_chr_us0", + "vpe_chr_us1", + "vpe_chr_us2", + "vpe_dei", + "sc", + "csc", + "vpdma"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt --- a/Documentation/devicetree/bindings/media/video-interfaces.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt 2016-05-11 13:31:53.189225170 -0400 @@ -86,6 +86,8 @@ synchronization may be required, where supported. - data-active: similar to HSYNC and VSYNC, specifies data line polarity. - field-even-active: field signal level during the even field data transmission. +- num-channels: for time multiplexed multi channel video signal, this property + specifies number of channels multiplexed. - pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock signal. - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for diff -Naur --no-dereference a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt --- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,146 @@ +Device tree bindings for OMAP general purpose memory controllers (GPMC) + +The actual devices are instantiated from the child nodes of a GPMC node. + +Required properties: + + - compatible: Should be set to one of the following: + + ti,omap2420-gpmc (omap2420) + ti,omap2430-gpmc (omap2430) + ti,omap3430-gpmc (omap3430 & omap3630) + ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) + ti,am3352-gpmc (am335x devices) + + - reg: A resource specifier for the register space + (see the example below) + - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is + completed. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - gpmc,num-cs: The maximum number of chip-select lines that controller + can support. + - gpmc,num-waitpins: The maximum number of wait pins that controller can + support. + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + 0 + + Currently, calculated values derived from the contents + of the per-CS register GPMC_CONFIG7 (as set up by the + bootloader) are used for the physical address decoding. + As this will change in the future, filling correct + values here is a requirement. + - gpio-controller: The GPMC driver implements a GPIO controller for the + GPMC WAIT pins that can be used as general purpose inputs. + 0 maps to GPMC_WAIT0 pin. + - interrupt-controller: The GPMC driver implements and interrupt controller for + the NAND events "fifoevent" and "termcount" plus the + rising/falling edges on the GPMC_WAIT pins. + The interrupt number mapping is as follows + 0 - NAND_fifoevent + 1 - NAND_termcount + 2 - GPMC_WAIT0 pin edge + 3 - GPMC_WAIT1 pin edge, and so on. + +Required properties when using NAND prefetch dma: + - dmas GPMC NAND prefetch dma channel + - dma-names Must be set to "rxtx" + +Timing properties for child nodes. All are optional and default to 0. + + - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: + - gpmc,cs-on-ns: Assertion time + - gpmc,cs-rd-off-ns: Read deassertion time + - gpmc,cs-wr-off-ns: Write deassertion time + + ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: + - gpmc,adv-on-ns: Assertion time + - gpmc,adv-rd-off-ns: Read deassertion time + - gpmc,adv-wr-off-ns: Write deassertion time + + WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,we-on-ns Assertion time + - gpmc,we-off-ns: Deassertion time + + OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,oe-on-ns: Assertion time + - gpmc,oe-off-ns: Deassertion time + + Access time and cycle time timings (in nanoseconds) corresponding to + GPMC_CONFIG5: + - gpmc,page-burst-access-ns: Multiple access word delay + - gpmc,access-ns: Start-cycle to first data valid delay + - gpmc,rd-cycle-ns: Total read cycle time + - gpmc,wr-cycle-ns: Total write cycle time + - gpmc,bus-turnaround-ns: Turn-around time between successive accesses + - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses + - gpmc,clk-activation-ns: GPMC clock activation time + - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid + data + +Boolean timing parameters. If property is present parameter enabled and +disabled if omitted: + - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock + - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock + - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive + accesses to a different CS + - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive + accesses to the same CS + - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock + - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock + - gpmc,time-para-granularity: Multiply all access times by 2 + +The following are only applicable to OMAP3+ and AM335x: + - gpmc,wr-access-ns: In synchronous write mode, for single or + burst accesses, defines the number of + GPMC_FCLK cycles from start access time + to the GPMC_CLK rising edge used by the + memory device for the first data capture. + - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies + the time when the first data is driven on + the address-data bus. + +GPMC chip-select settings properties for child nodes. All are optional. + +- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. +- gpmc,burst-wrap Enables wrap bursting +- gpmc,burst-read Enables read page/burst mode +- gpmc,burst-write Enables write page/burst mode +- gpmc,device-width Total width of device(s) connected to a GPMC + chip-select in bytes. The GPMC supports 8-bit + and 16-bit devices and so this property must be + 1 or 2. +- gpmc,mux-add-data Address and data multiplexing configuration. + Valid values are 1 for address-address-data + multiplexing mode and 2 for address-data + multiplexing mode. +- gpmc,sync-read Enables synchronous read. Defaults to asynchronous + is this is not set. +- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous + is this is not set. +- gpmc,wait-pin Wait-pin used by client. Must be less than + "gpmc,num-waitpins". +- gpmc,wait-on-read Enables wait monitoring on reads. +- gpmc,wait-on-write Enables wait monitoring on writes. + +Example for an AM33xx board: + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = <100>; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ + + /* child nodes go here */ + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/mfd/tps65086.txt b/Documentation/devicetree/bindings/mfd/tps65086.txt --- a/Documentation/devicetree/bindings/mfd/tps65086.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/mfd/tps65086.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,55 @@ +* TPS65086 Power Management Integrated Circuit (PMIC) bindings + +Required properties: + - compatible : Should be "ti,tps65086". + - reg : I2C slave address. + - interrupt-parent : Phandle to the parent interrupt controller. + - interrupts : The interrupt line the device is connected to. + - interrupt-controller : Marks the device node as an interrupt controller. + - #interrupt-cells : The number of cells to describe an IRQ, should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as trigger + masks from ../interrupt-controller/interrupts.txt. + - gpio-controller : Marks the device node as a GPIO Controller. + - #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + - regulators: : List of child nodes that specify the regulator + initialization data. Child nodes must be named + after their hardware counterparts: buck[1-6], + ldoa[1-3], swa1, swb[1-2], and vtt. Each child + node is defined using the standard binding for + regulators and the optional regulator properties + defined below. + +Optional regulator properties: + - ti,regulator-step-size-25mv : This is applicable for buck[1,2,6], set this + if the regulator is factory set with a 25mv + step voltage mapping. + - ti,regulator-decay : This is applicable for buck[1-6], set this if + the output needs to decay, default is for + the output to slew down. + +Example: + + pmic: tps65086@5e { + compatible = "ti,tps65086"; + reg = <0x5e>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + buck1 { + regulator-name = "vcc1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + regulator-boot-on; + ti,regulator-decay; + ti,regulator-step-size-25mv; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/mfd/tps65912.txt b/Documentation/devicetree/bindings/mfd/tps65912.txt --- a/Documentation/devicetree/bindings/mfd/tps65912.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/mfd/tps65912.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,50 @@ +* TPS65912 Power Management Integrated Circuit bindings + +Required properties: + - compatible : Should be "ti,tps65912". + - reg : Slave address or chip select number (I2C / SPI). + - interrupt-parent : The parent interrupt controller. + - interrupts : The interrupt line the device is connected to. + - interrupt-controller : Marks the device node as an interrupt controller. + - #interrupt-cells : The number of cells to describe an IRQ, should be 2. + The first cell is the IRQ number. + The second cell is the flags, encoded as trigger + masks from ../interrupt-controller/interrupts.txt. + - gpio-controller : Marks the device node as a GPIO Controller. + - #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify flags. + See ../gpio/gpio.txt for more information. + - regulators: : List of child nodes that specify the regulator + initialization data. Child nodes must be named + after their hardware counterparts: dcdc[1-4] and + ldo[1-10]. Each child nodes is defined using the + standard binding for regulators. + +Example: + + pmic: tps65912@2d { + compatible = "ti,tps65912"; + reg = <0x2d>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + dcdc1 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/misc/bone_capemgr.txt b/Documentation/devicetree/bindings/misc/bone_capemgr.txt --- a/Documentation/devicetree/bindings/misc/bone_capemgr.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/misc/bone_capemgr.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,111 @@ +* Beaglebone cape manager driver + +Required properties: +- compatible: "ti,bone-capemgr" +- eeprom: phandle to the EEPROM baseboard. + The EEPROM framework interface is use to obtain the data. + +Required children nodes: + +- baseboardmaps: Contains nodes, which each of the them defines a mapping from + the baseboard EEPROM board-name ID to a DT friendly compatible + string. + + - board-name: The baseboard EEPROM board name, i.e. A335BONE for the + original beaglebone white. + - compatible-name: The DT friendly compatible string to be used for matching + compatible capes, i.e. "ti,beaglebone" + + + - nvmem-cells: Defines the phandles of the nvmem cells of the baseboard and the + slots. + - nvmem-cells: Defines the names of the nvmem cells. Required to have at + least a baseboard cell name. + + - #slots: Defines how many slots are there. + +- Example of a beaglebone cape-manager: + +bone_capemgr { + compatible = "ti,bone-capemgr"; + status = "okay"; + + nvmem-cell = <&baseboard_data + &cape0_data &cape1_data &cape2_data &cape3_data>; + nvmem-cell-names = "baseboard", "slot0", "slot1", "slot2", "slot3"; + + #slots = <4>; + + /* map board revisions to compatible definitions */ + baseboardmaps { + baseboard_beaglebone: board@0 { + board-name = "A335BONE"; + compatible-name = "ti,beaglebone"; + }; + + baseboard_beaglebone_black: board@1 { + board-name = "A335BNLT"; + compatible-name = "ti,beaglebone-black"; + }; + }; +}; + +The format of the cape to be loaded is in a standard overlay format with +the following root properties that are interpreted by the cape manager: + +Required properties: + - compatible: Should be compatible to the baseboard according to the + baseboard map value, i.e. "ti,beaglebone". + - part-numer: Should contain the part-number as stored in the EEPROM. + - version: Should contain a list of all the version that are supported + by the single cape dtbo, i.e. "00A1". + +Optional properties: + - exclusive-use: A string list which state the resources this cape requires. + No processing or matching to anything regarding the internal + kernel state is performed; it's purpose is to guard against + conflicts with other capes. + - priority: A priority to be assigned when loading a cape. A lower value + has higher priority. The purpose of the priority is to control + which cape is loaded first in case of a conflict. + +- Example of a serial cape: + +/dts-v1/; +/plugin/; +/ { + compatible = "ti,beaglebone", "ti,beaglebone-black"; + + /* identification */ + part-number = "BB-BONE-SERL-03"; + version = "00A1"; + + /* state the resources this cape uses */ + exclusive-use = + /* the pin header uses */ + "P9.21", /* uart2_txd */ + "P9.22", /* uart2_rxd */ + /* the hardware ip uses */ + "uart2"; + + fragment@0 { + target = <&am33xx_pinmux>; + __overlay__ { + bb_uart2_pins: pinmux_bb_uart2_pins { + pinctrl-single,pins = < + 0x150 0x21 /* spi0_sclk.uart2_rxd | MODE1 */ + 0x154 0x01 /* spi0_d0.uart2_txd | MODE1 */ + >; + }; + }; + }; + + fragment@1 { + target = <&uart2>; + __overlay__ { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bb_uart2_pins>; + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/misc/sram.txt b/Documentation/devicetree/bindings/misc/sram.txt --- a/Documentation/devicetree/bindings/misc/sram.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/misc/sram.txt 2016-05-11 13:31:53.189225170 -0400 @@ -39,6 +39,8 @@ of the kernel, e.g. by bootloader or userspace - label : the name for the reserved partition, if omitted, the label is taken from the node name excluding the unit address. +- map-exec : map range to allow code execution +- map-exec-nocache : map range to allow code execution and also non-cached Example: diff -Naur --no-dereference a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -12,6 +12,7 @@ Should be "ti,omap3-hsmmc", for OMAP3 controllers Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0 Should be "ti,omap4-hsmmc", for OMAP4 controllers + Should be "ti,dra7-hsmmc", for dra7 and dra72 controllers Should be "ti,am33xx-hsmmc", for AM335x controllers - ti,hwmods: Must be "mmc", n is controller instance starting 1 @@ -19,6 +20,11 @@ ti,dual-volt: boolean, supports dual voltage cards -supply: phandle to the regulator device tree node "supply-name" examples are "vmmc", "vmmc_aux" etc +pinctrl-names: Should be a list of pinctrl state names and can be "sdr104", +"hs200_1_8v", "ddr50", "sdr50", "sdr25", "sdr12", "hs", "ddr_1_8v" or +"default". +pinctrl-: Phandle referencing pin configuration of the sd/emmc controller. +See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt ti,non-removable: non-removable slot (like eMMC) ti,needs-special-reset: Requires a special softreset sequence ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed diff -Naur --no-dereference a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,57 @@ +* Cadence Quad SPI controller + +Required properties: +- compatible : Should be "cdns,qspi-nor". + TI K2G platform must contain "ti,k2g-qspi". +- reg : Contains two entries, each of which is a tuple consisting of a + physical address and length. The first entry is the address and + length of the controller register set. The second entry is the + address and length of the QSPI Controller data area. +- interrupts : Unit interrupt specifier for the controller interrupt. +- clocks : phandle to the Quad SPI clock. +- cdns,fifo-depth : Size of the data FIFO in words. +- cdns,fifo-width : Bus width of the data FIFO in bytes. +- cdns,trigger-address : 32-bit indirect AHB trigger address. + +Optional properties: +- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. + +Optional subnodes: +Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional +custom properties: +- cdns,read-delay : Delay for read capture logic, in clock cycles +- cdns,tshsl-ns : Delay in nanoseconds for the length that the master + mode chip select outputs are de-asserted between + transactions. +- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being + de-activated and the activation of another. +- cdns,tchsh-ns : Delay in nanoseconds between last bit of current + transaction and deasserting the device chip select + (qspi_n_ss_out). +- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low + and first bit transfer. + +Example: + + qspi: spi@ff705000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff705000 0x1000>, + <0xffa00000 0x1000>; + interrupts = <0 151 4>; + clocks = <&qspi_clk>; + cdns,is-decoded-cs; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + + flash0: n25q00@0 { + ... + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt 2016-05-11 13:31:53.189225170 -0400 @@ -13,7 +13,11 @@ Required properties: - - reg: The CS line the peripheral is connected to + - compatible: "ti,omap2-nand" + - reg: range id (CS number), base offset and length of the + NAND I/O space + - interrupt-parent: must point to gpmc node + - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount. Optional properties: @@ -35,7 +39,7 @@ "prefetch-polled" Prefetch polled mode (default) "polled" Polled mode, without prefetch - "prefetch-dma" Prefetch enabled sDMA mode + "prefetch-dma" Prefetch enabled DMA mode "prefetch-irq" Prefetch enabled irq mode - elm_id: use "ti,elm-id" instead @@ -44,6 +48,7 @@ locating ECC errors for BCHx algorithms. SoC devices which have ELM hardware engines should specify this device node in .dtsi Using ELM for ECC error correction frees some CPU cycles. + - rb-gpios: GPIO specifier for the ready/busy# pin. For inline partition table parsing (optional): @@ -55,20 +60,26 @@ gpmc: gpmc@50000000 { compatible = "ti,am3352-gpmc"; ti,hwmods = "gpmc"; - reg = <0x50000000 0x1000000>; + reg = <0x50000000 0x36c>; interrupts = <100>; gpmc,num-cs = <8>; gpmc,num-waitpins = <2>; #address-cells = <2>; #size-cells = <1>; - ranges = <0 0 0x08000000 0x2000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */ elm_id = <&elm>; + interrupt-controller; + #interrupt-cells = <2>; nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>; nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; ti,nand-xfer-type = "polled"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; diff -Naur --no-dereference a/Documentation/devicetree/bindings/net/keystone-netcp.txt b/Documentation/devicetree/bindings/net/keystone-netcp.txt --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/net/keystone-netcp.txt 2016-05-11 13:31:53.189225170 -0400 @@ -62,7 +62,9 @@ big endian mode with the DSP in little endian. NetCP device properties: Device specification for NetCP sub-modules. + 1Gb/10Gb (gbe/xgbe) ethernet switch sub-module specifications. +=================================================================== Required properties: - label: Must be "netcp-gbe" for 1Gb & "netcp-xgbe" for 10Gb. - compatible: Must be one of below:- @@ -72,22 +74,27 @@ "ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2) "ti,netcp-xgbe" for 10 GbE +- syscon-subsys: phandle to syscon node of the switch + subsystem registers. + +- syscon-pcsr: (10gbe only) phandle to syscon node of the + switch PCSR registers. + - reg: register location and the size for the following register regions in the specified order. - switch subsystem registers + - sgmii module registers - sgmii port3/4 module registers (only for NetCP 1.4) - switch module registers - - serdes registers (only for 10G) NetCP 1.4 ethss, here is the order - index #0 - switch subsystem registers + index #0 - sgmii module registers index #1 - sgmii port3/4 module registers index #2 - switch module registers NetCP 1.5 ethss 9 port, 5 port and 2 port - index #0 - switch subsystem registers + index #0 - sgmii module registers index #1 - switch module registers - index #2 - serdes registers - tx-channel: the navigator packet dma channel name for tx. - tx-queue: the navigator queue number associated with the tx dma channel. @@ -113,6 +120,10 @@ will only initialize these ports and attach PHY driver to them if needed. +- phys: phandles to serdes devices + see Documentation/devicetree/bindings/phy/ti-phy.txt + for Keystone SerDes device specificcations. + NetCP interface properties: Interface specification for NetCP sub-modules. Required properties: - rx-channel: the navigator packet dma channel name for rx. @@ -145,6 +156,43 @@ Example binding: +gbe_subsys: subsys@2090000 { + compatible = "syscon"; + reg = <0x02090000 0x100>; +}; + +gbe_serdes: phy@232a000 { + status = "ok"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x0232a000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + netcp: netcp@2000000 { reg = <0x2620110 0x8>; reg-names = "efuse"; @@ -163,10 +211,12 @@ ranges; gbe@90000 { label = "netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; + syscon-subsys = <&gbe_subsys>; + reg = <0x90100 0x200>, <0x90400 0x200>, <0x90800 0x700>; /* enable-ale; */ tx-queue = <648>; tx-channel = <8>; + phys = <&gbe_serdes>; interfaces { gbe0: interface-0 { @@ -219,3 +269,266 @@ }; }; }; + +Example bindings (10gbe): + +xgbe_subsys: subsys@2f00000 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00000 0x100>; +}; + +xgbe_pcsr: pcsr@2f00600 { + status = "disabled"; + compatible = "syscon"; + reg = <0x02f00600 0x100>; +}; + +xgbe_serdes: phy@231e000 { + status = "disabled"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-xgbe"; + reg = <0x0231e000 0x2000>; + link-rate-kbps = <10312500>; + num-lanes = <2>; + syscon-peripheral = <&xgbe_subsys>; + syscon-link = <&xgbe_pcsr>; + /*rx-force-enable;*/ + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcpx: netcpx@2f00000 { + status = "disabled"; + compatible = "ti,netcp-1.0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&clkxge>; + clock-names = "clk_xge"; + dma-coherent; + /* big-endian; */ + + ti,navigator-dmas = <&dma_xgbe 0>, + <&dma_xgbe 8>, + <&dma_xgbe 0>; + ti,navigator-dma-names = "xnetrx0", "xnetrx1", "xnettx"; + + netcp-devices { + #address-cells = <1>; + #size-cells = <1>; + ranges; + xgbe@2f00000 { + label = "netcp-xgbe"; + compatible = "ti,netcp-xgbe"; + syscon-subsys = <&xgbe_subsys>; + syscon-pcsr = <&xgbe_pcsr>; + reg = <0x02f00100 0x200>, <0x02f01000 0xb00>; + /* enable-ale; */ + tx-queue = <692>; + tx-channel = "xnettx"; + phys = <&xgbe_serdes>; + + interfaces { + xgbe0: interface-0 { + slave-port = <0>; + link-interface = <11>; /* MAC_MAC */ + }; + xgbe1: interface-1 { + slave-port = <1>; + link-interface = <11>; + }; + }; + }; + }; + + netcp-interfaces { + interface-0 { + rx-channel = "xnetrx0"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <532>; + tx-completion-queue = <534>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe0>; + + }; + interface-1 { + rx-channel = "xnetrx1"; + rx-pool = <2048 12>; /* num_desc region-id */ + tx-pool = <1024 12>; /* num_desc region-id */ + rx-queue-depth = <1024 1024 0 0>; + rx-buffer-size = <1536 4096 0 0>; + rx-queue = <533>; + tx-completion-queue = <535>; + efuse-mac = <0>; + netcp-xgbe = <&xgbe1>; + }; + }; +}; + +Packet Accelarator sub-module specifications. +============================================= + +Note: The bindings are experimental and may change while feature development +is in progress. However attempt will be made to make changes backward +compatible if possible. + +Required properties: +- label: Must be "netcp-pa" for PA on K2H/K SoC + Must be "netcp-pa2" for PA2 on K2L/E SoCs + +- compatible: Must be one of below:- + "ti,netcp-pa" for PA + "ti,netcp-pa2" for PA2 + +- reg: register location and the size for the following register + regions in the specified order. + + Packet Accelarator (PA) + - Mailbox + - Packet ID + - LUT2 + - streaming switch + - Control + - Timers + - Statistics + - IRAM + - SRAM + + Packet Accelarator 2 (PA2) + - Mailbox + - RA bridge + - Thread mapper + - RA + - Statistics regs + - Statistics block + - cluster memory + +- clusters: Contain cluster specific configuration + reg: cluster ID + tx-queue: Queue for sending commands/data to a cluster + tx-channel: knav Tx channel associated with the queue + +- tx-cmd-pool: specifies the number of descriptors to be used & the region-id + for creating the tx descriptor pool for tx channnels. +- rx-cmd-rsp-chan: rx channel name for receiving responses from + PDSPs +- rx-cmd-rsp-pool: specifies the number of descriptors to be used + & the region-id for creating the rx descriptor + pool for rx rsp channel. +- rx-cmd-rsp-queue-depth: number of descriptors in each of the free + descriptor queue (FDQ) for the pktdma Rx flow. + There can be at present a maximum of 4 queues + per Rx flow. +- rx-cmd-rsp-buffer-size: Size of the buffers allocated for the desc + in each rx response FDQs. +- mac-lut-ranges: LUT range of index used by PA device for MAC + rules. LUT is shared across different software + components in the system and this range is + reserved for PA device. +- rx-route: Rx Queue / Flow base used by PA. They should + match with rx-channel queue / flow for netcp + ethernet interface when PA is in the rx path. +- netcp-interfaces: interface specific configuration for PA. + slave-port cpsw slave port number for the interface +Optional properties:- + +- ip-lut-ranges: LUT range of index reserved for PA device. + Used for rx checksum handling. +- netcp-interfaces: interface specific configuration for PA. + rx-channel: rx channel name for ethernet interface when PA + is in the rx path for data. Uses a different + flow id when PA is added to the rx path. +- disable-hw-timestamp: Disable hw timestamp feature. + +Example: + +PA is a netcp device and appears under netcp-devices node. Example bindings for +PA device is provided below. + + netcp-devices { + + + + pa@0 { + #address-cells = <1>; + #size-cells = <1>; + label = "netcp-pa"; + compatible = "ti,netcp-pa"; + + reg = <0 0x60>, /* Mailbox */ + <0x400 0x10>, /* Packet ID */ + <0x500 0x40>, /* LUT2 */ + <0x604 0x4>, /* streaming switch */ + <0x1000 0x600>, /* Control */ + <0x3000 0x600>, /* Timers */ + <0x6000 0x100>, /* Statistics */ + <0x10000 0x30000>, /* Iram */ + <0x40000 0x8000>; /* Sram */ + + mac-lut-ranges = <0 43 56 63>; + /* Static reservation in LUT-1 (outer IP) + * used by driver to add IP rules for Rx checksum + * offload. + */ + ip-lut-ranges = <61 63>; + /* base queue, base flow. Should match with that + * for netrx0 + */ + rx-route = <8704 22>; + tx-cmd-pool = <256 12>; + /* rx command pool */ + rx-cmd-rsp-pool = <256 12>; + /* rx channel name for command response */ + rx-cmd-rsp-chan = "pa-cmd-rsp"; + rx-cmd-rsp-queue-depth = <128 32 0 0>; + rx-cmd-rsp-buffer-size = <128 512 0 0>; + + /* PA clusters that does packet processing */ + clusters { + #address-cells = <1>; + #size-cells = <0>; + cluster@0 { + reg = <0>; + tx-queue = <640>; + tx-channel = "pa-cl0"; + }; + + cluster@1 { + reg = <1>; + tx-queue = <641>; + tx-channel = "pa-cl1"; + }; + + cluster@5 { + reg = <5>; + tx-queue = <645>; + tx-channel = "pa-cl5"; + }; + }; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt --- a/Documentation/devicetree/bindings/opp/opp.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/opp/opp.txt 2016-05-11 13:31:53.189225170 -0400 @@ -45,21 +45,10 @@ phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. -Devices may want to choose OPP tables at runtime and so can provide a list of -phandles here. But only *one* of them should be chosen at runtime. This must be -accompanied by a corresponding "operating-points-names" property, to uniquely -identify the OPP tables. - If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". -Optional properties: -- operating-points-names: Names of OPP tables (required if multiple OPP - tables are present), to uniquely identify them. The same list must be present - for all the CPUs which are sharing clock/voltage rails and hence the OPP - tables. - * OPP Table Node This describes the OPPs belonging to a device. This node can have following @@ -100,6 +89,14 @@ Entries for multiple regulators must be present in the same order as regulators are specified in device's DT node. +- opp-microvolt-: Named opp-microvolt property. This is exactly similar to + the above opp-microvolt property, but allows multiple voltage ranges to be + provided for the same OPP. At runtime, the platform can pick a and + matching opp-microvolt- property will be enabled for all OPPs. If the + platform doesn't pick a specific or the doesn't match with any + opp-microvolt- properties, then opp-microvolt property shall be used, if + present. + - opp-microamp: The maximum current drawn by the device in microamperes considering system specific parameters (such as transients, process, aging, maximum operating temperature range etc.) as necessary. This may be used to @@ -112,6 +109,9 @@ for few regulators, then this should be marked as zero for them. If it isn't required for any regulator, then this property need not be present. +- opp-microamp-: Named opp-microamp property. Similar to + opp-microvolt- property, but for microamp instead. + - clock-latency-ns: Specifies the maximum possible transition latency (in nanoseconds) for switching to this OPP from any other OPP. @@ -123,6 +123,26 @@ - opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in the table should have this. +- opp-supported-hw: This enables us to select only a subset of OPPs from the + larger OPP table, based on what version of the hardware we are running on. We + still can't have multiple nodes with the same opp-hz value in OPP table. + + It's an user defined array containing a hierarchy of hardware version numbers, + supported by the OPP. For example: a platform with hierarchy of three levels + of versions (A, B and C), this field should be like , where X + corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z + corresponds to version hierarchy C. + + Each level of hierarchy is represented by a 32 bit value, and so there can be + only 32 different supported version per hierarchy. i.e. 1 bit per version. A + value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy + level. And a value of 0x00000000 will disable the OPP completely, and so we + never want that to happen. + + If 32 values aren't sufficient for a version hierarchy, than that version + hierarchy can be contained in multiple 32 bit values. i.e. in the + above example, Z1 & Z2 refer to the version hierarchy Z. + - status: Marks the node enabled/disabled. Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. @@ -157,20 +177,20 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; - opp01 { + opp@1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <980000 1000000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; - opp02 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; clock-latency-ns = <290000>; @@ -236,20 +256,20 @@ * independently. */ - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; - opp01 { + opp@1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <980000 1000000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; - opp02 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; opp-microamp = <90000; @@ -312,20 +332,20 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000 975000 985000>; opp-microamp = <70000>; clock-latency-ns = <300000>; opp-suspend; }; - opp01 { + opp@1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <980000 1000000 1010000>; opp-microamp = <80000>; clock-latency-ns = <310000>; }; - opp02 { + opp@1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1025000>; opp-microamp = <90000>; @@ -338,20 +358,20 @@ compatible = "operating-points-v2"; opp-shared; - opp10 { + opp@1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1045000 1050000 1055000>; opp-microamp = <95000>; clock-latency-ns = <400000>; opp-suspend; }; - opp11 { + opp@1400000000 { opp-hz = /bits/ 64 <1400000000>; opp-microvolt = <1075000>; opp-microamp = <100000>; clock-latency-ns = <400000>; }; - opp12 { + opp@1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1010000 1100000 1110000>; opp-microamp = <95000>; @@ -378,7 +398,7 @@ compatible = "operating-points-v2"; opp-shared; - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000>, /* Supply 0 */ <960000>, /* Supply 1 */ @@ -391,7 +411,7 @@ /* OR */ - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000 975000 985000>, /* Supply 0 */ <960000 965000 975000>, /* Supply 1 */ @@ -404,7 +424,7 @@ /* OR */ - opp00 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <970000 975000 985000>, /* Supply 0 */ <960000 965000 975000>, /* Supply 1 */ @@ -417,7 +437,8 @@ }; }; -Example 5: Multiple OPP tables +Example 5: opp-supported-hw +(example: three level hierarchy of versions: cuts, substrate and process) / { cpus { @@ -426,40 +447,73 @@ ... cpu-supply = <&cpu_supply> - operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; - operating-points-names = "slow", "fast"; + operating-points-v2 = <&cpu0_opp_table_slow>; }; }; - cpu0_opp_table_slow: opp_table_slow { + opp_table { compatible = "operating-points-v2"; status = "okay"; opp-shared; - opp00 { + opp@600000000 { + /* + * Supports all substrate and process versions for 0xF + * cuts, i.e. only first four cuts. + */ + opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF> opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 915000 925000>; ... }; - opp01 { + opp@800000000 { + /* + * Supports: + * - cuts: only one, 6th cut (represented by 6th bit). + * - substrate: supports 16 different substrate versions + * - process: supports 9 different process versions + */ + opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0> opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000 915000 925000>; + ... + }; + }; +}; + +Example 6: opp-microvolt-, opp-microamp-: +(example: device with two possible microvolt ranges: slow and fast) + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; ... + + operating-points-v2 = <&cpu0_opp_table>; }; }; - cpu0_opp_table_fast: opp_table_fast { + cpu0_opp_table: opp_table0 { compatible = "operating-points-v2"; - status = "okay"; opp-shared; - opp10 { + opp@1000000000 { opp-hz = /bits/ 64 <1000000000>; - ... + opp-microvolt-slow = <900000 915000 925000>; + opp-microvolt-fast = <970000 975000 985000>; + opp-microamp-slow = <70000>; + opp-microamp-fast = <71000>; }; - opp11 { - opp-hz = /bits/ 64 <1100000000>; - ... + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-slow = <900000 915000 925000>, /* Supply vcc0 */ + <910000 925000 935000>; /* Supply vcc1 */ + opp-microvolt-fast = <970000 975000 985000>, /* Supply vcc0 */ + <960000 965000 975000>; /* Supply vcc1 */ + opp-microamp = <70000>; /* Will be used for both slow/fast */ }; }; }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt --- a/Documentation/devicetree/bindings/phy/ti-phy.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt 2016-05-11 13:31:53.189225170 -0400 @@ -31,6 +31,10 @@ Required properties: - compatible: Should be "ti,omap-usb2" + Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on + DRA7x + Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY + in DRA7x - reg : Address and length of the register set for the device. - #phy-cells: determine the number of cells that should be given in the phandle while referencing this phy. @@ -40,10 +44,14 @@ * "wkupclk" - wakeup clock. * "refclk" - reference clock (optional). -Optional properties: +Deprecated properties: - ctrl-module : phandle of the control module used by PHY driver to power on the PHY. +Recommended properies: +- syscon-phy-power : phandle/offset pair. Phandle to the system control + module and the register offset to power on/off the PHY. + This is usually a subnode of ocp2scp to which it is connected. usb2phy@4a0ad080 { @@ -77,14 +85,22 @@ * "div-clk" - apll clock Optional properties: - - ctrl-module : phandle of the control module used by PHY driver to power on - the PHY. - id: If there are multiple instance of the same type, in order to differentiate between each instance "id" can be used (e.g., multi-lane PCIe PHY). If "id" is not provided, it is set to default value of '1'. - syscon-pllreset: Handle to system control region that contains the CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy. + - syscon-pcs : phandle/offset pair. Phandle to the system control module and the + register offset to write the PCS delay value. + +Deprecated properties: + - ctrl-module : phandle of the control module used by PHY driver to power on + the PHY. + +Recommended properies: + - syscon-phy-power : phandle/offset pair. Phandle to the system control + module and the register offset to power on/off the PHY. This is usually a subnode of ocp2scp to which it is connected. @@ -115,4 +131,243 @@ clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; #phy-cells = <0>; + +TI Keystone SerDes PHY +====================== + +Required properties: + - compatible: should be one of + * "ti,keystone-serdes-gbe" + * "ti,keystone-serdes-xgbe" + * "ti,keystone-serdes-pcie" + - reg: + * base address and length of the SerDes register set + - #phy-cells: + * From the generic phy bindings, must be 0; + - num-lanes: + * Number of lanes in SerDes. + +Optional properties: + - syscon-peripheral: + * Handle to the subsystem register region of the peripheral + inside which the SerDes exists. Required for 10gbe. + - syscon-link: + * Handle to the Link register region of the peripheral inside + which the SerDes exists. Example: it is the PCSR register + region in the case of 10gbe. Required for 10gbe. + - rx-force-enable: + * Include this property if receiver attenuation and boost are + to be configured with specific values defined in rx-force. + - link-rate-kbps: + * SerDes link rate to be configured, in kbps. + + +For gbe and 10gbe SerDes, it is optional to represent each lane as +a sub-node, which can be enabled or disabled individually using +the "status" property. If a lane is not represented by a node, the +lane is disabled. + +Required properties (lane sub-node): + - reg: + * lane number + +Optional properties (lane sub-node): + - control-rate: + * Lane control rate + 0: full rate + 1: half rate + 2: quarter rate + - rx-start: + * Initial lane rx equalizer attenuation and boost configurations. + * Must be array of 2 integers. + - rx-force: + * Forced lane rx equalizer attenuation and boost configurations. + * Must be array of 2 integers. + - tx-coeff: + * Lane c1, c2, cm, attenuation and regulator output voltage + configurations. + * Must be array of 5 integers. + - loopback: + * Include this property to enable loopback at the SerDes + lane level. + +Example for Keystone K2E GBE: +----------------------------- + +gbe_serdes0: phy@232a000 { + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x0232a000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +gbe_serdes1: phy@2324000 { + #phy-cells = <0>; + compatible = "ti,keystone-serdes-gbe"; + reg = <0x02324000 0x2000>; + link-rate-kbps = <1250000>; + num-lanes = <4>; + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <2>; /* quart */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <0 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +netcp: netcp@24000000 { + ... + + netcp-devices { + ... + + gbe@200000 { /* ETHSS */ + ... + + phys = <&gbe_serdes0>, <&gbe_serdes1>; + + ... + }; + + ... + }; +}; + +Example for Keystone PCIE: +-------------------------- + + pcie0_phy: phy@2320000 { + #phy-cells = <0>; + compatible = "ti,keystone-serdes-pcie"; + reg = <0x02320000 0x4000>; + link-rate-kbps = <5000000>; + num-lanes = <2>; + }; + + +Then the PHY can be used in PCIe controller node as + + pcie0: pcie@21800000 { + ... + + phys = <&pcie0_phy>; + } + +Example for K2E 10GBE: +---------------------- + +Define the syscon regmaps for 10gbe subsystem: + +xgbe_subsys: subsys@2f00000 { + status = "ok"; + compatible = "syscon"; + reg = <0x02f00000 0x100>; +}; + +Define the syscon regmaps for 10gbe pcsr: + +xgbe_pcsr: pcsr@2f00000 { + status = "ok"; + compatible = "syscon"; + reg = <0x02f00600 0x100>; +}; + +Define the 10gbe SerDes node: + +xgbe_serdes: phy@231e000 { + status = "ok"; + #phy-cells = <0>; + compatible = "ti,keystone-serdes-xgbe"; + reg = <0x0231e000 0x2000>; + link-rate-kbps = <10312500>; + num-lanes = <2>; + syscon-peripheral = <&xgbe_subsys>; + syscon-link = <&xgbe_pcsr>; + lanes { + #address-cells = <1>; + #size-cells = <0>; + lane@0 { + /*loopback;*/ + reg = <0>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + lane@1 { + /*loopback;*/ + reg = <1>; + control-rate = <0>; /* full */ + rx-start = <7 5>; + rx-force = <1 1>; + tx-coeff = <2 0 0 12 4>; + /* c1 c2 cm att vreg */ + }; + }; +}; + +Then the 10gbe SerDes PHY can be used in the 10gbe switch node: + +netcpx: netcpx@2f00000 { + + ... + + netcp-devices { + + ... + + xgbe@2f00000 { + + ... + + syscon-subsys = <&xgbe_subsys>; + syscon-pcsr = <&xgbe_pcsr>; + phys = <&xgbe_serdes>; + + ... + }; + }; + + ... + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/pinctrl/ti,iodelay-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay-pinctrl.txt --- a/Documentation/devicetree/bindings/pinctrl/ti,iodelay-pinctrl.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/pinctrl/ti,iodelay-pinctrl.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,86 @@ +Texas Instruments I/O Delay module configuration pinctrl definition + +Used in conjunction with Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt + +Required Properties: +- compatible: Should be: + "ti,dra7-iodelay" - I/O delay configuration for DRA7 +- reg - must be the register address range of IODelay module +- #address-cells = <1>; +- #size-cells = <0>; + +Important note: Use of "ti,dra7-iodelay" compatible definition need to be +carefully evaluated due to the expectation of glitch during configuration. + +Example: + +dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; +}; + +Configuration definition follows similar model as the pinctrl-single: +The groups of pin configuration are defined under "pinctrl-single,pins" + +&dra7_iodelay_core { + mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { + pinctrl-single,pins = < + 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + >; + }; +}; + +Usage in conjunction with pinctrl single: + +For a complete description of the pins both the regular muxing as well as the +iodelay configuration is necessary. For example: + +&dra7_pmx_core { + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; + +&dra7_iodelay_core { + mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { + pinctrl-single,pins = < + 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */ + 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */ + 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */ + 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */ + 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */ + 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */ + 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */ + 0x1ec (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_IN */ + 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */ + 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default &mmc2_iodelay_3v3_conf>; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt --- a/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,18 @@ +* OMAP PWM for dual-mode timers + +Required properties: +- compatible: Shall contain "ti,omap-dmtimer-pwm". +- ti,timers: phandle to PWM capable OMAP timer. See arm/omap/timer.txt for info + about these timers. +- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of + the cells format. + +Optional properties: +- ti,prescaler: Should be a value between 0 and 7, see the timers datasheet + +Example: + pwm9: dmtimer-pwm@9 { + compatible = "ti,omap-dmtimer-pwm"; + ti,timers = <&timer9>; + #pwm-cells = <3>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt 2016-05-11 13:31:53.189225170 -0400 @@ -4,6 +4,7 @@ - compatible: Must be "ti,-ecap". for am33xx - compatible = "ti,am33xx-ecap"; for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for dra7xx - compatible = "ti,dra7xx-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -19,7 +20,6 @@ compatible = "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x48300100 0x80>; - ti,hwmods = "ecap0"; }; ecap0: ecap@0 { /* ECAP on da850 */ @@ -27,3 +27,10 @@ #pwm-cells = <3>; reg = <0x306000 0x80>; }; + +ecap0: ecap@4843e100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt 2016-05-11 13:31:53.189225170 -0400 @@ -4,26 +4,36 @@ - compatible: Must be "ti,-ehrpwm". for am33xx - compatible = "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. - reg: physical base address and size of the registers map. Optional properties: -- ti,hwmods: Name of the hwmod associated to the EHRPWM: - "ehrpwm", being the 0-based instance number from the HW spec +- clocks: Reference to the ehrpwm's tb clock +- clock-names : must contain "tbclk" Example: -ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */ +ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */ compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x100>; - ti,hwmods = "ehrpwm0"; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; }; -ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */ +ehrpwm0: pwm@01f00000 { /* EHRPWM on da850 */ compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; }; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra7xx */ + compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt 2016-05-11 13:31:53.189225170 -0400 @@ -1,7 +1,9 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss" + for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss" - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -29,3 +31,14 @@ /* child nodes go here */ }; + +epwmss0: epwmss@4843e000 { /* On DRA7xx */ + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt --- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt 2016-05-11 13:31:53.189225170 -0400 @@ -1,5 +1,12 @@ * palmas regulator IP block devicetree bindings +The tps659038 for the AM57x class have OTP spins that +have different part numbers but the same functionality. There +is not a need to add the OTP spins to the palmas driver. The +spin devices should use the tps659038 as it's compatible value. +This is the list of those devices: +tps659037 + Required properties: - compatible : Should be from the list ti,twl6035-pmic @@ -8,6 +15,7 @@ ti,tps65913-pmic ti,tps65914-pmic ti,tps65917-pmic + ti,tps659038-pmic and also the generic series names ti,palmas-pmic - interrupt-parent : The parent interrupt controller which is palmas. diff -Naur --no-dereference a/Documentation/devicetree/bindings/remoteproc/omap-remoteproc.txt b/Documentation/devicetree/bindings/remoteproc/omap-remoteproc.txt --- a/Documentation/devicetree/bindings/remoteproc/omap-remoteproc.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/remoteproc/omap-remoteproc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,145 @@ +OMAP4+ Remoteproc Devices +========================= + +The OMAP family of SoCs usually have one or more slave processor sub-systems +that are used to offload some of the processor-intensive tasks, or to manage +other hardware accelerators, for achieving various system level goals. + +The processor cores in the sub-system are usually behind an IOMMU, and may +contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2 +caches, an Interrupt Controller, a Cache Controller etc. + +The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor +sub-system. The DSP processor sub-system can contain any of the TI's C64x, +C66x or C67x family of DSP cores as the main execution unit. The IPU processor +sub-system usually contains either a Dual-Core Cortex-M3 or Dual-Core Cortex-M4 +processors. + +Remote Processor Node: +====================== +Each remote processor sub-system is represented as a single DT node. Each node +has a number of required or optional properties that enable the OS running on +the host processor (MPU) to perform the device management of the remote +processor and to communicate with the remote processor. The various properties +can be classified as constant or variable. The constant properties are dictated +by the SoC and does not change from one board to another having the same SoC. +Examples of constant properties include 'iommus', 'reg'. The variable properties +are dictated by the system integration aspects such as memory on the board, or +configuration used within the corresponding firmware image. Examples of variable +properties include 'mboxes', 'memory-region', 'timers', 'watchdog-timers' etc. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,omap4-dsp" for DSPs on OMAP4 SoCs + "ti,omap5-dsp" for DSPs on OMAP5 SoCs + "ti,dra7-dsp" for DSPs on DRA7xx SoCs + "ti,omap4-ipu" for IPUs on OMAP4 SoCs + "ti,omap5-ipu" for IPUs on OMAP5 SoCs + "ti,dra7-ipu" for IPUs on DRA7xx SoCs + +- ti,hwmods: Name of the hwmod associated with the remoteproc device + +- iommus: phandles to OMAP IOMMU nodes, that need to be programmed + for this remote processor to access any external RAM memory or + other peripheral device address spaces. This property usually + has only a single phandle. Multiple phandles are used only in + cases where the sub-system has different ports for different + sub-modules within the processor sub-system (eg: DRA7 DSPs), + and need the same programming in both the MMUs. + +- mboxes: OMAP Mailbox specifier denoting the sub-mailbox, to be used for + communication with the remote processor. The specifier format is + as per the bindings, + Documentation/devicetree/bindings/mailbox/omap-mailbox.txt + This property should match with the sub-mailbox node used in + the firmware image. + +Optional properties: +-------------------- +Some of these properties are mandatory on some SoCs, and some are optional +depending on the configuration of the firmware image to be executed on the +remote processor. The conditions are mentioned for each property. + +The following are the optional properties: +- reg: Address space for any remoteproc memories present on + the SoC. Should contain an entry for each value in + 'reg-names'. These are mandatory for all DSP and IPU + processors that have them (OMAP4/OMAP5 DSPs do not have + any RAMs) + +- reg-names: Required names for each of the address spaces defined in + the 'reg' property. Should contain a string from among + the following names, each representing the corresponding + internal RAM memory region, + "l2ram" for L2 RAM, + "l1pram" for L1 Program RAM Memory/Cache, + "l1dram" for L1 Data RAM Memory/Cache, + + All devices may not have all the above memories. + +- syscon-bootreg: Should be a pair of the phandle to the System Control + Configuration region that contains the boot address + register, and the register offset of the boot address + register within the System Control module. This property + is required for all the DSP instances on OMAP4, OMAP5 + and DRA7xx SoCs. + +- memory-region: phandle to the reserved memory node to be associated + with the remoteproc device. The reserved memory node + should be a CMA memory node, and should be defined as + per the bindings, + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +- mbox-names: Optional names for the OMAP mailbox specifiers mentioned + in the 'mboxes' property, one per specifier value + +- timers: One or more phandles to OMAP DMTimer nodes, that serve + as System/Tick timers for the OS running on the remote + processors. This will usually be a single timer if the + processor sub-system is running in SMP mode, or one per + core in the processor sub-system. + + This property is mandatory on remote processors requiring + external tick wakeup, and to support Power Management + features. The timers to be used should match with the + timers used in the firmware image. + +- watchdog-timers: One or more phandles to OMAP DMTimer nodes, used to + serve as Watchdog timers for the processor cores. This + will usually be one per executing processor core, even + if the processor sub-system is running a SMP OS. + + The timers to be used should match with the watchdog + timers used in the firmware image. + +- ti,rproc-standby-info: Standby data for the remote processor. This is + mandatory to support Power Management for the OMAP + remoteprocs, and should contain the address containing + the module standby status. + +Example: +-------- + +/* OMAP4 DSP node in SoC DTS file */ +ocp { + dsp: dsp { + compatible = "ti,omap4-dsp"; + ti,hwmods = "dsp"; + syscon-bootreg = <&scm_conf 0x304>; + iommus = <&mmu_dsp>; + mboxes = <&mailbox &mbox_dsp>; + ti,rproc-standby-info = <0x4a004420>; + status = "disabled"; + }; +}; + +/* OMAP4 DSP node additional fields in a Board DTS file */ +&dsp { + status = "okay"; + memory-region = <&dsp_cma_pool>; + timers = <&timer5>; + watchdog-timers = <&timer6>; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt --- a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,152 @@ +TI Keystone DSP devices +======================= + +Binding status: Unstable - Subject to changes for using common shared memories + +The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core +sub-systems that are used to offload some of the processor-intensive tasks or +algorithms, for achieving various system level goals. + +The processor cores in the sub-system usually contain additional sub-modules +like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory +controller, a dedicated local power/sleep controller etc. The DSP processor +core in Keystone 2 SoCs is usually a TMS320C66x CorePac processor. + +DSP Device Node: +================ +Each DSP Core sub-system is represented as a single DT node. Each node has a +number of required or optional properties that enable the OS running on the +host processor (ARM CorePac) to perform the device management of the remote +processor and to communicate with the remote processor. + +Required properties: +-------------------- +The following are the mandatory properties: + +- compatible: Should be one of the following, + "ti,k2hk-dsp" for DSPs on Keystone2 Hawking/Kepler SoCs + "ti,k2l-dsp" for DSPs on Keystone2 Lamarr SoCs + "ti,k2e-dsp" for DSPs on Keystone2 Edison SoCs + "ti,k2g-dsp" for DSPs on Keystone2 Galileo SoCs + +- reg: Should contain an entry for each value in 'reg-names'. + Each entry should have the memory region's start address + and the size of the region, the representation matching + the parent node's '#address-cells' and '#size-cells' values. + +- reg-names: Should contain strings with the following names, each + representing a specific internal memory region, and + should be defined in this order, + "l2sram", "l1pram", "l1dram" + +- clocks: Should contain the device's input clock, and should be + defined as per the bindings in, + Documentation/devicetree/bindings/clock/keystone-gate.txt + for K2HK/K2L/K2E SoCs or, + Documentation/devicetree/bindings/clock/ti,sci-clk.txt + for K2G SoC + +- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device + State Control node, and the register offset of the DSP + boot address register within that node's address space. + +- resets: Should contain the phandle to the reset controller node + managing the resets for this device, and a reset + specifier. Please refer to either of the following reset + bindings for the reset argument specifier as per SoC, + Documentation/devicetree/bindings/reset/reset/syscon-reset.txt + for K2HK/K2L/K2E SoCs or, + Documentation/devicetree/bindings/reset/reset/ti,sci-reset.txt + for K2G SoC + +- interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller + IP node that is used by the ARM CorePac processor to + receive interrupts from the DSP remote processors. See + Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt + for details. + +- interrupts: Should contain an entry for each value in 'interrupt-names'. + Each entry should have the interrupt source number used by + the remote processor to the host processor. The values should + follow the interrupt-specifier format as dictated by the + 'interrupt-parent' node. The purpose of each is as per the + description in the 'interrupt-names' property. + +- interrupt-names: Should contain strings with the following names, each + representing a specific interrupt, + "vring" - interrupt for virtio based IPC + "exception" - interrupt for exception notification + +- kick-gpio: Should specify the gpio device needed for the virtio IPC + stack. This will be used to interrupt the remote processor, + and should be defined as per the bindings in, + Documentation/devicetree/bindings/gpio/gpio.txt + +Optional properties: +-------------------- + +- power-domains: _required_ property only for Keystone 2 Galileo SoC. + Should contain a phandle to a PM domain provider node, + and a PM domain specifier as defined by the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + +- memory-region: phandle to the reserved memory node to be associated + with the remoteproc device. The reserved memory node + can be a CMA memory node, and should be defined as + per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + +Examples: +--------- + +1. + /* K2HK DSP node in SoC DTS file */ + soc { + dsp0: dsp0 { + compatible = "ti,k2hk-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + clocks = <&clkgem0>; + ti,syscon-dev = <&devctrl 0x40>; + resets = <&pscrst 0>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + }; + + /* K2HK EVM Board file */ + &dsp0 { + memory-region = <&dsp_common_cma_pool>; + }; + +2. + /* K2G DSP node in SoC DTS file */ + soc { + dsp0: dsp0 { + compatible = "ti,k2g-dsp"; + reg = <0x10800000 0x00100000>, + <0x10e00000 0x00008000>, + <0x10f00000 0x00008000>; + reg-names = "l2sram", "l1pram", "l1dram"; + power-domains = <&k2g_pds K2G_DEV_CGEM0>; + clocks = <&k2g_clks K2G_DEV_CGEM0 0>; + ti,syscon-dev = <&devctrl 0x40>; + resets = <&k2g_reset K2G_DEV_CGEM0 K2G_DEV_CGEM0_DSP0_RESET>; + interrupt-parent = <&kirq0>; + interrupts = <0 8>; + interrupt-names = "vring", "exception"; + kick-gpio = <&dspgpio0 27 0>; + }; + + }; + + /* K2G EVM Board file */ + &dsp0 { + memory-region = <&dsp_common_cma_pool>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/remoteproc/ti,pruss-remoteproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,pruss-remoteproc.txt --- a/Documentation/devicetree/bindings/remoteproc/ti,pruss-remoteproc.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/remoteproc/ti,pruss-remoteproc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,211 @@ +PRU-ICSS on TI SoCs +=================== + +Binding status: Unstable - Subject to changes to account for all sub-modules + +The Programmable Real-Time Unit and Industrial Communication Subsystem +(PRU-ICSS) is present on various TI SoCs such as AM335x or AM437x. A +PRUSS consists of dual 32-bit RISC cores (Programmable Real-Time Units, +or PRUs), shared RAM, data and instruction RAMs, some internal peripheral +modules to facilitate industrial communication, and an interrupt controller. +The programmable nature of the PRUs provide flexibility to implement custom +peripheral interfaces, fast real-time responses, or specialized data handling. +The common peripheral modules include the following, + - an Ethernet MII_RT module with two MII ports + - an MDIO port to control external Ethernet PHYs + - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial + Ethernet functions + - an Enhanced Capture Module (eCAP) + - an Industrial Ethernet Timer with 7/9 capture and 16 compare events + - a 16550-compatible UART to support PROFIBUS + +A PRU-ICSS subsystem can have up to three shared data memories. A PRU core +acts on a primary Data RAM (there are usually 2 Data RAMs) at its address +0x0, but also has access to a secondary Data RAM (primary to the other PRU +core) at its address 0x2000. A shared Data RAM, if present, can be accessed +by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are +common to both the PRU cores. Each PRU core also has a private instruction RAM, +and specific register spaces for Control and Debug functionalities. + + +PRU-ICSS Parent Node +===================== +Each PRU-ICSS subsystem instance is represented as a node with +the individual PRU processor cores, an INTC node and an MDIO node +represented as child nodes within the parent PRUSS node. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3352-pruss" for AM335x family of SoCs + "ti,am4372-pruss" for AM437x family of SoCs + "ti,am5728-pruss" for AM57xx family of SoCs +- ti,hwmods : name of the hwmod associated with the PRUSS instance +- reg : base address and size for each of the sub-modules as + mentioned in reg-names, and in the same order as the + reg-names +- reg-names : should contain a string from among the following names, + each representing a specific sub-module. A PRU-ICSS may + not have all of the Data RAMs. The binding is agnostic + of the order of these reg-names + "dram0" for Data RAM0, + "dram1" for Data RAM1, + "shrdram2" for Shared Data RAM, + "intc" for INTC sub-module, + "cfg" for CFG sub-module, + "iep" for IEP sub-module, + "mii_rt" for MII-RT sub-module, +- #address-cells : should be 1 +- #size-cells : should be 1 +- ranges : no specific range translations required, child nodes have the + same address view as the parent, so should be mentioned without + any value for the property + + +PRUSS INTC Child Node +====================== +Each PRUSS has a single interrupt controller instance that is common to both +the PRU cores. Each interrupt controller can detect 64 input events which are +then mapped to 10 possible output interrupts through two levels of mapping. The +input events can be triggered by either the PRUs and/or various other PRUSS +internal and external peripherals. The first 2 output interrupts are fed +exclusively to the internal PRU cores, with the remaining 8 connected to +external interrupt controllers including the MPU. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3352-pruss-intc" for AM335x family of SoCs + "ti,am4372-pruss-intc" for AM437x family of SoCs + "ti,am5728-pruss-intc" for AM57xx family of SoCs +- interrupts : all the interrupts generated towards the main host + processor in the SoC. The format depends on the + interrupt specifier for the particular SoC's MPU + parent interrupt controller +- interrupt-names : should use one of the following names for each + interrupt, the name should match the corresponding + host interrupt number, + "host2", "host3", "host4", "host5", "host6", + "host7", "host8" or "host9" + NOTE: AM437x SoCs do not have "host7" interrupt + connected to MPU +- interrupt-controller : mark this node as an interrupt controller +- #interrupt-cells : should be 1. Client users shall use the PRU System + event number (the interrupt source that the client + is interested in) as the value of the interrupts + property in their node + + +PRU Child Node +=============== +Each PRUSS has dual PRU cores, each represented by a PRU child node. Each node +can optionally be rendered inactive by using the standard DT string property, +"status". + +Each PRU child node must either be named "pru0" or "pru1", for the first and +and second PRUs respectively. + +Required Properties: +-------------------- +- compatible : should be + "ti,am3352-pru" for AM335x family of SoCs + "ti,am4372-pru" for AM437x family of SoCs + "ti,am5728-pru" for AM57xx family of SoCs +- reg : base address and size for each of the 3 sub-module address + spaces as mentioned in reg-names, and in the same order as + the reg-names +- reg-names : should contain each of the following 3 names, with the "iram" + entry being the first one + "iram" for Instruction RAM, + "control" for the CTRL sub-module registers, + "debug" for the Debug sub-module registers, + +Optional Properties: +-------------------- +- mboxes : OMAP Mailbox specifier denoting the sub-mailbox, if using a + mailbox for IPC signalling between host and a PRU core. This + property is currently _required_ to support virtio based + communication (will be made truly optional in the future to + choose between either PRUSS system events or mailboxes for + signalling). The specifier format is as per the bindings, + Documentation/devicetree/bindings/mailbox/omap-mailbox.txt + This property should match with the sub-mailbox node used in + the corresponding firmware image. + + +MDIO Child Node +================ +Each PRUSS has an MDIO module that can be used to control external PHYs. The +MDIO module used within the PRU-ICSS is an instance of the MDIO Controller +used in TI Davinci SoCs. Please refer to the corresponding binding document, +Documentation/devicetree/bindings/net/davinci-mdio.txt for details. + + +Application/User Nodes +======================= +The PRUSS device node will typically get used by application/user nodes that +define/represent a PRU application. Each application/client node would need a +reference to the PRUSS node or directly the PRU nodes in general. + +Optional Properties: +-------------------- +- pruss : phandle to a PRUSS node + + +Example: +======== + /* AM33xx PRU-ICSS */ + pruss: pruss@4a300000 { + compatible = "ti,am3352-pruss"; + ti,hwmods = "pruss"; + reg = <0x4a300000 0x2000>, + <0x4a302000 0x2000>, + <0x4a310000 0x3000>, + <0x4a320000 0x2000>, + <0x4a326000 0x2000>, + <0x4a32e000 0x31c>, + <0x4a332000 0x58>; + reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg", + "iep", "mii_rt"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_intc: intc@4a320000 { + compatible = "ti,am3352-pruss-intc"; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + pru0: pru0@4a334000 { + compatible = "ti,am3352-pru"; + reg = <0x4a334000 0x2000>, + <0x4a322000 0x400>, + <0x4a322400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru0>; + }; + + pru1: pru1@4a338000 { + compatible = "ti,am3352-pru"; + reg = <0x4a338000 0x2000>, + <0x4a324000 0x400>, + <0x4a324400 0x100>; + reg-names = "iram", "control", "debug"; + mboxes = <&mailbox &mbox_pru1>; + }; + + pruss_mdio: mdio@4a332400 { + compatible = "ti,davinci_mdio"; + reg = <0x4a332400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/reset/syscon-reset.txt b/Documentation/devicetree/bindings/reset/syscon-reset.txt --- a/Documentation/devicetree/bindings/reset/syscon-reset.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/reset/syscon-reset.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,110 @@ +SysCon Reset Controller +======================= + +Almost all SoCs have hardware modules that require reset control in addition +to clock and power control for their functionality. The reset control is +typically provided by means of memory-mapped I/O registers. These registers are +sometimes a part of a larger register space region implementing various +functionalities. This register range is best represented as a syscon node to +allow multiple entities to access their relevant registers in the common +register space. + +A SysCon Reset Controller node defines a device that uses a syscon node +and provides reset management functionality for various hardware modules +present on the SoC. + +SysCon Reset Controller Node +============================ +Each of the reset provider/controller nodes should be a child of a syscon +node and have the following properties. + +Required properties: +-------------------- + - compatible : Should be "syscon-reset" + - #reset-cells : Should be 1. Please see the reset consumer node below + for usage details + - #address-cells : Should be 1 + - #size-cells : Should be 0 + +SysCon Reset Child Node +============================ +Each reset provider/controller node should have a child node for each reset +it would like to expose to consumers. + +Required properties: +-------------------- + - reg : Reset's logical number, this value will be used by + consumers of this reset as their reset specifier value + - reset-control : Contains the reset control register information, + Should contain 3 cells defined as: + Cell #1 : register offset of the reset + control/status register from the syscon + register base + Cell #2 : bit shift value for the reset in the + respective reset control/status register + Cell #3 : polarity of the reset bit, should use the + definitions defined in the DT include file + include/dt-bindings/reset/syscon.h + Should be RESET_ASSERT_SET for resets + that are asserted when the bit is set, + and RESET_ASSERT_CLEAR for resets that + are asserted when the bit is cleared. + +Optional properties: +-------------------- + - reset-status : Contains the reset status register information. The + contents of this property are the equivalent to + reset-control as defined above. If this property is + not present and the toggle flag is not set, the + reset register is assumed to be the same as the + control register + - toggle : Mark this reset as a toggle only reset, this is used + when no status register is available. + +SysCon Reset Consumer Nodes +=========================== +Each of the reset consumer nodes should have the following properties, +in addition to their own properties. + +Required properties: +-------------------- + - resets : A phandle and a reset specifier, the reset specifier should + be a numerical address matching the desired reset as set + by the reg property defined above. + +Please also refer to Documentation/devicetree/bindings/reset/reset.txt for +common reset controller usage by consumers. + +Example: +-------- +The following example demonstrates a syscon node, the reset controller node +using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 +Edison SoC. + +/ { + soc { + psc: power-sleep-controller@02350000 { + compatible = "syscon", "simple-mfd"; + reg = <0x02350000 0x1000>; + + pscrst: psc-reset { + compatible = "syscon-reset"; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsp@0 { + reg = <0>; + reset-control = <0xa3c 8 RESET_ASSERT_CLEAR>; + reset-status = <0x83c 8 RESET_ASSERT_CLEAR>; + }; + }; + }; + + dsp0: dsp0 { + ... + resets = <&pscrst 0>; + ... + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt --- a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,68 @@ +Texas Instruments System Control Interface (TI-SCI) Reset Controller +===================================================================== + +Some TI SoCs contain a system controller (like the Power Management Micro +Controller (PMMC) on Keystone 2 Galileo SoC) that are responsible for +controlling the state of the various hardware modules present on the SoC. +Communication between the host processor running an OS and the system +controller happens through a protocol called TI System Control Interface +(TI-SCI protocol). For TI SCI details, please refer to the document, +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt + +TI-SCI Reset Controller Node +============================ +This reset controller node uses the TI SCI protocol to perform the reset +management of various hardware modules present on the SoC. + +Required properties: +-------------------- + - compatible : Should be "ti,sci-reset" + - ti,sci : phandle to the TI SCI device to use for managing resets + - #reset-cells : Should be 2. Please see the reset consumer node below for + usage details. + +TI-SCI Reset Consumer Nodes +=========================== +Each of the reset consumer nodes should have the following properties, +in addition to their own properties. + +Required properties: +-------------------- + - resets : A phandle and reset specifier pair, one pair for each reset + signal that affects the device, or that the device manages. + The phandle should point to the TI-SCI reset controller node, + and the reset specifier should have 2 cell-values. The first + cell should contain the device ID, the values of which are + specified in the .h> include file. + The second cell should contain the reset mask value used by + system controller, the values of which are specified in the + include file .h>, where is the + name of the SoC involved, for example 'k2g'. + +Please also refer to Documentation/devicetree/bindings/reset/reset.txt for +common reset controller usage by consumers. + + +Example: +-------- +The following example demonstrates both a TI-SCI reset controller node and a +consumer (a DSP device) on the Keystone 2 Galileo SoC. + +#include +#include + +/ { + soc { + k2g_reset: k2g_reset { + compatible = "ti,sci-reset"; + ti,sci = <&pmmc>; + #reset-cells = <2>; + }; + + dsp0: dsp0 { + ... + resets = <&k2g_reset K2G_DEV_CGEM0 K2G_DEV_CGEM0_DSP0_RESET>; + ... + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/serial/keystone-uart.txt b/Documentation/devicetree/bindings/serial/keystone-uart.txt --- a/Documentation/devicetree/bindings/serial/keystone-uart.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/serial/keystone-uart.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,23 @@ +Keystone UART controller + +Required properties: +- compatible : should be "ti,keystone-uart" for K2G, K2E, K2L and K2HL + controllers + +See Documentation/devicetree/bindings/serial/8250.txt for other required +and optional properties. + +Example: + + uart1: serial@02531000 { + compatible = "ti,keystone-uart", "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02531000 0x100>; + interrupts = ; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_UART1>; + clocks = <&k2g_clks K2G_DEV_UART1 0>; + clock-names = "fck"; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/soc/ti/keystone-dsp-mem.txt b/Documentation/devicetree/bindings/soc/ti/keystone-dsp-mem.txt --- a/Documentation/devicetree/bindings/soc/ti/keystone-dsp-mem.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/soc/ti/keystone-dsp-mem.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,27 @@ +TI Keystone DSP Memory Mapping Device +===================================== + +Binding status: Unstable - ABI compatibility may be broken in the future + +The Keystone DSP Memory Mapping Device is a device node used to represent +the memory regions that can be mapped into userspace for providing direct +user-mode access to regions for the purposes of shared memory communication +with the DSP remote processor devices on the SoC. It can also be used for +supporting user-space based loading of the DSP remoteproc devices. + +Required properties: +-------------------- +- compatible : Should be "ti,keystone-dsp-mem" +- reg : An array of memory regions, each region represented by a tuple + of the region's start address and the size of the region. + +Example: +-------- + /* K2HK EVM */ + soc { + mpm_mem: dspmem { + compatible = "ti,keystone-dsp-mem"; + reg = <0x0c000000 0x00600000>, /* MSMC Memory */ + <0xa0000000 0x20000000>; /* DDR Memory */ + }; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt --- a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt 2016-05-11 13:31:53.189225170 -0400 @@ -18,6 +18,7 @@ Required properties: - compatible : Must be "ti,keystone-navigator-qmss"; + : Must be "ti,keystone-navigator-qmss-l" for NSS Lite - clocks : phandle to the reference clock for this device. - queue-range : total range of queue numbers for the device. - linkram0 :
for internal link ram, where size is the total @@ -39,6 +40,12 @@ - Descriptor memory setup region. - Queue Management/Queue Proxy region for queue Push. - Queue Management/Queue Proxy region for queue Pop. + +For NSS lite, following QMSS reg indexes are used in that order + - Queue Peek region. + - Queue configuration region. + - Queue Management/Queue Proxy region for queue Push/Pop. + - queue-pools : child node classifying the queue ranges into pools. Queue ranges are grouped into 3 type of pools: - qpend : pool of qpend(interruptible) queues diff -Naur --no-dereference a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt --- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,57 @@ +Texas Instruments TI-SCI Generic Power Domain +--------------------------------------------- + +Some TI SoCs contain a system controller (like the PMMC, etc...) that are +responsible for control the state of the IPs that are present. Communication +between the host processor running an OS and the system controller happens +through a protocol known as TI SCI. This pm domain implementation plugs into +the generic pm domain framework and makes use of the TI SCI protocol power on +and off each device when needed. + +PM Domains Nodes +================ +The PM domains node represents the global PM domain managed by the PMMC, +which in this case is one cell implementation as documented by the generic +PM domain bindings in +Documentation/devicetree/bindings/power/power_domain.txt. + +Required Properties: +-------------------- +- compatible: should be "ti,sci-pm-domains" +- #power-domain-cells: Must be 1 so that an offset can be provided in each + device node. +- ti,sci: Phandle to the TI SCI device to use for managing the devices + + +Example: +-------------------- +/* From arch/arm/boot/dts/k2g.dtsi */ +k2g_pds: k2g_pds { + compatible = "ti,sci-pm-domains"; + #power-domain-cells = <1>; + ti,sci = <&pmmc>; +}; + +PM Domain Consumers +=================== +Hardware blocks belonging to a PM domain should contain a "power-domains" +property that is a phandle pointing to the corresponding PM domain node +along with an index representing the device id to be passed for the PMMC +for device control. + +See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g. + +Example: +-------------------- +/* From arch/arm/boot/dts/k2g.dtsi */ +uart0: serial@02530c00 { + compatible = "ns16550a"; + current-speed = <115200>; + reg-shift = <2>; + reg-io-width = <4>; + reg = <0x02530c00 0x100>; + interrupts = ; + clock-frequency = <200000000>; + status = "disabled"; + power-domains = <&k2g_pds K2G_DEV_UART0>; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt b/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt --- a/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,150 @@ +Wakeup M3 IPC Driver +===================== + +The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor +(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks +that cannot be controlled from the MPU, like suspend/resume and certain deep +C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver +to boot the wkup_m3, it handles communication with the CM3 using IPC registers +present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an +API to allow the SoC PM code to execute specific PM tasks. + +Wkup M3 Device Node: +==================== +A wkup_m3_ipc device node is used to represent the IPC registers within an +SoC. + +Required properties: +-------------------- +- compatible: Should be, + "ti,am3352-wkup-m3-ipc" for AM33xx SoCs + "ti,am4372-wkup-m3-ipc" for AM43xx SoCs +- reg: Contains the IPC register address space to communicate + with the Wakeup M3 processor +- interrupts: Contains the interrupt information for the wkup_m3 + interrupt that signals the MPU. +- ti,rproc: phandle to the wkup_m3 rproc node so the IPC driver + can boot it. +- mboxes: phandles used by IPC framework to get correct mbox + channel for communication. Must point to appropriate + mbox_wkupm3 child node. + +Example: +-------- +/* AM33xx */ + l4_wkup: l4_wkup@44c00000 { + ... + + scm: scm@210000 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x210000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x2000>; + + ... + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + reg = <0x1324 0x24>; + interrupts = <78>; + ti,rproc = <&wkup_m3>; + mboxes = <&mailbox &mbox_wkupm3>; + }; + + ... + }; + }; + +Support for I2C PMIC Voltage Scaling +-------------------- +It is possible to pass the name of a binary file to laod to the CM3 firmware +in order to provide I2C sequences for the CM3 to send out to the PMIC during +low power mode entry. + +Optional properties: +-------------------- +- scale-data-fw: Name of the firmware binary in /lib/firmware to copy to m3 + aux data. + +Support for VTT Toggle +================================== +In order to enable the support for VTT toggle during Suspend/Resume +sequence needed by some boards (like AM335x EVM-SK & AM437x GP EVM), +the below DT properties are required. It is possible to toggle VTT +using one of two methods depending on the SoC being used, either +GPIO0 toggle (AM335x and AM437x), or any GPIO with DS_PAD_CONFIG +bits in the control module (AM437x only). + +VTT Toggle using GPIO0 +---------------------------------- +Supported by: AM335x and AM437x +Used on: AM335x EVM-SK + +Optional properties: +- ti,needs-vtt-toggle: Indicates that the boards requires VTT toggling + during suspend/resume. +- ti,vtt-gpio-pin: Specifies the GPIO0 pin used for VTT toggle. + +Important Note: +- Here it is assumed that VTT Toggle will be done using a pin on GPIO-0 Instance. + It will not work on any other GPIO using the above properties, regardless of + which part is being used. + +Example: + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am3352-wkup-m3-ipc"; + ... + ... + ti,needs-vtt-toggle; + ti,vtt-gpio-pin = <7>; + ... + }; + +VTT Toggle using any GPIO +---------------------------------- +Supported by: AM437x ONLY +Used on: AM437x GP EVM + +Many of the pins on AM437x have the ability to configure both normal and +sleep states. Because of this it is possible to use any pin with a +corresponding CTRL_CONF_* register in the control module and the +DS_PAD_CONFIG bits to toggle the VTT regulator enable pin. The DS state of +the pin must be configured such that the pin disables the VTT regulator. The +normal state of the pin must be configured such that the VTT regulator is +enabled by the state alone. This is because the VTT regulator must be enabled +before context is restored to the controlling GPIO. + +Optional properties: +- ti,set-io-isolation: Indicates that the IO's should be placed into + isolation and the DS_PAD_CONFIG values should be + used during suspend. + +Example: + +On the AM437x GP EVM, the VTT enable line must be held low to disable VTT +regulator and held high to enable, so the following pinctrl entry is used. +The DS pull is enabled which uses a pull down by default and DS off mode is +used which outputs a low by default. For the normal state, a pull up is +specified so that the VTT enable line gets pulled high immediately after +the DS states are removed upon exit from DeepSleep0. + + &am43xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&ddr3_vtt_toggle_default>; + + ddr3_vtt_toggle_default: ddr_vtt_toggle_default { + pinctrl-single,pins = < + 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | + DS0_FORCE_OFF_MODE | MUX_MODE7)>; + }; + ... + }; + + wkup_m3_ipc: wkup_m3_ipc@1324 { + compatible = "ti,am4372-wkup-m3-ipc"; + ... + ... + ti,set-io-isolation; + ... + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt --- a/Documentation/devicetree/bindings/sound/simple-card.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/sound/simple-card.txt 2016-05-11 13:31:53.189225170 -0400 @@ -84,6 +84,9 @@ in dai startup() and disabled with clk_disable_unprepare() in dai shutdown(). +- system-clock-direction : "in" or "out", default "in" +- system-clock-id : Numberic ID of the system clock to + select within the dai, default is 0. Example 1 - single DAI link: diff -Naur --no-dereference a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt 2016-05-11 13:31:53.189225170 -0400 @@ -15,14 +15,39 @@ - spi-max-frequency: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt +Optional properties: +- syscon-chipselects: Handle to system control region contains QSPI + chipselect register and offset of that register. + +NOTE: TI QSPI controller requires different pinmux and IODelay +paramaters for Mode-0 and Mode-3 operations, which needs to be set up by +the bootloader (U-Boot). Default configuration only supports Mode-0 +operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be +specified in the slave nodes of TI QSPI controller without appropriate +modification to bootloader. + Example: +For am4372: qspi: qspi@4b300000 { - compatible = "ti,dra7xxx-qspi"; - reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>; + compatible = "ti,am4372-qspi"; + reg = <0x47900000 0x100>, <0x30000000 0x4000000>; reg-names = "qspi_base", "qspi_mmap"; #address-cells = <1>; #size-cells = <0>; spi-max-frequency = <25000000>; ti,hwmods = "qspi"; }; + +For dra7xx: +qspi: qspi@4b300000 { + compatible = "ti,dra7xxx-qspi"; + reg = <0x4b300000 0x100>, + <0x5c000000 0x4000000>, + reg-names = "qspi_base", "qspi_mmap"; + syscon-chipselects = <&scm_conf 0x558>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <48000000>; + ti,hwmods = "qspi"; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt --- a/Documentation/devicetree/bindings/usb/generic.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/bindings/usb/generic.txt 2016-05-11 13:31:53.189225170 -0400 @@ -24,6 +24,11 @@ optional for OTG device. - adp-disable: tells OTG controllers we want to disable OTG ADP, ADP is optional for OTG device. + - otg-controller: phandle to otg controller. Host or gadget controllers can + contain this property to link it to a particular otg + controller. If this property is not present then otg + core assumes that host and gadget controllers are + children of the otg controller. This is an attribute to a USB controller such as: diff -Naur --no-dereference a/Documentation/devicetree/bindings/video/backlight/led-backlight.txt b/Documentation/devicetree/bindings/video/backlight/led-backlight.txt --- a/Documentation/devicetree/bindings/video/backlight/led-backlight.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/video/backlight/led-backlight.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,30 @@ +led-backlight bindings + +Required properties: + - compatible: "led-backlight" + - leds: phandle to a led OF node [0] + - brightness-levels: Array of distinct LED brightness levels. These + are in the range from 0 to 255, passed to the LED class driver. + - default-brightness-level: the default brightness level (index into the + array defined by the "brightness-levels" property) + - power-supply: regulator for supply voltage + +Optional properties: + - enable-gpios: contains a single GPIO specifier for the GPIO which enables + and disables the backlight (see GPIO binding[1]) + +[0]: Documentation/devicetree/bindings/leds/common.txt +[1]: Documentation/devicetree/bindings/gpio/gpio.txt + +Example: + + backlight { + compatible = "led-backlight"; + leds = <&backlight_led>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + + power-supply = <&vdd_bl_reg>; + enable-gpios = <&gpio 58 0>; + }; diff -Naur --no-dereference a/Documentation/devicetree/bindings/video/sil,sii9022.txt b/Documentation/devicetree/bindings/video/sil,sii9022.txt --- a/Documentation/devicetree/bindings/video/sil,sii9022.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/video/sil,sii9022.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,67 @@ +Silicon Image SiI9022 HDMI Encoder +================================== + +Silicon Image SiI9022 is an HDMI encoder that encodes parallel RGB +signal to HDMI signal. The SiI9022 is controlled with i2c command, and +it has a single reset pin and single interrupt pin. + +Required properties: +- compatible: "sil,sii9022" + +Optional properties: +- reset-gpio: reset gpio +- interrupts: interrupt line + +Required for HDMI audio: +- i2s-fifo-routing: + - Array of exactly 4 integers indicating i2s pins to audio fifo routing + - First integer defines routing to fifo 0 and second to fifo 1, etc. + - Integers can be filled with definitions from: + include/dt-bindings/sound/sii9022-audio.h + +Required nodes: +- Video port 0 for parallel video input +- Video port 1 for HDMI output + +Example +------- + +&i2c2 { + sii9022: sii9022@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + + i2s-fifo-routing = < + (ENABLE_BIT|CONNECT_SD0) + 0 + 0 + 0 + >; + + reset-gpio = <&gpio2 1 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/video/ti,dra7evm-tpd12s015.txt b/Documentation/devicetree/bindings/video/ti,dra7evm-tpd12s015.txt --- a/Documentation/devicetree/bindings/video/ti,dra7evm-tpd12s015.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/video/ti,dra7evm-tpd12s015.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,48 @@ +TPD12S015 HDMI level shifter and ESD protection chip customized for DRA7 EVM +============================================================================ + +Required properties: +- compatible: "ti,dra7evm-tpd12s015" + +Optional properties: +- gpios: CT CP HPD, LS OE and HPD gpios +- disable-hpd: Disables hot plug detect, required for old DRA7 + EVMs(Rev D and older) + +Required nodes: +- Video port 0 for HDMI input +- Video port 1 for HDMI output + +Example +------- + +tpd12s015: encoder@1 { + compatible = "ti,dra7evm-tpd12s015"; + + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */ + <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */ + <&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */ + + disable-hpd; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/bindings/video/ti,k2g-dss.txt b/Documentation/devicetree/bindings/video/ti,k2g-dss.txt --- a/Documentation/devicetree/bindings/video/ti,k2g-dss.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/video/ti,k2g-dss.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,34 @@ +Texas Instruments K2G Display Subsystem +========================================= + +See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic +description about OMAP Display Subsystem bindings. + +DSS Core +-------- + +Required properties: +- compatible: "ti,k2g-dss" +- reg: address and length of the register space for 'dss' +- clocks: handle to fclk +- clock-names: "fck" + +Required nodes: +- DISPC + +Optional nodes: +- Video port for DPI output + +DPI Endpoint required properties: +- data-lines: number of lines used + +DISPC +----- + +Required properties: +- compatible: "ti,k2g-dispc" +- reg: addresses and lengths of the register spaces +- reg-names: "common", "vid1", "ovr1", "vp1" +- interrupts: the DISPC interrupt +- clocks: handles to fclk and vp clock +- clock-names: "fck", "vp" diff -Naur --no-dereference a/Documentation/devicetree/bindings/video/ti,tlc59108.txt b/Documentation/devicetree/bindings/video/ti,tlc59108.txt --- a/Documentation/devicetree/bindings/video/ti,tlc59108.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/bindings/video/ti,tlc59108.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,26 @@ +TLC59108 based DPI panel +======================== + +Required properties +- compatible: "ti,tlc59108-lp101"; /* For 1280x800 Panel on DRA7/DRA72 EVM */ + +- reg: i2c slave address of the chip on the board +- enable-gpio: Enable GPIO for the DPI panel + +Required nodes: +- Video port for DPI input + +Example: +------- + +tlc59108: tlc59108@40 { + ompatible = "ti,tlc59108-lp101"; + reg = <0x40>; + enable_gpio = ; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; +}; diff -Naur --no-dereference a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt --- a/Documentation/devicetree/configfs-overlays.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/devicetree/configfs-overlays.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,31 @@ +Howto use the configfs overlay interface. + +A device-tree configfs entry is created in /config/device-tree/overlays +and and it is manipulated using standard file system I/O. +Note that this is a debug level interface, for use by developers and +not necessarily something accessed by normal users due to the +security implications of having direct access to the kernel's device tree. + +* To create an overlay you mkdir the directory: + + # mkdir /config/device-tree/overlays/foo + +* Either you echo the overlay firmware file to the path property file. + + # echo foo.dtbo >/config/device-tree/overlays/foo/path + +* Or you cat the contents of the overlay to the dtbo file + + # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo + +The overlay file will be applied, and devices will be created/destroyed +as required. + +To remove it simply rmdir the directory. + + # rmdir /config/device-tree/overlays/foo + +The rationalle of the dual interface (firmware & direct copy) is that each is +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). diff -Naur --no-dereference a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt --- a/Documentation/devicetree/overlay-notes.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/devicetree/overlay-notes.txt 2016-05-11 13:31:53.189225170 -0400 @@ -100,6 +100,14 @@ of_overlay_destroy_all() which will remove every single one in the correct order. +If your board has multiple slots/places where a single overlay can work +and each slot is defined by a node, you can use the of_overlay_create_indirect() +method to select the target. + +For overlays on probeable busses, use the of_overlay_create_target_root() method +in which you supply a device node as a target root, and which all target +references in the overlay are performed relative to that node. + Overlay DTS Format ------------------ @@ -113,6 +121,11 @@ target=; /* phandle target of the overlay */ or target-path="/path"; /* target path of the overlay */ + or + target-indirect { /* indirect target selector */ + foo { target|target-path ... }; + bar { .... }; + }; __overlay__ { property-a; /* add property-a to the target */ @@ -131,3 +144,11 @@ not contain a __symbols__ node, i.e. it was not compiled with the -@ option. The __symbols__ node is only required for the target= method, since it contains the information required to map from a phandle to a tree location. + +The indirect target requires the use of a selector target on the call to +of_overlay_create_indirect(). I.e. passing the "foo" id will select the target +in the foo node, "bar" in bar node, etc. + +Note that when using the target root create method all target references must +lie under the target root node. I.e. the overlay is not allowed to 'break' out +of the root. diff -Naur --no-dereference a/Documentation/dmaengine/client.txt b/Documentation/dmaengine/client.txt --- a/Documentation/dmaengine/client.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/dmaengine/client.txt 2016-05-11 13:31:53.189225170 -0400 @@ -22,25 +22,14 @@ Channel allocation is slightly different in the slave DMA context, client drivers typically need a channel from a particular DMA controller only and even in some cases a specific channel is desired. - To request a channel dma_request_channel() API is used. + To request a channel dma_request_chan() API is used. Interface: - struct dma_chan *dma_request_channel(dma_cap_mask_t mask, - dma_filter_fn filter_fn, - void *filter_param); - where dma_filter_fn is defined as: - typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); - - The 'filter_fn' parameter is optional, but highly recommended for - slave and cyclic channels as they typically need to obtain a specific - DMA channel. - - When the optional 'filter_fn' parameter is NULL, dma_request_channel() - simply returns the first channel that satisfies the capability mask. - - Otherwise, the 'filter_fn' routine will be called once for each free - channel which has a capability in 'mask'. 'filter_fn' is expected to - return 'true' when the desired DMA channel is found. + struct dma_chan *dma_request_chan(struct device *dev, const char *name); + + Which will find and return the 'name' DMA channel associated with the 'dev' + device. The association is done via DT, ACPI or board file based + dma_slave_map matching table. A channel allocated via this interface is exclusive to the caller, until dma_release_channel() is called. @@ -128,7 +117,7 @@ transaction. For cyclic DMA, a callback function may wish to terminate the - DMA via dmaengine_terminate_all(). + DMA via dmaengine_terminate_async(). Therefore, it is important that DMA engine drivers drop any locks before calling the callback function which may cause a @@ -166,12 +155,29 @@ Further APIs: -1. int dmaengine_terminate_all(struct dma_chan *chan) +1. int dmaengine_terminate_sync(struct dma_chan *chan) + int dmaengine_terminate_async(struct dma_chan *chan) + int dmaengine_terminate_all(struct dma_chan *chan) /* DEPRECATED */ This causes all activity for the DMA channel to be stopped, and may discard data in the DMA FIFO which hasn't been fully transferred. No callback functions will be called for any incomplete transfers. + Two variants of this function are available. + + dmaengine_terminate_async() might not wait until the DMA has been fully + stopped or until any running complete callbacks have finished. But it is + possible to call dmaengine_terminate_async() from atomic context or from + within a complete callback. dmaengine_synchronize() must be called before it + is safe to free the memory accessed by the DMA transfer or free resources + accessed from within the complete callback. + + dmaengine_terminate_sync() will wait for the transfer and any running + complete callbacks to finish before it returns. But the function must not be + called from atomic context or from within a complete callback. + + dmaengine_terminate_all() is deprecated and should not be used in new code. + 2. int dmaengine_pause(struct dma_chan *chan) This pauses activity on the DMA channel without data loss. @@ -197,3 +203,20 @@ a running DMA channel. It is recommended that DMA engine users pause or stop (via dmaengine_terminate_all()) the channel before using this API. + +5. void dmaengine_synchronize(struct dma_chan *chan) + + Synchronize the termination of the DMA channel to the current context. + + This function should be used after dmaengine_terminate_async() to synchronize + the termination of the DMA channel to the current context. The function will + wait for the transfer and any running complete callbacks to finish before it + returns. + + If dmaengine_terminate_async() is used to stop the DMA channel this function + must be called before it is safe to free memory accessed by previously + submitted descriptors or to free any resources accessed within the complete + callback of previously submitted descriptors. + + The behavior of this function is undefined if dma_async_issue_pending() has + been called between dmaengine_terminate_async() and this function. diff -Naur --no-dereference a/Documentation/dmaengine/provider.txt b/Documentation/dmaengine/provider.txt --- a/Documentation/dmaengine/provider.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/dmaengine/provider.txt 2016-05-11 13:31:53.189225170 -0400 @@ -327,8 +327,24 @@ * device_terminate_all - Aborts all the pending and ongoing transfers on the channel - - This command should operate synchronously on the channel, - terminating right away all the channels + - For aborted transfers the complete callback should not be called + - Can be called from atomic context or from within a complete + callback of a descriptor. Must not sleep. Drivers must be able + to handle this correctly. + - Termination may be asynchronous. The driver does not have to + wait until the currently active transfer has completely stopped. + See device_synchronize. + + * device_synchronize + - Must synchronize the termination of a channel to the current + context. + - Must make sure that memory for previously submitted + descriptors is no longer accessed by the DMA controller. + - Must make sure that all complete callbacks for previously + submitted descriptors have finished running and none are + scheduled to run. + - May sleep. + Misc notes (stuff that should be documented, but don't really know where to put them) diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/01intro.txt b/Documentation/filesystems/aufs/design/01intro.txt --- a/Documentation/filesystems/aufs/design/01intro.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/01intro.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,170 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Introduction +---------------------------------------- + +aufs [ei ju: ef es] | [a u f s] +1. abbrev. for "advanced multi-layered unification filesystem". +2. abbrev. for "another unionfs". +3. abbrev. for "auf das" in German which means "on the" in English. + Ex. "Butter aufs Brot"(G) means "butter onto bread"(E). + But "Filesystem aufs Filesystem" is hard to understand. + +AUFS is a filesystem with features: +- multi layered stackable unification filesystem, the member directory + is called as a branch. +- branch permission and attribute, 'readonly', 'real-readonly', + 'readwrite', 'whiteout-able', 'link-able whiteout', etc. and their + combination. +- internal "file copy-on-write". +- logical deletion, whiteout. +- dynamic branch manipulation, adding, deleting and changing permission. +- allow bypassing aufs, user's direct branch access. +- external inode number translation table and bitmap which maintains the + persistent aufs inode number. +- seekable directory, including NFS readdir. +- file mapping, mmap and sharing pages. +- pseudo-link, hardlink over branches. +- loopback mounted filesystem as a branch. +- several policies to select one among multiple writable branches. +- revert a single systemcall when an error occurs in aufs. +- and more... + + +Multi Layered Stackable Unification Filesystem +---------------------------------------------------------------------- +Most people already knows what it is. +It is a filesystem which unifies several directories and provides a +merged single directory. When users access a file, the access will be +passed/re-directed/converted (sorry, I am not sure which English word is +correct) to the real file on the member filesystem. The member +filesystem is called 'lower filesystem' or 'branch' and has a mode +'readonly' and 'readwrite.' And the deletion for a file on the lower +readonly branch is handled by creating 'whiteout' on the upper writable +branch. + +On LKML, there have been discussions about UnionMount (Jan Blunck, +Bharata B Rao and Valerie Aurora) and Unionfs (Erez Zadok). They took +different approaches to implement the merged-view. +The former tries putting it into VFS, and the latter implements as a +separate filesystem. +(If I misunderstand about these implementations, please let me know and +I shall correct it. Because it is a long time ago when I read their +source files last time). + +UnionMount's approach will be able to small, but may be hard to share +branches between several UnionMount since the whiteout in it is +implemented in the inode on branch filesystem and always +shared. According to Bharata's post, readdir does not seems to be +finished yet. +There are several missing features known in this implementations such as +- for users, the inode number may change silently. eg. copy-up. +- link(2) may break by copy-up. +- read(2) may get an obsoleted filedata (fstat(2) too). +- fcntl(F_SETLK) may be broken by copy-up. +- unnecessary copy-up may happen, for example mmap(MAP_PRIVATE) after + open(O_RDWR). + +In linux-3.18, "overlay" filesystem (formerly known as "overlayfs") was +merged into mainline. This is another implementation of UnionMount as a +separated filesystem. All the limitations and known problems which +UnionMount are equally inherited to "overlay" filesystem. + +Unionfs has a longer history. When I started implementing a stackable +filesystem (Aug 2005), it already existed. It has virtual super_block, +inode, dentry and file objects and they have an array pointing lower +same kind objects. After contributing many patches for Unionfs, I +re-started my project AUFS (Jun 2006). + +In AUFS, the structure of filesystem resembles to Unionfs, but I +implemented my own ideas, approaches and enhancements and it became +totally different one. + +Comparing DM snapshot and fs based implementation +- the number of bytes to be copied between devices is much smaller. +- the type of filesystem must be one and only. +- the fs must be writable, no readonly fs, even for the lower original + device. so the compression fs will not be usable. but if we use + loopback mount, we may address this issue. + for instance, + mount /cdrom/squashfs.img /sq + losetup /sq/ext2.img + losetup /somewhere/cow + dmsetup "snapshot /dev/loop0 /dev/loop1 ..." +- it will be difficult (or needs more operations) to extract the + difference between the original device and COW. +- DM snapshot-merge may help a lot when users try merging. in the + fs-layer union, users will use rsync(1). + +You may want to read my old paper "Filesystems in LiveCD" +(http://aufs.sourceforge.net/aufs2/report/sq/sq.pdf). + + +Several characters/aspects/persona of aufs +---------------------------------------------------------------------- + +Aufs has several characters, aspects or persona. +1. a filesystem, callee of VFS helper +2. sub-VFS, caller of VFS helper for branches +3. a virtual filesystem which maintains persistent inode number +4. reader/writer of files on branches such like an application + +1. Callee of VFS Helper +As an ordinary linux filesystem, aufs is a callee of VFS. For instance, +unlink(2) from an application reaches sys_unlink() kernel function and +then vfs_unlink() is called. vfs_unlink() is one of VFS helper and it +calls filesystem specific unlink operation. Actually aufs implements the +unlink operation but it behaves like a redirector. + +2. Caller of VFS Helper for Branches +aufs_unlink() passes the unlink request to the branch filesystem as if +it were called from VFS. So the called unlink operation of the branch +filesystem acts as usual. As a caller of VFS helper, aufs should handle +every necessary pre/post operation for the branch filesystem. +- acquire the lock for the parent dir on a branch +- lookup in a branch +- revalidate dentry on a branch +- mnt_want_write() for a branch +- vfs_unlink() for a branch +- mnt_drop_write() for a branch +- release the lock on a branch + +3. Persistent Inode Number +One of the most important issue for a filesystem is to maintain inode +numbers. This is particularly important to support exporting a +filesystem via NFS. Aufs is a virtual filesystem which doesn't have a +backend block device for its own. But some storage is necessary to +keep and maintain the inode numbers. It may be a large space and may not +suit to keep in memory. Aufs rents some space from its first writable +branch filesystem (by default) and creates file(s) on it. These files +are created by aufs internally and removed soon (currently) keeping +opened. +Note: Because these files are removed, they are totally gone after + unmounting aufs. It means the inode numbers are not persistent + across unmount or reboot. I have a plan to make them really + persistent which will be important for aufs on NFS server. + +4. Read/Write Files Internally (copy-on-write) +Because a branch can be readonly, when you write a file on it, aufs will +"copy-up" it to the upper writable branch internally. And then write the +originally requested thing to the file. Generally kernel doesn't +open/read/write file actively. In aufs, even a single write may cause a +internal "file copy". This behaviour is very similar to cp(1) command. + +Some people may think it is better to pass such work to user space +helper, instead of doing in kernel space. Actually I am still thinking +about it. But currently I have implemented it in kernel space. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/02struct.txt b/Documentation/filesystems/aufs/design/02struct.txt --- a/Documentation/filesystems/aufs/design/02struct.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/02struct.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,258 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Basic Aufs Internal Structure + +Superblock/Inode/Dentry/File Objects +---------------------------------------------------------------------- +As like an ordinary filesystem, aufs has its own +superblock/inode/dentry/file objects. All these objects have a +dynamically allocated array and store the same kind of pointers to the +lower filesystem, branch. +For example, when you build a union with one readwrite branch and one +readonly, mounted /au, /rw and /ro respectively. +- /au = /rw + /ro +- /ro/fileA exists but /rw/fileA + +Aufs lookup operation finds /ro/fileA and gets dentry for that. These +pointers are stored in a aufs dentry. The array in aufs dentry will be, +- [0] = NULL (because /rw/fileA doesn't exist) +- [1] = /ro/fileA + +This style of an array is essentially same to the aufs +superblock/inode/dentry/file objects. + +Because aufs supports manipulating branches, ie. add/delete/change +branches dynamically, these objects has its own generation. When +branches are changed, the generation in aufs superblock is +incremented. And a generation in other object are compared when it is +accessed. When a generation in other objects are obsoleted, aufs +refreshes the internal array. + + +Superblock +---------------------------------------------------------------------- +Additionally aufs superblock has some data for policies to select one +among multiple writable branches, XIB files, pseudo-links and kobject. +See below in detail. +About the policies which supports copy-down a directory, see +wbr_policy.txt too. + + +Branch and XINO(External Inode Number Translation Table) +---------------------------------------------------------------------- +Every branch has its own xino (external inode number translation table) +file. The xino file is created and unlinked by aufs internally. When two +members of a union exist on the same filesystem, they share the single +xino file. +The struct of a xino file is simple, just a sequence of aufs inode +numbers which is indexed by the lower inode number. +In the above sample, assume the inode number of /ro/fileA is i111 and +aufs assigns the inode number i999 for fileA. Then aufs writes 999 as +4(8) bytes at 111 * 4(8) bytes offset in the xino file. + +When the inode numbers are not contiguous, the xino file will be sparse +which has a hole in it and doesn't consume as much disk space as it +might appear. If your branch filesystem consumes disk space for such +holes, then you should specify 'xino=' option at mounting aufs. + +Aufs has a mount option to free the disk blocks for such holes in XINO +files on tmpfs or ramdisk. But it is not so effective actually. If you +meet a problem of disk shortage due to XINO files, then you should try +"tmpfs-ino.patch" (and "vfs-ino.patch" too) in aufs4-standalone.git. +The patch localizes the assignment inumbers per tmpfs-mount and avoid +the holes in XINO files. + +Also a writable branch has three kinds of "whiteout bases". All these +are existed when the branch is joined to aufs, and their names are +whiteout-ed doubly, so that users will never see their names in aufs +hierarchy. +1. a regular file which will be hardlinked to all whiteouts. +2. a directory to store a pseudo-link. +3. a directory to store an "orphan"-ed file temporary. + +1. Whiteout Base + When you remove a file on a readonly branch, aufs handles it as a + logical deletion and creates a whiteout on the upper writable branch + as a hardlink of this file in order not to consume inode on the + writable branch. +2. Pseudo-link Dir + See below, Pseudo-link. +3. Step-Parent Dir + When "fileC" exists on the lower readonly branch only and it is + opened and removed with its parent dir, and then user writes + something into it, then aufs copies-up fileC to this + directory. Because there is no other dir to store fileC. After + creating a file under this dir, the file is unlinked. + +Because aufs supports manipulating branches, ie. add/delete/change +dynamically, a branch has its own id. When the branch order changes, +aufs finds the new index by searching the branch id. + + +Pseudo-link +---------------------------------------------------------------------- +Assume "fileA" exists on the lower readonly branch only and it is +hardlinked to "fileB" on the branch. When you write something to fileA, +aufs copies-up it to the upper writable branch. Additionally aufs +creates a hardlink under the Pseudo-link Directory of the writable +branch. The inode of a pseudo-link is kept in aufs super_block as a +simple list. If fileB is read after unlinking fileA, aufs returns +filedata from the pseudo-link instead of the lower readonly +branch. Because the pseudo-link is based upon the inode, to keep the +inode number by xino (see above) is essentially necessary. + +All the hardlinks under the Pseudo-link Directory of the writable branch +should be restored in a proper location later. Aufs provides a utility +to do this. The userspace helpers executed at remounting and unmounting +aufs by default. +During this utility is running, it puts aufs into the pseudo-link +maintenance mode. In this mode, only the process which began the +maintenance mode (and its child processes) is allowed to operate in +aufs. Some other processes which are not related to the pseudo-link will +be allowed to run too, but the rest have to return an error or wait +until the maintenance mode ends. If a process already acquires an inode +mutex (in VFS), it has to return an error. + + +XIB(external inode number bitmap) +---------------------------------------------------------------------- +Addition to the xino file per a branch, aufs has an external inode number +bitmap in a superblock object. It is also an internal file such like a +xino file. +It is a simple bitmap to mark whether the aufs inode number is in-use or +not. +To reduce the file I/O, aufs prepares a single memory page to cache xib. + +As well as XINO files, aufs has a feature to truncate/refresh XIB to +reduce the number of consumed disk blocks for these files. + + +Virtual or Vertical Dir, and Readdir in Userspace +---------------------------------------------------------------------- +In order to support multiple layers (branches), aufs readdir operation +constructs a virtual dir block on memory. For readdir, aufs calls +vfs_readdir() internally for each dir on branches, merges their entries +with eliminating the whiteout-ed ones, and sets it to file (dir) +object. So the file object has its entry list until it is closed. The +entry list will be updated when the file position is zero and becomes +obsoleted. This decision is made in aufs automatically. + +The dynamically allocated memory block for the name of entries has a +unit of 512 bytes (by default) and stores the names contiguously (no +padding). Another block for each entry is handled by kmem_cache too. +During building dir blocks, aufs creates hash list and judging whether +the entry is whiteouted by its upper branch or already listed. +The merged result is cached in the corresponding inode object and +maintained by a customizable life-time option. + +Some people may call it can be a security hole or invite DoS attack +since the opened and once readdir-ed dir (file object) holds its entry +list and becomes a pressure for system memory. But I'd say it is similar +to files under /proc or /sys. The virtual files in them also holds a +memory page (generally) while they are opened. When an idea to reduce +memory for them is introduced, it will be applied to aufs too. +For those who really hate this situation, I've developed readdir(3) +library which operates this merging in userspace. You just need to set +LD_PRELOAD environment variable, and aufs will not consume no memory in +kernel space for readdir(3). + + +Workqueue +---------------------------------------------------------------------- +Aufs sometimes requires privilege access to a branch. For instance, +in copy-up/down operation. When a user process is going to make changes +to a file which exists in the lower readonly branch only, and the mode +of one of ancestor directories may not be writable by a user +process. Here aufs copy-up the file with its ancestors and they may +require privilege to set its owner/group/mode/etc. +This is a typical case of a application character of aufs (see +Introduction). + +Aufs uses workqueue synchronously for this case. It creates its own +workqueue. The workqueue is a kernel thread and has privilege. Aufs +passes the request to call mkdir or write (for example), and wait for +its completion. This approach solves a problem of a signal handler +simply. +If aufs didn't adopt the workqueue and changed the privilege of the +process, then the process may receive the unexpected SIGXFSZ or other +signals. + +Also aufs uses the system global workqueue ("events" kernel thread) too +for asynchronous tasks, such like handling inotify/fsnotify, re-creating a +whiteout base and etc. This is unrelated to a privilege. +Most of aufs operation tries acquiring a rw_semaphore for aufs +superblock at the beginning, at the same time waits for the completion +of all queued asynchronous tasks. + + +Whiteout +---------------------------------------------------------------------- +The whiteout in aufs is very similar to Unionfs's. That is represented +by its filename. UnionMount takes an approach of a file mode, but I am +afraid several utilities (find(1) or something) will have to support it. + +Basically the whiteout represents "logical deletion" which stops aufs to +lookup further, but also it represents "dir is opaque" which also stop +further lookup. + +In aufs, rmdir(2) and rename(2) for dir uses whiteout alternatively. +In order to make several functions in a single systemcall to be +revertible, aufs adopts an approach to rename a directory to a temporary +unique whiteouted name. +For example, in rename(2) dir where the target dir already existed, aufs +renames the target dir to a temporary unique whiteouted name before the +actual rename on a branch, and then handles other actions (make it opaque, +update the attributes, etc). If an error happens in these actions, aufs +simply renames the whiteouted name back and returns an error. If all are +succeeded, aufs registers a function to remove the whiteouted unique +temporary name completely and asynchronously to the system global +workqueue. + + +Copy-up +---------------------------------------------------------------------- +It is a well-known feature or concept. +When user modifies a file on a readonly branch, aufs operate "copy-up" +internally and makes change to the new file on the upper writable branch. +When the trigger systemcall does not update the timestamps of the parent +dir, aufs reverts it after copy-up. + + +Move-down (aufs3.9 and later) +---------------------------------------------------------------------- +"Copy-up" is one of the essential feature in aufs. It copies a file from +the lower readonly branch to the upper writable branch when a user +changes something about the file. +"Move-down" is an opposite action of copy-up. Basically this action is +ran manually instead of automatically and internally. +For desgin and implementation, aufs has to consider these issues. +- whiteout for the file may exist on the lower branch. +- ancestor directories may not exist on the lower branch. +- diropq for the ancestor directories may exist on the upper branch. +- free space on the lower branch will reduce. +- another access to the file may happen during moving-down, including + UDBA (see "Revalidate Dentry and UDBA"). +- the file should not be hard-linked nor pseudo-linked. they should be + handled by auplink utility later. + +Sometimes users want to move-down a file from the upper writable branch +to the lower readonly or writable branch. For instance, +- the free space of the upper writable branch is going to run out. +- create a new intermediate branch between the upper and lower branch. +- etc. + +For this purpose, use "aumvdown" command in aufs-util.git. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/03atomic_open.txt b/Documentation/filesystems/aufs/design/03atomic_open.txt --- a/Documentation/filesystems/aufs/design/03atomic_open.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/03atomic_open.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,85 @@ + +# Copyright (C) 2015-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Support for a branch who has its ->atomic_open() +---------------------------------------------------------------------- +The filesystems who implement its ->atomic_open() are not majority. For +example NFSv4 does, and aufs should call NFSv4 ->atomic_open, +particularly for open(O_CREAT|O_EXCL, 0400) case. Other than +->atomic_open(), NFSv4 returns an error for this open(2). While I am not +sure whether all filesystems who have ->atomic_open() behave like this, +but NFSv4 surely returns the error. + +In order to support ->atomic_open() for aufs, there are a few +approaches. + +A. Introduce aufs_atomic_open() + - calls one of VFS:do_last(), lookup_open() or atomic_open() for + branch fs. +B. Introduce aufs_atomic_open() calling create, open and chmod. this is + an aufs user Pip Cet's approach + - calls aufs_create(), VFS finish_open() and notify_change(). + - pass fake-mode to finish_open(), and then correct the mode by + notify_change(). +C. Extend aufs_open() to call branch fs's ->atomic_open() + - no aufs_atomic_open(). + - aufs_lookup() registers the TID to an aufs internal object. + - aufs_create() does nothing when the matching TID is registered, but + registers the mode. + - aufs_open() calls branch fs's ->atomic_open() when the matching + TID is registered. +D. Extend aufs_open() to re-try branch fs's ->open() with superuser's + credential + - no aufs_atomic_open(). + - aufs_create() registers the TID to an internal object. this info + represents "this process created this file just now." + - when aufs gets EACCES from branch fs's ->open(), then confirm the + registered TID and re-try open() with superuser's credential. + +Pros and cons for each approach. + +A. + - straightforward but highly depends upon VFS internal. + - the atomic behavaiour is kept. + - some of parameters such as nameidata are hard to reproduce for + branch fs. + - large overhead. +B. + - easy to implement. + - the atomic behavaiour is lost. +C. + - the atomic behavaiour is kept. + - dirty and tricky. + - VFS checks whether the file is created correctly after calling + ->create(), which means this approach doesn't work. +D. + - easy to implement. + - the atomic behavaiour is lost. + - to open a file with superuser's credential and give it to a user + process is a bad idea, since the file object keeps the credential + in it. It may affect LSM or something. This approach doesn't work + either. + +The approach A is ideal, but it hard to implement. So here is a +variation of A, which is to be implemented. + +A-1. Introduce aufs_atomic_open() + - calls branch fs ->atomic_open() if exists. otherwise calls + vfs_create() and finish_open(). + - the demerit is that the several checks after branch fs + ->atomic_open() are lost. in the ordinary case, the checks are + done by VFS:do_last(), lookup_open() and atomic_open(). some can + be implemented in aufs, but not all I am afraid. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/03lookup.txt b/Documentation/filesystems/aufs/design/03lookup.txt --- a/Documentation/filesystems/aufs/design/03lookup.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/03lookup.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,113 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Lookup in a Branch +---------------------------------------------------------------------- +Since aufs has a character of sub-VFS (see Introduction), it operates +lookup for branches as VFS does. It may be a heavy work. But almost all +lookup operation in aufs is the simplest case, ie. lookup only an entry +directly connected to its parent. Digging down the directory hierarchy +is unnecessary. VFS has a function lookup_one_len() for that use, and +aufs calls it. + +When a branch is a remote filesystem, aufs basically relies upon its +->d_revalidate(), also aufs forces the hardest revalidate tests for +them. +For d_revalidate, aufs implements three levels of revalidate tests. See +"Revalidate Dentry and UDBA" in detail. + + +Test Only the Highest One for the Directory Permission (dirperm1 option) +---------------------------------------------------------------------- +Let's try case study. +- aufs has two branches, upper readwrite and lower readonly. + /au = /rw + /ro +- "dirA" exists under /ro, but /rw. and its mode is 0700. +- user invoked "chmod a+rx /au/dirA" +- the internal copy-up is activated and "/rw/dirA" is created and its + permission bits are set to world readable. +- then "/au/dirA" becomes world readable? + +In this case, /ro/dirA is still 0700 since it exists in readonly branch, +or it may be a natively readonly filesystem. If aufs respects the lower +branch, it should not respond readdir request from other users. But user +allowed it by chmod. Should really aufs rejects showing the entries +under /ro/dirA? + +To be honest, I don't have a good solution for this case. So aufs +implements 'dirperm1' and 'nodirperm1' mount options, and leave it to +users. +When dirperm1 is specified, aufs checks only the highest one for the +directory permission, and shows the entries. Otherwise, as usual, checks +every dir existing on all branches and rejects the request. + +As a side effect, dirperm1 option improves the performance of aufs +because the number of permission check is reduced when the number of +branch is many. + + +Revalidate Dentry and UDBA (User's Direct Branch Access) +---------------------------------------------------------------------- +Generally VFS helpers re-validate a dentry as a part of lookup. +0. digging down the directory hierarchy. +1. lock the parent dir by its i_mutex. +2. lookup the final (child) entry. +3. revalidate it. +4. call the actual operation (create, unlink, etc.) +5. unlock the parent dir + +If the filesystem implements its ->d_revalidate() (step 3), then it is +called. Actually aufs implements it and checks the dentry on a branch is +still valid. +But it is not enough. Because aufs has to release the lock for the +parent dir on a branch at the end of ->lookup() (step 2) and +->d_revalidate() (step 3) while the i_mutex of the aufs dir is still +held by VFS. +If the file on a branch is changed directly, eg. bypassing aufs, after +aufs released the lock, then the subsequent operation may cause +something unpleasant result. + +This situation is a result of VFS architecture, ->lookup() and +->d_revalidate() is separated. But I never say it is wrong. It is a good +design from VFS's point of view. It is just not suitable for sub-VFS +character in aufs. + +Aufs supports such case by three level of revalidation which is +selectable by user. +1. Simple Revalidate + Addition to the native flow in VFS's, confirm the child-parent + relationship on the branch just after locking the parent dir on the + branch in the "actual operation" (step 4). When this validation + fails, aufs returns EBUSY. ->d_revalidate() (step 3) in aufs still + checks the validation of the dentry on branches. +2. Monitor Changes Internally by Inotify/Fsnotify + Addition to above, in the "actual operation" (step 4) aufs re-lookup + the dentry on the branch, and returns EBUSY if it finds different + dentry. + Additionally, aufs sets the inotify/fsnotify watch for every dir on branches + during it is in cache. When the event is notified, aufs registers a + function to kernel 'events' thread by schedule_work(). And the + function sets some special status to the cached aufs dentry and inode + private data. If they are not cached, then aufs has nothing to + do. When the same file is accessed through aufs (step 0-3) later, + aufs will detect the status and refresh all necessary data. + In this mode, aufs has to ignore the event which is fired by aufs + itself. +3. No Extra Validation + This is the simplest test and doesn't add any additional revalidation + test, and skip the revalidation in step 4. It is useful and improves + aufs performance when system surely hide the aufs branches from user, + by over-mounting something (or another method). diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/04branch.txt b/Documentation/filesystems/aufs/design/04branch.txt --- a/Documentation/filesystems/aufs/design/04branch.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/04branch.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,74 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Branch Manipulation + +Since aufs supports dynamic branch manipulation, ie. add/remove a branch +and changing its permission/attribute, there are a lot of works to do. + + +Add a Branch +---------------------------------------------------------------------- +o Confirm the adding dir exists outside of aufs, including loopback + mount, and its various attributes. +o Initialize the xino file and whiteout bases if necessary. + See struct.txt. + +o Check the owner/group/mode of the directory + When the owner/group/mode of the adding directory differs from the + existing branch, aufs issues a warning because it may impose a + security risk. + For example, when a upper writable branch has a world writable empty + top directory, a malicious user can create any files on the writable + branch directly, like copy-up and modify manually. If something like + /etc/{passwd,shadow} exists on the lower readonly branch but the upper + writable branch, and the writable branch is world-writable, then a + malicious guy may create /etc/passwd on the writable branch directly + and the infected file will be valid in aufs. + I am afraid it can be a security issue, but aufs can do nothing except + producing a warning. + + +Delete a Branch +---------------------------------------------------------------------- +o Confirm the deleting branch is not busy + To be general, there is one merit to adopt "remount" interface to + manipulate branches. It is to discard caches. At deleting a branch, + aufs checks the still cached (and connected) dentries and inodes. If + there are any, then they are all in-use. An inode without its + corresponding dentry can be alive alone (for example, inotify/fsnotify case). + + For the cached one, aufs checks whether the same named entry exists on + other branches. + If the cached one is a directory, because aufs provides a merged view + to users, as long as one dir is left on any branch aufs can show the + dir to users. In this case, the branch can be removed from aufs. + Otherwise aufs rejects deleting the branch. + + If any file on the deleting branch is opened by aufs, then aufs + rejects deleting. + + +Modify the Permission of a Branch +---------------------------------------------------------------------- +o Re-initialize or remove the xino file and whiteout bases if necessary. + See struct.txt. + +o rw --> ro: Confirm the modifying branch is not busy + Aufs rejects the request if any of these conditions are true. + - a file on the branch is mmap-ed. + - a regular file on the branch is opened for write and there is no + same named entry on the upper branch. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/05wbr_policy.txt b/Documentation/filesystems/aufs/design/05wbr_policy.txt --- a/Documentation/filesystems/aufs/design/05wbr_policy.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/05wbr_policy.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,64 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Policies to Select One among Multiple Writable Branches +---------------------------------------------------------------------- +When the number of writable branch is more than one, aufs has to decide +the target branch for file creation or copy-up. By default, the highest +writable branch which has the parent (or ancestor) dir of the target +file is chosen (top-down-parent policy). +By user's request, aufs implements some other policies to select the +writable branch, for file creation several policies, round-robin, +most-free-space, and other policies. For copy-up, top-down-parent, +bottom-up-parent, bottom-up and others. + +As expected, the round-robin policy selects the branch in circular. When +you have two writable branches and creates 10 new files, 5 files will be +created for each branch. mkdir(2) systemcall is an exception. When you +create 10 new directories, all will be created on the same branch. +And the most-free-space policy selects the one which has most free +space among the writable branches. The amount of free space will be +checked by aufs internally, and users can specify its time interval. + +The policies for copy-up is more simple, +top-down-parent is equivalent to the same named on in create policy, +bottom-up-parent selects the writable branch where the parent dir +exists and the nearest upper one from the copyup-source, +bottom-up selects the nearest upper writable branch from the +copyup-source, regardless the existence of the parent dir. + +There are some rules or exceptions to apply these policies. +- If there is a readonly branch above the policy-selected branch and + the parent dir is marked as opaque (a variation of whiteout), or the + target (creating) file is whiteout-ed on the upper readonly branch, + then the result of the policy is ignored and the target file will be + created on the nearest upper writable branch than the readonly branch. +- If there is a writable branch above the policy-selected branch and + the parent dir is marked as opaque or the target file is whiteouted + on the branch, then the result of the policy is ignored and the target + file will be created on the highest one among the upper writable + branches who has diropq or whiteout. In case of whiteout, aufs removes + it as usual. +- link(2) and rename(2) systemcalls are exceptions in every policy. + They try selecting the branch where the source exists as possible + since copyup a large file will take long time. If it can't be, + ie. the branch where the source exists is readonly, then they will + follow the copyup policy. +- There is an exception for rename(2) when the target exists. + If the rename target exists, aufs compares the index of the branches + where the source and the target exists and selects the higher + one. If the selected branch is readonly, then aufs follows the + copyup policy. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/06fhsm.txt b/Documentation/filesystems/aufs/design/06fhsm.txt --- a/Documentation/filesystems/aufs/design/06fhsm.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/06fhsm.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,120 @@ + +# Copyright (C) 2011-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + +File-based Hierarchical Storage Management (FHSM) +---------------------------------------------------------------------- +Hierarchical Storage Management (or HSM) is a well-known feature in the +storage world. Aufs provides this feature as file-based with multiple +writable branches, based upon the principle of "Colder, the Lower". +Here the word "colder" means that the less used files, and "lower" means +that the position in the order of the stacked branches vertically. +These multiple writable branches are prioritized, ie. the topmost one +should be the fastest drive and be used heavily. + +o Characters in aufs FHSM story +- aufs itself and a new branch attribute. +- a new ioctl interface to move-down and to establish a connection with + the daemon ("move-down" is a converse of "copy-up"). +- userspace tool and daemon. + +The userspace daemon establishes a connection with aufs and waits for +the notification. The notified information is very similar to struct +statfs containing the number of consumed blocks and inodes. +When the consumed blocks/inodes of a branch exceeds the user-specified +upper watermark, the daemon activates its move-down process until the +consumed blocks/inodes reaches the user-specified lower watermark. + +The actual move-down is done by aufs based upon the request from +user-space since we need to maintain the inode number and the internal +pointer arrays in aufs. + +Currently aufs FHSM handles the regular files only. Additionally they +must not be hard-linked nor pseudo-linked. + + +o Cowork of aufs and the user-space daemon + During the userspace daemon established the connection, aufs sends a + small notification to it whenever aufs writes something into the + writable branch. But it may cost high since aufs issues statfs(2) + internally. So user can specify a new option to cache the + info. Actually the notification is controlled by these factors. + + the specified cache time. + + classified as "force" by aufs internally. + Until the specified time expires, aufs doesn't send the info + except the forced cases. When aufs decide forcing, the info is always + notified to userspace. + For example, the number of free inodes is generally large enough and + the shortage of it happens rarely. So aufs doesn't force the + notification when creating a new file, directory and others. This is + the typical case which aufs doesn't force. + When aufs writes the actual filedata and the files consumes any of new + blocks, the aufs forces notifying. + + +o Interfaces in aufs +- New branch attribute. + + fhsm + Specifies that the branch is managed by FHSM feature. In other word, + participant in the FHSM. + When nofhsm is set to the branch, it will not be the source/target + branch of the move-down operation. This attribute is set + independently from coo and moo attributes, and if you want full + FHSM, you should specify them as well. +- New mount option. + + fhsm_sec + Specifies a second to suppress many less important info to be + notified. +- New ioctl. + + AUFS_CTL_FHSM_FD + create a new file descriptor which userspace can read the notification + (a subset of struct statfs) from aufs. +- Module parameter 'brs' + It has to be set to 1. Otherwise the new mount option 'fhsm' will not + be set. +- mount helpers /sbin/mount.aufs and /sbin/umount.aufs + When there are two or more branches with fhsm attributes, + /sbin/mount.aufs invokes the user-space daemon and /sbin/umount.aufs + terminates it. As a result of remounting and branch-manipulation, the + number of branches with fhsm attribute can be one. In this case, + /sbin/mount.aufs will terminate the user-space daemon. + + +Finally the operation is done as these steps in kernel-space. +- make sure that, + + no one else is using the file. + + the file is not hard-linked. + + the file is not pseudo-linked. + + the file is a regular file. + + the parent dir is not opaqued. +- find the target writable branch. +- make sure the file is not whiteout-ed by the upper (than the target) + branch. +- make the parent dir on the target branch. +- mutex lock the inode on the branch. +- unlink the whiteout on the target branch (if exists). +- lookup and create the whiteout-ed temporary name on the target branch. +- copy the file as the whiteout-ed temporary name on the target branch. +- rename the whiteout-ed temporary name to the original name. +- unlink the file on the source branch. +- maintain the internal pointer array and the external inode number + table (XINO). +- maintain the timestamps and other attributes of the parent dir and the + file. + +And of course, in every step, an error may happen. So the operation +should restore the original file state after an error happens. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/06mmap.txt b/Documentation/filesystems/aufs/design/06mmap.txt --- a/Documentation/filesystems/aufs/design/06mmap.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/06mmap.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,72 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +mmap(2) -- File Memory Mapping +---------------------------------------------------------------------- +In aufs, the file-mapped pages are handled by a branch fs directly, no +interaction with aufs. It means aufs_mmap() calls the branch fs's +->mmap(). +This approach is simple and good, but there is one problem. +Under /proc, several entries show the mmapped files by its path (with +device and inode number), and the printed path will be the path on the +branch fs's instead of virtual aufs's. +This is not a problem in most cases, but some utilities lsof(1) (and its +user) may expect the path on aufs. + +To address this issue, aufs adds a new member called vm_prfile in struct +vm_area_struct (and struct vm_region). The original vm_file points to +the file on the branch fs in order to handle everything correctly as +usual. The new vm_prfile points to a virtual file in aufs, and the +show-functions in procfs refers to vm_prfile if it is set. +Also we need to maintain several other places where touching vm_file +such like +- fork()/clone() copies vma and the reference count of vm_file is + incremented. +- merging vma maintains the ref count too. + +This is not a good approach. It just fakes the printed path. But it +leaves all behaviour around f_mapping unchanged. This is surely an +advantage. +Actually aufs had adopted another complicated approach which calls +generic_file_mmap() and handles struct vm_operations_struct. In this +approach, aufs met a hard problem and I could not solve it without +switching the approach. + +There may be one more another approach which is +- bind-mount the branch-root onto the aufs-root internally +- grab the new vfsmount (ie. struct mount) +- lazy-umount the branch-root internally +- in open(2) the aufs-file, open the branch-file with the hidden + vfsmount (instead of the original branch's vfsmount) +- ideally this "bind-mount and lazy-umount" should be done atomically, + but it may be possible from userspace by the mount helper. + +Adding the internal hidden vfsmount and using it in opening a file, the +file path under /proc will be printed correctly. This approach looks +smarter, but is not possible I am afraid. +- aufs-root may be bind-mount later. when it happens, another hidden + vfsmount will be required. +- it is hard to get the chance to bind-mount and lazy-umount + + in kernel-space, FS can have vfsmount in open(2) via + file->f_path, and aufs can know its vfsmount. But several locks are + already acquired, and if aufs tries to bind-mount and lazy-umount + here, then it may cause a deadlock. + + in user-space, bind-mount doesn't invoke the mount helper. +- since /proc shows dev and ino, aufs has to give vma these info. it + means a new member vm_prinode will be necessary. this is essentially + equivalent to vm_prfile described above. + +I have to give up this "looks-smater" approach. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/06xattr.txt b/Documentation/filesystems/aufs/design/06xattr.txt --- a/Documentation/filesystems/aufs/design/06xattr.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/06xattr.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,96 @@ + +# Copyright (C) 2014-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + +Listing XATTR/EA and getting the value +---------------------------------------------------------------------- +For the inode standard attributes (owner, group, timestamps, etc.), aufs +shows the values from the topmost existing file. This behaviour is good +for the non-dir entries since the bahaviour exactly matches the shown +information. But for the directories, aufs considers all the same named +entries on the lower branches. Which means, if one of the lower entry +rejects readdir call, then aufs returns an error even if the topmost +entry allows it. This behaviour is necessary to respect the branch fs's +security, but can make users confused since the user-visible standard +attributes don't match the behaviour. +To address this issue, aufs has a mount option called dirperm1 which +checks the permission for the topmost entry only, and ignores the lower +entry's permission. + +A similar issue can happen around XATTR. +getxattr(2) and listxattr(2) families behave as if dirperm1 option is +always set. Otherwise these very unpleasant situation would happen. +- listxattr(2) may return the duplicated entries. +- users may not be able to remove or reset the XATTR forever, + + +XATTR/EA support in the internal (copy,move)-(up,down) +---------------------------------------------------------------------- +Generally the extended attributes of inode are categorized as these. +- "security" for LSM and capability. +- "system" for posix ACL, 'acl' mount option is required for the branch + fs generally. +- "trusted" for userspace, CAP_SYS_ADMIN is required. +- "user" for userspace, 'user_xattr' mount option is required for the + branch fs generally. + +Moreover there are some other categories. Aufs handles these rather +unpopular categories as the ordinary ones, ie. there is no special +condition nor exception. + +In copy-up, the support for XATTR on the dst branch may differ from the +src branch. In this case, the copy-up operation will get an error and +the original user operation which triggered the copy-up will fail. It +can happen that even all copy-up will fail. +When both of src and dst branches support XATTR and if an error occurs +during copying XATTR, then the copy-up should fail obviously. That is a +good reason and aufs should return an error to userspace. But when only +the src branch support that XATTR, aufs should not return an error. +For example, the src branch supports ACL but the dst branch doesn't +because the dst branch may natively un-support it or temporary +un-support it due to "noacl" mount option. Of course, the dst branch fs +may NOT return an error even if the XATTR is not supported. It is +totally up to the branch fs. + +Anyway when the aufs internal copy-up gets an error from the dst branch +fs, then aufs tries removing the just copied entry and returns the error +to the userspace. The worst case of this situation will be all copy-up +will fail. + +For the copy-up operation, there two basic approaches. +- copy the specified XATTR only (by category above), and return the + error unconditionally if it happens. +- copy all XATTR, and ignore the error on the specified category only. + +In order to support XATTR and to implement the correct behaviour, aufs +chooses the latter approach and introduces some new branch attributes, +"icexsec", "icexsys", "icextr", "icexusr", and "icexoth". +They correspond to the XATTR namespaces (see above). Additionally, to be +convenient, "icex" is also provided which means all "icex*" attributes +are set (here the word "icex" stands for "ignore copy-error on XATTR"). + +The meaning of these attributes is to ignore the error from setting +XATTR on that branch. +Note that aufs tries copying all XATTR unconditionally, and ignores the +error from the dst branch according to the specified attributes. + +Some XATTR may have its default value. The default value may come from +the parent dir or the environment. If the default value is set at the +file creating-time, it will be overwritten by copy-up. +Some contradiction may happen I am afraid. +Do we need another attribute to stop copying XATTR? I am unsure. For +now, aufs implements the branch attributes to ignore the error. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/07export.txt b/Documentation/filesystems/aufs/design/07export.txt --- a/Documentation/filesystems/aufs/design/07export.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/07export.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,58 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Export Aufs via NFS +---------------------------------------------------------------------- +Here is an approach. +- like xino/xib, add a new file 'xigen' which stores aufs inode + generation. +- iget_locked(): initialize aufs inode generation for a new inode, and + store it in xigen file. +- destroy_inode(): increment aufs inode generation and store it in xigen + file. it is necessary even if it is not unlinked, because any data of + inode may be changed by UDBA. +- encode_fh(): for a root dir, simply return FILEID_ROOT. otherwise + build file handle by + + branch id (4 bytes) + + superblock generation (4 bytes) + + inode number (4 or 8 bytes) + + parent dir inode number (4 or 8 bytes) + + inode generation (4 bytes)) + + return value of exportfs_encode_fh() for the parent on a branch (4 + bytes) + + file handle for a branch (by exportfs_encode_fh()) +- fh_to_dentry(): + + find the index of a branch from its id in handle, and check it is + still exist in aufs. + + 1st level: get the inode number from handle and search it in cache. + + 2nd level: if not found in cache, get the parent inode number from + the handle and search it in cache. and then open the found parent + dir, find the matching inode number by vfs_readdir() and get its + name, and call lookup_one_len() for the target dentry. + + 3rd level: if the parent dir is not cached, call + exportfs_decode_fh() for a branch and get the parent on a branch, + build a pathname of it, convert it a pathname in aufs, call + path_lookup(). now aufs gets a parent dir dentry, then handle it as + the 2nd level. + + to open the dir, aufs needs struct vfsmount. aufs keeps vfsmount + for every branch, but not itself. to get this, (currently) aufs + searches in current->nsproxy->mnt_ns list. it may not be a good + idea, but I didn't get other approach. + + test the generation of the gotten inode. +- every inode operation: they may get EBUSY due to UDBA. in this case, + convert it into ESTALE for NFSD. +- readdir(): call lockdep_on/off() because filldir in NFSD calls + lookup_one_len(), vfs_getattr(), encode_fh() and others. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/08shwh.txt b/Documentation/filesystems/aufs/design/08shwh.txt --- a/Documentation/filesystems/aufs/design/08shwh.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/08shwh.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,52 @@ + +# Copyright (C) 2005-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Show Whiteout Mode (shwh) +---------------------------------------------------------------------- +Generally aufs hides the name of whiteouts. But in some cases, to show +them is very useful for users. For instance, creating a new middle layer +(branch) by merging existing layers. + +(borrowing aufs1 HOW-TO from a user, Michael Towers) +When you have three branches, +- Bottom: 'system', squashfs (underlying base system), read-only +- Middle: 'mods', squashfs, read-only +- Top: 'overlay', ram (tmpfs), read-write + +The top layer is loaded at boot time and saved at shutdown, to preserve +the changes made to the system during the session. +When larger changes have been made, or smaller changes have accumulated, +the size of the saved top layer data grows. At this point, it would be +nice to be able to merge the two overlay branches ('mods' and 'overlay') +and rewrite the 'mods' squashfs, clearing the top layer and thus +restoring save and load speed. + +This merging is simplified by the use of another aufs mount, of just the +two overlay branches using the 'shwh' option. +# mount -t aufs -o ro,shwh,br:/livesys/overlay=ro+wh:/livesys/mods=rr+wh \ + aufs /livesys/merge_union + +A merged view of these two branches is then available at +/livesys/merge_union, and the new feature is that the whiteouts are +visible! +Note that in 'shwh' mode the aufs mount must be 'ro', which will disable +writing to all branches. Also the default mode for all branches is 'ro'. +It is now possible to save the combined contents of the two overlay +branches to a new squashfs, e.g.: +# mksquashfs /livesys/merge_union /path/to/newmods.squash + +This new squashfs archive can be stored on the boot device and the +initramfs will use it to replace the old one at the next boot. diff -Naur --no-dereference a/Documentation/filesystems/aufs/design/10dynop.txt b/Documentation/filesystems/aufs/design/10dynop.txt --- a/Documentation/filesystems/aufs/design/10dynop.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/design/10dynop.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,47 @@ + +# Copyright (C) 2010-2016 Junjiro R. Okajima +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +Dynamically customizable FS operations +---------------------------------------------------------------------- +Generally FS operations (struct inode_operations, struct +address_space_operations, struct file_operations, etc.) are defined as +"static const", but it never means that FS have only one set of +operation. Some FS have multiple sets of them. For instance, ext2 has +three sets, one for XIP, for NOBH, and for normal. +Since aufs overrides and redirects these operations, sometimes aufs has +to change its behaviour according to the branch FS type. More importantly +VFS acts differently if a function (member in the struct) is set or +not. It means aufs should have several sets of operations and select one +among them according to the branch FS definition. + +In order to solve this problem and not to affect the behaviour of VFS, +aufs defines these operations dynamically. For instance, aufs defines +dummy direct_IO function for struct address_space_operations, but it may +not be set to the address_space_operations actually. When the branch FS +doesn't have it, aufs doesn't set it to its address_space_operations +while the function definition itself is still alive. So the behaviour +itself will not change, and it will return an error when direct_IO is +not set. + +The lifetime of these dynamically generated operation object is +maintained by aufs branch object. When the branch is removed from aufs, +the reference counter of the object is decremented. When it reaches +zero, the dynamically generated operation object will be freed. + +This approach is designed to support AIO (io_submit), Direct I/O and +XIP (DAX) mainly. +Currently this approach is applied to address_space_operations for +regular files only. diff -Naur --no-dereference a/Documentation/filesystems/aufs/README b/Documentation/filesystems/aufs/README --- a/Documentation/filesystems/aufs/README 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/filesystems/aufs/README 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,391 @@ + +Aufs4 -- advanced multi layered unification filesystem version 4.x +http://aufs.sf.net +Junjiro R. Okajima + + +0. Introduction +---------------------------------------- +In the early days, aufs was entirely re-designed and re-implemented +Unionfs Version 1.x series. Adding many original ideas, approaches, +improvements and implementations, it becomes totally different from +Unionfs while keeping the basic features. +Recently, Unionfs Version 2.x series begin taking some of the same +approaches to aufs1's. +Unionfs is being developed by Professor Erez Zadok at Stony Brook +University and his team. + +Aufs4 supports linux-4.0 and later, and for linux-3.x series try aufs3. +If you want older kernel version support, try aufs2-2.6.git or +aufs2-standalone.git repository, aufs1 from CVS on SourceForge. + +Note: it becomes clear that "Aufs was rejected. Let's give it up." + According to Christoph Hellwig, linux rejects all union-type + filesystems but UnionMount. + + +PS. Al Viro seems have a plan to merge aufs as well as overlayfs and + UnionMount, and he pointed out an issue around a directory mutex + lock and aufs addressed it. But it is still unsure whether aufs will + be merged (or any other union solution). + + + +1. Features +---------------------------------------- +- unite several directories into a single virtual filesystem. The member + directory is called as a branch. +- you can specify the permission flags to the branch, which are 'readonly', + 'readwrite' and 'whiteout-able.' +- by upper writable branch, internal copyup and whiteout, files/dirs on + readonly branch are modifiable logically. +- dynamic branch manipulation, add, del. +- etc... + +Also there are many enhancements in aufs, such as: +- test only the highest one for the directory permission (dirperm1) +- copyup on open (coo=) +- 'move' policy for copy-up between two writable branches, after + checking free space. +- xattr, acl +- readdir(3) in userspace. +- keep inode number by external inode number table +- keep the timestamps of file/dir in internal copyup operation +- seekable directory, supporting NFS readdir. +- whiteout is hardlinked in order to reduce the consumption of inodes + on branch +- do not copyup, nor create a whiteout when it is unnecessary +- revert a single systemcall when an error occurs in aufs +- remount interface instead of ioctl +- maintain /etc/mtab by an external command, /sbin/mount.aufs. +- loopback mounted filesystem as a branch +- kernel thread for removing the dir who has a plenty of whiteouts +- support copyup sparse file (a file which has a 'hole' in it) +- default permission flags for branches +- selectable permission flags for ro branch, whether whiteout can + exist or not +- export via NFS. +- support /fs/aufs and /aufs. +- support multiple writable branches, some policies to select one + among multiple writable branches. +- a new semantics for link(2) and rename(2) to support multiple + writable branches. +- no glibc changes are required. +- pseudo hardlink (hardlink over branches) +- allow a direct access manually to a file on branch, e.g. bypassing aufs. + including NFS or remote filesystem branch. +- userspace wrapper for pathconf(3)/fpathconf(3) with _PC_LINK_MAX. +- and more... + +Currently these features are dropped temporary from aufs4. +See design/08plan.txt in detail. +- nested mount, i.e. aufs as readonly no-whiteout branch of another aufs + (robr) +- statistics of aufs thread (/sys/fs/aufs/stat) + +Features or just an idea in the future (see also design/*.txt), +- reorder the branch index without del/re-add. +- permanent xino files for NFSD +- an option for refreshing the opened files after add/del branches +- light version, without branch manipulation. (unnecessary?) +- copyup in userspace +- inotify in userspace +- readv/writev + + +2. Download +---------------------------------------- +There are three GIT trees for aufs4, aufs4-linux.git, +aufs4-standalone.git, and aufs-util.git. Note that there is no "4" in +"aufs-util.git." +While the aufs-util is always necessary, you need either of aufs4-linux +or aufs4-standalone. + +The aufs4-linux tree includes the whole linux mainline GIT tree, +git://git.kernel.org/.../torvalds/linux.git. +And you cannot select CONFIG_AUFS_FS=m for this version, eg. you cannot +build aufs4 as an external kernel module. +Several extra patches are not included in this tree. Only +aufs4-standalone tree contains them. They are described in the later +section "Configuration and Compilation." + +On the other hand, the aufs4-standalone tree has only aufs source files +and necessary patches, and you can select CONFIG_AUFS_FS=m. +But you need to apply all aufs patches manually. + +You will find GIT branches whose name is in form of "aufs4.x" where "x" +represents the linux kernel version, "linux-4.x". For instance, +"aufs4.0" is for linux-4.0. For latest "linux-4.x-rcN", use +"aufs4.x-rcN" branch. + +o aufs4-linux tree +$ git clone --reference /your/linux/git/tree \ + git://github.com/sfjro/aufs4-linux.git aufs4-linux.git +- if you don't have linux GIT tree, then remove "--reference ..." +$ cd aufs4-linux.git +$ git checkout origin/aufs4.0 + +Or You may want to directly git-pull aufs into your linux GIT tree, and +leave the patch-work to GIT. +$ cd /your/linux/git/tree +$ git remote add aufs4 git://github.com/sfjro/aufs4-linux.git +$ git fetch aufs4 +$ git checkout -b my4.0 v4.0 +$ (add your local change...) +$ git pull aufs4 aufs4.0 +- now you have v4.0 + your_changes + aufs4.0 in you my4.0 branch. +- you may need to solve some conflicts between your_changes and + aufs4.0. in this case, git-rerere is recommended so that you can + solve the similar conflicts automatically when you upgrade to 4.1 or + later in the future. + +o aufs4-standalone tree +$ git clone git://github.com/sfjro/aufs4-standalone.git aufs4-standalone.git +$ cd aufs4-standalone.git +$ git checkout origin/aufs4.0 + +o aufs-util tree +$ git clone git://git.code.sf.net/p/aufs/aufs-util aufs-util.git +- note that the public aufs-util.git is on SourceForge instead of + GitHUB. +$ cd aufs-util.git +$ git checkout origin/aufs4.0 + +Note: The 4.x-rcN branch is to be used with `rc' kernel versions ONLY. +The minor version number, 'x' in '4.x', of aufs may not always +follow the minor version number of the kernel. +Because changes in the kernel that cause the use of a new +minor version number do not always require changes to aufs-util. + +Since aufs-util has its own minor version number, you may not be +able to find a GIT branch in aufs-util for your kernel's +exact minor version number. +In this case, you should git-checkout the branch for the +nearest lower number. + +For (an unreleased) example: +If you are using "linux-4.10" and the "aufs4.10" branch +does not exist in aufs-util repository, then "aufs4.9", "aufs4.8" +or something numerically smaller is the branch for your kernel. + +Also you can view all branches by + $ git branch -a + + +3. Configuration and Compilation +---------------------------------------- +Make sure you have git-checkout'ed the correct branch. + +For aufs4-linux tree, +- enable CONFIG_AUFS_FS. +- set other aufs configurations if necessary. + +For aufs4-standalone tree, +There are several ways to build. + +1. +- apply ./aufs4-kbuild.patch to your kernel source files. +- apply ./aufs4-base.patch too. +- apply ./aufs4-mmap.patch too. +- apply ./aufs4-standalone.patch too, if you have a plan to set + CONFIG_AUFS_FS=m. otherwise you don't need ./aufs4-standalone.patch. +- copy ./{Documentation,fs,include/uapi/linux/aufs_type.h} files to your + kernel source tree. Never copy $PWD/include/uapi/linux/Kbuild. +- enable CONFIG_AUFS_FS, you can select either + =m or =y. +- and build your kernel as usual. +- install the built kernel. + Note: Since linux-3.9, every filesystem module requires an alias + "fs-". You should make sure that "fs-aufs" is listed in your + modules.aliases file if you set CONFIG_AUFS_FS=m. +- install the header files too by "make headers_install" to the + directory where you specify. By default, it is $PWD/usr. + "make help" shows a brief note for headers_install. +- and reboot your system. + +2. +- module only (CONFIG_AUFS_FS=m). +- apply ./aufs4-base.patch to your kernel source files. +- apply ./aufs4-mmap.patch too. +- apply ./aufs4-standalone.patch too. +- build your kernel, don't forget "make headers_install", and reboot. +- edit ./config.mk and set other aufs configurations if necessary. + Note: You should read $PWD/fs/aufs/Kconfig carefully which describes + every aufs configurations. +- build the module by simple "make". + Note: Since linux-3.9, every filesystem module requires an alias + "fs-". You should make sure that "fs-aufs" is listed in your + modules.aliases file. +- you can specify ${KDIR} make variable which points to your kernel + source tree. +- install the files + + run "make install" to install the aufs module, or copy the built + $PWD/aufs.ko to /lib/modules/... and run depmod -a (or reboot simply). + + run "make install_headers" (instead of headers_install) to install + the modified aufs header file (you can specify DESTDIR which is + available in aufs standalone version's Makefile only), or copy + $PWD/usr/include/linux/aufs_type.h to /usr/include/linux or wherever + you like manually. By default, the target directory is $PWD/usr. +- no need to apply aufs4-kbuild.patch, nor copying source files to your + kernel source tree. + +Note: The header file aufs_type.h is necessary to build aufs-util + as well as "make headers_install" in the kernel source tree. + headers_install is subject to be forgotten, but it is essentially + necessary, not only for building aufs-util. + You may not meet problems without headers_install in some older + version though. + +And then, +- read README in aufs-util, build and install it +- note that your distribution may contain an obsoleted version of + aufs_type.h in /usr/include/linux or something. When you build aufs + utilities, make sure that your compiler refers the correct aufs header + file which is built by "make headers_install." +- if you want to use readdir(3) in userspace or pathconf(3) wrapper, + then run "make install_ulib" too. And refer to the aufs manual in + detail. + +There several other patches in aufs4-standalone.git. They are all +optional. When you meet some problems, they will help you. +- aufs4-loopback.patch + Supports a nested loopback mount in a branch-fs. This patch is + unnecessary until aufs produces a message like "you may want to try + another patch for loopback file". +- vfs-ino.patch + Modifies a system global kernel internal function get_next_ino() in + order to stop assigning 0 for an inode-number. Not directly related to + aufs, but recommended generally. +- tmpfs-idr.patch + Keeps the tmpfs inode number as the lowest value. Effective to reduce + the size of aufs XINO files for tmpfs branch. Also it prevents the + duplication of inode number, which is important for backup tools and + other utilities. When you find aufs XINO files for tmpfs branch + growing too much, try this patch. +- lockdep-debug.patch + Because aufs is not only an ordinary filesystem (callee of VFS), but + also a caller of VFS functions for branch filesystems, subclassing of + the internal locks for LOCKDEP is necessary. LOCKDEP is a debugging + feature of linux kernel. If you enable CONFIG_LOCKDEP, then you will + need to apply this debug patch to expand several constant values. + If don't know what LOCKDEP, then you don't have apply this patch. + + +4. Usage +---------------------------------------- +At first, make sure aufs-util are installed, and please read the aufs +manual, aufs.5 in aufs-util.git tree. +$ man -l aufs.5 + +And then, +$ mkdir /tmp/rw /tmp/aufs +# mount -t aufs -o br=/tmp/rw:${HOME} none /tmp/aufs + +Here is another example. The result is equivalent. +# mount -t aufs -o br=/tmp/rw=rw:${HOME}=ro none /tmp/aufs + Or +# mount -t aufs -o br:/tmp/rw none /tmp/aufs +# mount -o remount,append:${HOME} /tmp/aufs + +Then, you can see whole tree of your home dir through /tmp/aufs. If +you modify a file under /tmp/aufs, the one on your home directory is +not affected, instead the same named file will be newly created under +/tmp/rw. And all of your modification to a file will be applied to +the one under /tmp/rw. This is called the file based Copy on Write +(COW) method. +Aufs mount options are described in aufs.5. +If you run chroot or something and make your aufs as a root directory, +then you need to customize the shutdown script. See the aufs manual in +detail. + +Additionally, there are some sample usages of aufs which are a +diskless system with network booting, and LiveCD over NFS. +See sample dir in CVS tree on SourceForge. + + +5. Contact +---------------------------------------- +When you have any problems or strange behaviour in aufs, please let me +know with: +- /proc/mounts (instead of the output of mount(8)) +- /sys/module/aufs/* +- /sys/fs/aufs/* (if you have them) +- /debug/aufs/* (if you have them) +- linux kernel version + if your kernel is not plain, for example modified by distributor, + the url where i can download its source is necessary too. +- aufs version which was printed at loading the module or booting the + system, instead of the date you downloaded. +- configuration (define/undefine CONFIG_AUFS_xxx) +- kernel configuration or /proc/config.gz (if you have it) +- behaviour which you think to be incorrect +- actual operation, reproducible one is better +- mailto: aufs-users at lists.sourceforge.net + +Usually, I don't watch the Public Areas(Bugs, Support Requests, Patches, +and Feature Requests) on SourceForge. Please join and write to +aufs-users ML. + + +6. Acknowledgements +---------------------------------------- +Thanks to everyone who have tried and are using aufs, whoever +have reported a bug or any feedback. + +Especially donators: +Tomas Matejicek(slax.org) made a donation (much more than once). + Since Apr 2010, Tomas M (the author of Slax and Linux Live + scripts) is making "doubling" donations. + Unfortunately I cannot list all of the donators, but I really + appreciate. + It ends Aug 2010, but the ordinary donation URL is still available. + +Dai Itasaka made a donation (2007/8). +Chuck Smith made a donation (2008/4, 10 and 12). +Henk Schoneveld made a donation (2008/9). +Chih-Wei Huang, ASUS, CTC donated Eee PC 4G (2008/10). +Francois Dupoux made a donation (2008/11). +Bruno Cesar Ribas and Luis Carlos Erpen de Bona, C3SL serves public + aufs2 GIT tree (2009/2). +William Grant made a donation (2009/3). +Patrick Lane made a donation (2009/4). +The Mail Archive (mail-archive.com) made donations (2009/5). +Nippy Networks (Ed Wildgoose) made a donation (2009/7). +New Dream Network, LLC (www.dreamhost.com) made a donation (2009/11). +Pavel Pronskiy made a donation (2011/2). +Iridium and Inmarsat satellite phone retailer (www.mailasail.com), Nippy + Networks (Ed Wildgoose) made a donation for hardware (2011/3). +Max Lekomcev (DOM-TV project) made a donation (2011/7, 12, 2012/3, 6 and +11). +Sam Liddicott made a donation (2011/9). +Era Scarecrow made a donation (2013/4). +Bor Ratajc made a donation (2013/4). +Alessandro Gorreta made a donation (2013/4). +POIRETTE Marc made a donation (2013/4). +Alessandro Gorreta made a donation (2013/4). +lauri kasvandik made a donation (2013/5). +"pemasu from Finland" made a donation (2013/7). +The Parted Magic Project made a donation (2013/9 and 11). +Pavel Barta made a donation (2013/10). +Nikolay Pertsev made a donation (2014/5). +James B made a donation (2014/7 and 2015/7). +Stefano Di Biase made a donation (2014/8). +Daniel Epellei made a donation (2015/1). +OmegaPhil made a donation (2016/1). + +Thank you very much. +Donations are always, including future donations, very important and +helpful for me to keep on developing aufs. + + +7. +---------------------------------------- +If you are an experienced user, no explanation is needed. Aufs is +just a linux filesystem. + + +Enjoy! + +# Local variables: ; +# mode: text; +# End: ; diff -Naur --no-dereference a/Documentation/filesystems/configfs/configfs.txt b/Documentation/filesystems/configfs/configfs.txt --- a/Documentation/filesystems/configfs/configfs.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/filesystems/configfs/configfs.txt 2016-05-11 13:31:53.189225170 -0400 @@ -51,15 +51,27 @@ An item is created via mkdir(2). The item's attributes will also appear at this time. readdir(3) can determine what the attributes are, read(2) can query their default values, and write(2) can store new -values. Like sysfs, attributes should be ASCII text files, preferably -with only one value per file. The same efficiency caveats from sysfs -apply. Don't mix more than one attribute in one attribute file. - -Like sysfs, configfs expects write(2) to store the entire buffer at -once. When writing to configfs attributes, userspace processes should -first read the entire file, modify the portions they wish to change, and -then write the entire buffer back. Attribute files have a maximum size -of one page (PAGE_SIZE, 4096 on i386). +values. Don't mix more than one attribute in one attribute file. + +There are two types of configfs attributes: + +* Normal attributes, which similar to sysfs attributes, are small ASCII text +files, with a maximum size of one page (PAGE_SIZE, 4096 on i386). Preferably +only one value per file should be used, and the same caveats from sysfs apply. +Configfs expects write(2) to store the entire buffer at once. When writing to +normal configfs attributes, userspace processes should first read the entire +file, modify the portions they wish to change, and then write the entire +buffer back. + +* Binary attributes, which are somewhat similar to sysfs binary attributes, +but with a few slight changes to semantics. The PAGE_SIZE limitation does not +apply, but the whole binary item must fit in single kernel vmalloc'ed buffer. +The write(2) calls from user space are buffered, and the attributes' +write_bin_attribute method will be invoked on the final close, therefore it is +imperative for user-space to check the return code of close(2) in order to +verify that the operation finished successfully. +To avoid a malicious user OOMing the kernel, there's a per-binary attribute +maximum buffer value. When an item needs to be destroyed, remove it with rmdir(2). An item cannot be destroyed if any other item has a link to it (via @@ -171,6 +183,7 @@ struct configfs_item_operations *ct_item_ops; struct configfs_group_operations *ct_group_ops; struct configfs_attribute **ct_attrs; + struct configfs_bin_attribute **ct_bin_attrs; }; The most basic function of a config_item_type is to define what @@ -201,6 +214,32 @@ attribute is writable and provides a ->store method, that method will be be called whenever userspace asks for a write(2) on the attribute. +[struct configfs_bin_attribute] + + struct configfs_attribute { + struct configfs_attribute cb_attr; + void *cb_private; + size_t cb_max_size; + }; + +The binary attribute is used when the one needs to use binary blob to +appear as the contents of a file in the item's configfs directory. +To do so add the binary attribute to the NULL-terminated array +config_item_type->ct_bin_attrs, and the item appears in configfs, the +attribute file will appear with the configfs_bin_attribute->cb_attr.ca_name +filename. configfs_bin_attribute->cb_attr.ca_mode specifies the file +permissions. +The cb_private member is provided for use by the driver, while the +cb_max_size member specifies the maximum amount of vmalloc buffer +to be used. + +If binary attribute is readable and the config_item provides a +ct_item_ops->read_bin_attribute() method, that method will be called +whenever userspace asks for a read(2) on the attribute. The converse +will happen for write(2). The reads/writes are bufferred so only a +single read/write will occur; the attributes' need not concern itself +with it. + [struct config_group] A config_item cannot live in a vacuum. The only way one can be created diff -Naur --no-dereference a/Documentation/hwlat_detector.txt b/Documentation/hwlat_detector.txt --- a/Documentation/hwlat_detector.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/hwlat_detector.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,64 @@ +Introduction: +------------- + +The module hwlat_detector is a special purpose kernel module that is used to +detect large system latencies induced by the behavior of certain underlying +hardware or firmware, independent of Linux itself. The code was developed +originally to detect SMIs (System Management Interrupts) on x86 systems, +however there is nothing x86 specific about this patchset. It was +originally written for use by the "RT" patch since the Real Time +kernel is highly latency sensitive. + +SMIs are usually not serviced by the Linux kernel, which typically does not +even know that they are occuring. SMIs are instead are set up by BIOS code +and are serviced by BIOS code, usually for "critical" events such as +management of thermal sensors and fans. Sometimes though, SMIs are used for +other tasks and those tasks can spend an inordinate amount of time in the +handler (sometimes measured in milliseconds). Obviously this is a problem if +you are trying to keep event service latencies down in the microsecond range. + +The hardware latency detector works by hogging all of the cpus for configurable +amounts of time (by calling stop_machine()), polling the CPU Time Stamp Counter +for some period, then looking for gaps in the TSC data. Any gap indicates a +time when the polling was interrupted and since the machine is stopped and +interrupts turned off the only thing that could do that would be an SMI. + +Note that the SMI detector should *NEVER* be used in a production environment. +It is intended to be run manually to determine if the hardware platform has a +problem with long system firmware service routines. + +Usage: +------ + +Loading the module hwlat_detector passing the parameter "enabled=1" (or by +setting the "enable" entry in "hwlat_detector" debugfs toggled on) is the only +step required to start the hwlat_detector. It is possible to redefine the +threshold in microseconds (us) above which latency spikes will be taken +into account (parameter "threshold="). + +Example: + + # modprobe hwlat_detector enabled=1 threshold=100 + +After the module is loaded, it creates a directory named "hwlat_detector" under +the debugfs mountpoint, "/debug/hwlat_detector" for this text. It is necessary +to have debugfs mounted, which might be on /sys/debug on your system. + +The /debug/hwlat_detector interface contains the following files: + +count - number of latency spikes observed since last reset +enable - a global enable/disable toggle (0/1), resets count +max - maximum hardware latency actually observed (usecs) +sample - a pipe from which to read current raw sample data + in the format + (can be opened O_NONBLOCK for a single sample) +threshold - minimum latency value to be considered (usecs) +width - time period to sample with CPUs held (usecs) + must be less than the total window size (enforced) +window - total period of sampling, width being inside (usecs) + +By default we will set width to 500,000 and window to 1,000,000, meaning that +we will sample every 1,000,000 usecs (1s) for 500,000 usecs (0.5s). If we +observe any latencies that exceed the threshold (initially 100 usecs), +then we write to a global sample ring buffer of 8K samples, which is +consumed by reading from the "sample" (pipe) debugfs file interface. diff -Naur --no-dereference a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt --- a/Documentation/kernel-parameters.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/kernel-parameters.txt 2016-05-11 13:31:53.189225170 -0400 @@ -90,6 +90,7 @@ NET Appropriate network support is enabled. NUMA NUMA support is enabled. NFS Appropriate NFS support is enabled. + OF Open Firmware support (device tree) is enabled. OSS OSS sound support is enabled. PV_OPS A paravirtualized kernel is enabled. PARIDE The ParIDE (parallel port IDE) subsystem is enabled. @@ -1629,6 +1630,15 @@ ip= [IP_PNP] See Documentation/filesystems/nfs/nfsroot.txt. + irqaffinity= [SMP] Set the default irq affinity mask + Format: + ,..., + or + - + (must be a positive range in ascending order) + or a mixture + ,...,- + irqfixup [HW] When an interrupt is not handled search all handlers for it. Intended to get systems with badly broken @@ -2618,6 +2628,8 @@ This can be set from sysctl after boot. See Documentation/sysctl/vm.txt for details. + of_overlay_disable [OF] Disable device tree overlays at boot time. + ohci1394_dma=early [HW] enable debugging via the ohci1394 driver. See Documentation/debugging-via-ohci1394.txt for more info. diff -Naur --no-dereference a/Documentation/misc-devices/bone_capemgr.txt b/Documentation/misc-devices/bone_capemgr.txt --- a/Documentation/misc-devices/bone_capemgr.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/misc-devices/bone_capemgr.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,63 @@ +--------------------------- + Beaglebone Cape-Manager +--------------------------- + +The beaglebone cape manager driver allows the automatic use of external +peripheral capes to be automatically supported by Linux without any manual +setup required by the user. + +Each beaglebone cape should contain an EEPROM that describes +it in a fixed I2C address on the i2c2 bus of the baseboard. +The format of the EEPROM is defined in the beaglebone reference +manual at: +http://beagleboard.org/static/beaglebone/latest/Docs/Hardware/BONE_SRM.pdf + +Reading the part number and revision information the manager +requests a firmware file formatted as a device tree overlay blob. + +Applying the overlay the devices are instantiated and the cape is +ready to be used. + +For instance if the part-number is BB-BONE-SERL-03 and the version is 00A1 +the firmware file requested will be BB-BONE-SERL-03-00A1-00A1.dtbo +It will be located by the in-kernel firmware +loader in the usual place, i.e. /lib/firmware/`uname -r`, /lib/firmware etc. + +The driver supports the following parameters (either as part of the kernel +command line or supplied at module insertion time). + +disable_partno: A comma delimited list of PART-NUMBER[:REV] of + disabled capes. +enable_partno: A comma delimited list of PART-NUMBER[:REV[:PRIO]] of + enabled capes. +boot_scan_period: The boot scan period in ms. When the cape manager is built-in + the kernel image, the firmware loader cannot find the files + before the rootfs is mounted. This parameter controls the + period with which the boot state is checked in that case. + +There's a sysfs control interface which is defined at the ABI documentation +area. + +Theory of operation: +-------------------- + +On driver probe the I2C EEPROM of the baseboard is read and information about +the current baseboard is retrieved. This information includes the mapping from +baseboard board name to DT friendly compatible string. I.e. the "A335BONE" board +name from EEPROM is mapped to the "ti,beaglebone" compatible string which should +be present in the dtbo to be loaded. + +Afterwards the EEPROMs declared in each slot are probed, and the EEPROMs found +are decoded keeping track the cape part-number and version data. + +Using the part-number and version a firmware file is requested (the firmware +file requested is -.dtbo). + +The dtbo is unflattend and the resulting device tree is matched against a +compatible baseboard, and in case of multiple parallel loading capes the +priorities defined are honored. That means that when there are multiple capes +being loaded in parallel the ones with the lowest priority number are loaded +first. + +Applying the device tree overlay makes the cape operational, as if it was part +of the kernel's booting device tree. diff -Naur --no-dereference a/Documentation/printk-formats.txt b/Documentation/printk-formats.txt --- a/Documentation/printk-formats.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/printk-formats.txt 2016-05-11 13:31:53.189225170 -0400 @@ -309,10 +309,40 @@ Passed by reference. +Device tree nodes: + + %pO[fnpPcCFr] + + For printing device tree nodes. The optional arguments are: + f device node full_name + n device node name + p device node phandle + P device node path spec (name + @unit) + F device node flags + c major compatible string + C full compatible string + r node reference count + Without any arguments prints full_name (same as %pOf) + The separator when using multiple arguments is '|' + + Examples: + + %pO /foo/bar@0 - Node full name + %pOf /foo/bar@0 - Same as above + %pOfp /foo/bar@0|10 - Node full name + phandle + %pOfcF /foo/bar@0|foo,device|--P- - Node full name + + major compatible string + + node flags + D - dynamic + d - detached + P - Populated + B - Populated bus + + Passed by reference + If you add other %p extensions, please extend lib/test_printf.c with one or more test cases, if at all feasible. - Thank you for your cooperation and attention. diff -Naur --no-dereference a/Documentation/sysrq.txt b/Documentation/sysrq.txt --- a/Documentation/sysrq.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/sysrq.txt 2016-05-11 13:31:53.189225170 -0400 @@ -59,10 +59,17 @@ On other - If you know of the key combos for other architectures, please let me know so I can add them to this section. -On all - write a character to /proc/sysrq-trigger. e.g.: - +On all - write a character to /proc/sysrq-trigger, e.g.: echo t > /proc/sysrq-trigger +On all - Enable network SysRq by writing a cookie to icmp_echo_sysrq, e.g. + echo 0x01020304 >/proc/sys/net/ipv4/icmp_echo_sysrq + Send an ICMP echo request with this pattern plus the particular + SysRq command key. Example: + # ping -c1 -s57 -p0102030468 + will trigger the SysRq-H (help) command. + + * What are the 'command' keys? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 'b' - Will immediately reboot the system without syncing or unmounting diff -Naur --no-dereference a/Documentation/trace/histograms.txt b/Documentation/trace/histograms.txt --- a/Documentation/trace/histograms.txt 1969-12-31 19:00:00.000000000 -0500 +++ b/Documentation/trace/histograms.txt 2016-05-11 13:31:53.189225170 -0400 @@ -0,0 +1,186 @@ + Using the Linux Kernel Latency Histograms + + +This document gives a short explanation how to enable, configure and use +latency histograms. Latency histograms are primarily relevant in the +context of real-time enabled kernels (CONFIG_PREEMPT/CONFIG_PREEMPT_RT) +and are used in the quality management of the Linux real-time +capabilities. + + +* Purpose of latency histograms + +A latency histogram continuously accumulates the frequencies of latency +data. There are two types of histograms +- potential sources of latencies +- effective latencies + + +* Potential sources of latencies + +Potential sources of latencies are code segments where interrupts, +preemption or both are disabled (aka critical sections). To create +histograms of potential sources of latency, the kernel stores the time +stamp at the start of a critical section, determines the time elapsed +when the end of the section is reached, and increments the frequency +counter of that latency value - irrespective of whether any concurrently +running process is affected by latency or not. +- Configuration items (in the Kernel hacking/Tracers submenu) + CONFIG_INTERRUPT_OFF_LATENCY + CONFIG_PREEMPT_OFF_LATENCY + + +* Effective latencies + +Effective latencies are actually occuring during wakeup of a process. To +determine effective latencies, the kernel stores the time stamp when a +process is scheduled to be woken up, and determines the duration of the +wakeup time shortly before control is passed over to this process. Note +that the apparent latency in user space may be somewhat longer, since the +process may be interrupted after control is passed over to it but before +the execution in user space takes place. Simply measuring the interval +between enqueuing and wakeup may also not appropriate in cases when a +process is scheduled as a result of a timer expiration. The timer may have +missed its deadline, e.g. due to disabled interrupts, but this latency +would not be registered. Therefore, the offsets of missed timers are +recorded in a separate histogram. If both wakeup latency and missed timer +offsets are configured and enabled, a third histogram may be enabled that +records the overall latency as a sum of the timer latency, if any, and the +wakeup latency. This histogram is called "timerandwakeup". +- Configuration items (in the Kernel hacking/Tracers submenu) + CONFIG_WAKEUP_LATENCY + CONFIG_MISSED_TIMER_OFSETS + + +* Usage + +The interface to the administration of the latency histograms is located +in the debugfs file system. To mount it, either enter + +mount -t sysfs nodev /sys +mount -t debugfs nodev /sys/kernel/debug + +from shell command line level, or add + +nodev /sys sysfs defaults 0 0 +nodev /sys/kernel/debug debugfs defaults 0 0 + +to the file /etc/fstab. All latency histogram related files are then +available in the directory /sys/kernel/debug/tracing/latency_hist. A +particular histogram type is enabled by writing non-zero to the related +variable in the /sys/kernel/debug/tracing/latency_hist/enable directory. +Select "preemptirqsoff" for the histograms of potential sources of +latencies and "wakeup" for histograms of effective latencies etc. The +histogram data - one per CPU - are available in the files + +/sys/kernel/debug/tracing/latency_hist/preemptoff/CPUx +/sys/kernel/debug/tracing/latency_hist/irqsoff/CPUx +/sys/kernel/debug/tracing/latency_hist/preemptirqsoff/CPUx +/sys/kernel/debug/tracing/latency_hist/wakeup/CPUx +/sys/kernel/debug/tracing/latency_hist/wakeup/sharedprio/CPUx +/sys/kernel/debug/tracing/latency_hist/missed_timer_offsets/CPUx +/sys/kernel/debug/tracing/latency_hist/timerandwakeup/CPUx + +The histograms are reset by writing non-zero to the file "reset" in a +particular latency directory. To reset all latency data, use + +#!/bin/sh + +TRACINGDIR=/sys/kernel/debug/tracing +HISTDIR=$TRACINGDIR/latency_hist + +if test -d $HISTDIR +then + cd $HISTDIR + for i in `find . | grep /reset$` + do + echo 1 >$i + done +fi + + +* Data format + +Latency data are stored with a resolution of one microsecond. The +maximum latency is 10,240 microseconds. The data are only valid, if the +overflow register is empty. Every output line contains the latency in +microseconds in the first row and the number of samples in the second +row. To display only lines with a positive latency count, use, for +example, + +grep -v " 0$" /sys/kernel/debug/tracing/latency_hist/preemptoff/CPU0 + +#Minimum latency: 0 microseconds. +#Average latency: 0 microseconds. +#Maximum latency: 25 microseconds. +#Total samples: 3104770694 +#There are 0 samples greater or equal than 10240 microseconds +#usecs samples + 0 2984486876 + 1 49843506 + 2 58219047 + 3 5348126 + 4 2187960 + 5 3388262 + 6 959289 + 7 208294 + 8 40420 + 9 4485 + 10 14918 + 11 18340 + 12 25052 + 13 19455 + 14 5602 + 15 969 + 16 47 + 17 18 + 18 14 + 19 1 + 20 3 + 21 2 + 22 5 + 23 2 + 25 1 + + +* Wakeup latency of a selected process + +To only collect wakeup latency data of a particular process, write the +PID of the requested process to + +/sys/kernel/debug/tracing/latency_hist/wakeup/pid + +PIDs are not considered, if this variable is set to 0. + + +* Details of the process with the highest wakeup latency so far + +Selected data of the process that suffered from the highest wakeup +latency that occurred in a particular CPU are available in the file + +/sys/kernel/debug/tracing/latency_hist/wakeup/max_latency-CPUx. + +In addition, other relevant system data at the time when the +latency occurred are given. + +The format of the data is (all in one line): + () \ +<- + +The value of is only relevant in the combined timer +and wakeup latency recording. In the wakeup recording, it is +always 0, in the missed_timer_offsets recording, it is the same +as . + +When retrospectively searching for the origin of a latency and +tracing was not enabled, it may be helpful to know the name and +some basic data of the task that (finally) was switching to the +late real-tlme task. In addition to the victim's data, also the +data of the possible culprit are therefore displayed after the +"<-" symbol. + +Finally, the timestamp of the time when the latency occurred +in . after the most recent system boot +is provided. + +These data are also reset when the wakeup histogram is reset. diff -Naur --no-dereference a/Documentation/usb/chipidea.txt b/Documentation/usb/chipidea.txt --- a/Documentation/usb/chipidea.txt 2016-05-04 17:50:15.000000000 -0400 +++ b/Documentation/usb/chipidea.txt 2016-05-11 13:31:53.189225170 -0400 @@ -5,7 +5,7 @@ 1.1 How to enable OTG FSM in menuconfig --------------------------------------- -Select CONFIG_USB_OTG_FSM, rebuild kernel Image and modules. +Select CONFIG_USB_OTG, rebuild kernel Image and modules. If you want to check some internal variables for otg fsm, select CONFIG_USB_CHIPIDEA_DEBUG, there are 2 files which can show otg fsm variables and some controller registers value: diff -Naur --no-dereference a/drivers/acpi/acpica/acglobal.h b/drivers/acpi/acpica/acglobal.h --- a/drivers/acpi/acpica/acglobal.h 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/acpi/acpica/acglobal.h 2016-05-11 13:31:53.197225234 -0400 @@ -116,7 +116,7 @@ * interrupt level */ ACPI_GLOBAL(acpi_spinlock, acpi_gbl_gpe_lock); /* For GPE data structs and registers */ -ACPI_GLOBAL(acpi_spinlock, acpi_gbl_hardware_lock); /* For ACPI H/W except GPE registers */ +ACPI_GLOBAL(acpi_raw_spinlock, acpi_gbl_hardware_lock); /* For ACPI H/W except GPE registers */ ACPI_GLOBAL(acpi_spinlock, acpi_gbl_reference_count_lock); /* Mutex for _OSI support */ diff -Naur --no-dereference a/drivers/acpi/acpica/hwregs.c b/drivers/acpi/acpica/hwregs.c --- a/drivers/acpi/acpica/hwregs.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/acpi/acpica/hwregs.c 2016-05-11 13:31:53.197225234 -0400 @@ -269,14 +269,14 @@ ACPI_BITMASK_ALL_FIXED_STATUS, ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address))); - lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); + raw_spin_lock_irqsave(acpi_gbl_hardware_lock, lock_flags); /* Clear the fixed events in PM1 A/B */ status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS, ACPI_BITMASK_ALL_FIXED_STATUS); - acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); + raw_spin_unlock_irqrestore(acpi_gbl_hardware_lock, lock_flags); if (ACPI_FAILURE(status)) { goto exit; diff -Naur --no-dereference a/drivers/acpi/acpica/hwxface.c b/drivers/acpi/acpica/hwxface.c --- a/drivers/acpi/acpica/hwxface.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/acpi/acpica/hwxface.c 2016-05-11 13:31:53.197225234 -0400 @@ -374,7 +374,7 @@ return_ACPI_STATUS(AE_BAD_PARAMETER); } - lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); + raw_spin_lock_irqsave(acpi_gbl_hardware_lock, lock_flags); /* * At this point, we know that the parent register is one of the @@ -435,7 +435,7 @@ unlock_and_exit: - acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); + raw_spin_unlock_irqrestore(acpi_gbl_hardware_lock, lock_flags); return_ACPI_STATUS(status); } diff -Naur --no-dereference a/drivers/acpi/acpica/utmutex.c b/drivers/acpi/acpica/utmutex.c --- a/drivers/acpi/acpica/utmutex.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/acpi/acpica/utmutex.c 2016-05-11 13:31:53.197225234 -0400 @@ -88,7 +88,7 @@ return_ACPI_STATUS (status); } - status = acpi_os_create_lock (&acpi_gbl_hardware_lock); + status = acpi_os_create_raw_lock (&acpi_gbl_hardware_lock); if (ACPI_FAILURE (status)) { return_ACPI_STATUS (status); } @@ -156,7 +156,7 @@ /* Delete the spinlocks */ acpi_os_delete_lock(acpi_gbl_gpe_lock); - acpi_os_delete_lock(acpi_gbl_hardware_lock); + acpi_os_delete_raw_lock(acpi_gbl_hardware_lock); acpi_os_delete_lock(acpi_gbl_reference_count_lock); /* Delete the reader/writer lock */ diff -Naur --no-dereference a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c --- a/drivers/ata/libata-sff.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/ata/libata-sff.c 2016-05-11 13:31:53.197225234 -0400 @@ -678,9 +678,9 @@ unsigned long flags; unsigned int consumed; - local_irq_save(flags); + local_irq_save_nort(flags); consumed = ata_sff_data_xfer32(dev, buf, buflen, rw); - local_irq_restore(flags); + local_irq_restore_nort(flags); return consumed; } @@ -719,7 +719,7 @@ unsigned long flags; /* FIXME: use a bounce buffer */ - local_irq_save(flags); + local_irq_save_nort(flags); buf = kmap_atomic(page); /* do the actual data transfer */ @@ -727,7 +727,7 @@ do_write); kunmap_atomic(buf); - local_irq_restore(flags); + local_irq_restore_nort(flags); } else { buf = page_address(page); ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, @@ -864,7 +864,7 @@ unsigned long flags; /* FIXME: use bounce buffer */ - local_irq_save(flags); + local_irq_save_nort(flags); buf = kmap_atomic(page); /* do the actual data transfer */ @@ -872,7 +872,7 @@ count, rw); kunmap_atomic(buf); - local_irq_restore(flags); + local_irq_restore_nort(flags); } else { buf = page_address(page); consumed = ap->ops->sff_data_xfer(dev, buf + offset, diff -Naur --no-dereference a/drivers/base/power/opp/core.c b/drivers/base/power/opp/core.c --- a/drivers/base/power/opp/core.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/power/opp/core.c 2016-05-11 13:31:53.197225234 -0400 @@ -13,50 +13,52 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include #include #include #include +#include #include "opp.h" /* - * The root of the list of all devices. All device_opp structures branch off - * from here, with each device_opp containing the list of opp it supports in + * The root of the list of all opp-tables. All opp_table structures branch off + * from here, with each opp_table containing the list of opps it supports in * various states of availability. */ -static LIST_HEAD(dev_opp_list); +static LIST_HEAD(opp_tables); /* Lock to allow exclusive modification to the device and opp lists */ -DEFINE_MUTEX(dev_opp_list_lock); +DEFINE_MUTEX(opp_table_lock); #define opp_rcu_lockdep_assert() \ do { \ RCU_LOCKDEP_WARN(!rcu_read_lock_held() && \ - !lockdep_is_held(&dev_opp_list_lock), \ - "Missing rcu_read_lock() or " \ - "dev_opp_list_lock protection"); \ + !lockdep_is_held(&opp_table_lock), \ + "Missing rcu_read_lock() or " \ + "opp_table_lock protection"); \ } while (0) -static struct device_list_opp *_find_list_dev(const struct device *dev, - struct device_opp *dev_opp) +static struct opp_device *_find_opp_dev(const struct device *dev, + struct opp_table *opp_table) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; - list_for_each_entry(list_dev, &dev_opp->dev_list, node) - if (list_dev->dev == dev) - return list_dev; + list_for_each_entry(opp_dev, &opp_table->dev_list, node) + if (opp_dev->dev == dev) + return opp_dev; return NULL; } -static struct device_opp *_managed_opp(const struct device_node *np) +static struct opp_table *_managed_opp(const struct device_node *np) { - struct device_opp *dev_opp; + struct opp_table *opp_table; - list_for_each_entry_rcu(dev_opp, &dev_opp_list, node) { - if (dev_opp->np == np) { + list_for_each_entry_rcu(opp_table, &opp_tables, node) { + if (opp_table->np == np) { /* * Multiple devices can point to the same OPP table and * so will have same node-pointer, np. @@ -64,7 +66,7 @@ * But the OPPs will be considered as shared only if the * OPP table contains a "opp-shared" property. */ - return dev_opp->shared_opp ? dev_opp : NULL; + return opp_table->shared_opp ? opp_table : NULL; } } @@ -72,24 +74,24 @@ } /** - * _find_device_opp() - find device_opp struct using device pointer - * @dev: device pointer used to lookup device OPPs + * _find_opp_table() - find opp_table struct using device pointer + * @dev: device pointer used to lookup OPP table * - * Search list of device OPPs for one containing matching device. Does a RCU - * reader operation to grab the pointer needed. + * Search OPP table for one containing matching device. Does a RCU reader + * operation to grab the pointer needed. * - * Return: pointer to 'struct device_opp' if found, otherwise -ENODEV or + * Return: pointer to 'struct opp_table' if found, otherwise -ENODEV or * -EINVAL based on type of error. * * Locking: For readers, this function must be called under rcu_read_lock(). - * device_opp is a RCU protected pointer, which means that device_opp is valid + * opp_table is a RCU protected pointer, which means that opp_table is valid * as long as we are under RCU lock. * - * For Writers, this function must be called with dev_opp_list_lock held. + * For Writers, this function must be called with opp_table_lock held. */ -struct device_opp *_find_device_opp(struct device *dev) +struct opp_table *_find_opp_table(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; opp_rcu_lockdep_assert(); @@ -98,9 +100,9 @@ return ERR_PTR(-EINVAL); } - list_for_each_entry_rcu(dev_opp, &dev_opp_list, node) - if (_find_list_dev(dev, dev_opp)) - return dev_opp; + list_for_each_entry_rcu(opp_table, &opp_tables, node) + if (_find_opp_dev(dev, opp_table)) + return opp_table; return ERR_PTR(-ENODEV); } @@ -213,16 +215,16 @@ */ unsigned long dev_pm_opp_get_max_clock_latency(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; unsigned long clock_latency_ns; rcu_read_lock(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) clock_latency_ns = 0; else - clock_latency_ns = dev_opp->clock_latency_ns_max; + clock_latency_ns = opp_table->clock_latency_ns_max; rcu_read_unlock(); return clock_latency_ns; @@ -230,6 +232,82 @@ EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_clock_latency); /** + * dev_pm_opp_get_max_volt_latency() - Get max voltage latency in nanoseconds + * @dev: device for which we do this operation + * + * Return: This function returns the max voltage latency in nanoseconds. + * + * Locking: This function takes rcu_read_lock(). + */ +unsigned long dev_pm_opp_get_max_volt_latency(struct device *dev) +{ + struct opp_table *opp_table; + struct dev_pm_opp *opp; + struct regulator *reg; + unsigned long latency_ns = 0; + unsigned long min_uV = ~0, max_uV = 0; + int ret; + + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + rcu_read_unlock(); + return 0; + } + + reg = opp_table->regulator; + if (IS_ERR(reg)) { + /* Regulator may not be required for device */ + if (reg) + dev_err(dev, "%s: Invalid regulator (%ld)\n", __func__, + PTR_ERR(reg)); + rcu_read_unlock(); + return 0; + } + + list_for_each_entry_rcu(opp, &opp_table->opp_list, node) { + if (!opp->available) + continue; + + if (opp->u_volt_min < min_uV) + min_uV = opp->u_volt_min; + if (opp->u_volt_max > max_uV) + max_uV = opp->u_volt_max; + } + + rcu_read_unlock(); + + /* + * The caller needs to ensure that opp_table (and hence the regulator) + * isn't freed, while we are executing this routine. + */ + ret = regulator_set_voltage_time(reg, min_uV, max_uV); + if (ret > 0) + latency_ns = ret * 1000; + + return latency_ns; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_volt_latency); + +/** + * dev_pm_opp_get_max_transition_latency() - Get max transition latency in + * nanoseconds + * @dev: device for which we do this operation + * + * Return: This function returns the max transition latency, in nanoseconds, to + * switch from one OPP to other. + * + * Locking: This function takes rcu_read_lock(). + */ +unsigned long dev_pm_opp_get_max_transition_latency(struct device *dev) +{ + return dev_pm_opp_get_max_volt_latency(dev) + + dev_pm_opp_get_max_clock_latency(dev); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_get_max_transition_latency); + +/** * dev_pm_opp_get_suspend_opp() - Get suspend opp * @dev: device for which we do this operation * @@ -244,21 +322,21 @@ */ struct dev_pm_opp *dev_pm_opp_get_suspend_opp(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; opp_rcu_lockdep_assert(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp) || !dev_opp->suspend_opp || - !dev_opp->suspend_opp->available) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table) || !opp_table->suspend_opp || + !opp_table->suspend_opp->available) return NULL; - return dev_opp->suspend_opp; + return opp_table->suspend_opp; } EXPORT_SYMBOL_GPL(dev_pm_opp_get_suspend_opp); /** - * dev_pm_opp_get_opp_count() - Get number of opps available in the opp list + * dev_pm_opp_get_opp_count() - Get number of opps available in the opp table * @dev: device for which we do this operation * * Return: This function returns the number of available opps if there are any, @@ -268,21 +346,21 @@ */ int dev_pm_opp_get_opp_count(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp; int count = 0; rcu_read_lock(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - count = PTR_ERR(dev_opp); - dev_err(dev, "%s: device OPP not found (%d)\n", + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + count = PTR_ERR(opp_table); + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, count); goto out_unlock; } - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available) count++; } @@ -299,7 +377,7 @@ * @freq: frequency to search for * @available: true/false - match for available opp * - * Return: Searches for exact match in the opp list and returns pointer to the + * Return: Searches for exact match in the opp table and returns pointer to the * matching opp if found, else returns ERR_PTR in case of error and should * be handled using IS_ERR. Error return values can be: * EINVAL: for bad pointer @@ -323,19 +401,20 @@ unsigned long freq, bool available) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - int r = PTR_ERR(dev_opp); - dev_err(dev, "%s: device OPP not found (%d)\n", __func__, r); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int r = PTR_ERR(opp_table); + + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, r); return ERR_PTR(r); } - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available == available && temp_opp->rate == freq) { opp = temp_opp; @@ -371,7 +450,7 @@ struct dev_pm_opp *dev_pm_opp_find_freq_ceil(struct device *dev, unsigned long *freq) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); @@ -381,11 +460,11 @@ return ERR_PTR(-EINVAL); } - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available && temp_opp->rate >= *freq) { opp = temp_opp; *freq = opp->rate; @@ -421,7 +500,7 @@ struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); opp_rcu_lockdep_assert(); @@ -431,11 +510,11 @@ return ERR_PTR(-EINVAL); } - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); - list_for_each_entry_rcu(temp_opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(temp_opp, &opp_table->opp_list, node) { if (temp_opp->available) { /* go to the next node, before choosing prev */ if (temp_opp->rate > *freq) @@ -451,116 +530,343 @@ } EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_floor); -/* List-dev Helpers */ -static void _kfree_list_dev_rcu(struct rcu_head *head) +/* + * The caller needs to ensure that opp_table (and hence the clk) isn't freed, + * while clk returned here is used. + */ +static struct clk *_get_opp_clk(struct device *dev) +{ + struct opp_table *opp_table; + struct clk *clk; + + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp doesn't exist\n", __func__); + clk = ERR_CAST(opp_table); + goto unlock; + } + + clk = opp_table->clk; + if (IS_ERR(clk)) + dev_err(dev, "%s: No clock available for the device\n", + __func__); + +unlock: + rcu_read_unlock(); + return clk; +} + +static int _set_opp_voltage(struct device *dev, struct regulator *reg, + unsigned long u_volt, unsigned long u_volt_min, + unsigned long u_volt_max) +{ + int ret; + + /* Regulator not available for device */ + if (IS_ERR(reg)) { + dev_dbg(dev, "%s: regulator not available: %ld\n", __func__, + PTR_ERR(reg)); + return 0; + } + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, u_volt_min, + u_volt, u_volt_max); + + ret = regulator_set_voltage_triplet(reg, u_volt_min, u_volt, + u_volt_max); + if (ret) + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, u_volt_min, u_volt, u_volt_max, ret); + + return ret; +} + +/** + * dev_pm_opp_set_rate() - Configure new OPP based on frequency + * @dev: device for which we do this operation + * @target_freq: frequency to achieve + * + * This configures the power-supplies and clock source to the levels specified + * by the OPP corresponding to the target_freq. + * + * Locking: This function takes rcu_read_lock(). + */ +int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq) +{ + struct opp_table *opp_table; + struct dev_pm_opp *old_opp, *opp; + struct regulator *reg; + struct clk *clk; + unsigned long freq, old_freq; + unsigned long u_volt, u_volt_min, u_volt_max; + unsigned long ou_volt, ou_volt_min, ou_volt_max; + int ret; + + if (unlikely(!target_freq)) { + dev_err(dev, "%s: Invalid target frequency %lu\n", __func__, + target_freq); + return -EINVAL; + } + + clk = _get_opp_clk(dev); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + freq = clk_round_rate(clk, target_freq); + if ((long)freq <= 0) + freq = target_freq; + + old_freq = clk_get_rate(clk); + + /* Return early if nothing to do */ + if (old_freq == freq) { + dev_dbg(dev, "%s: old/new frequencies (%lu Hz) are same, nothing to do\n", + __func__, freq); + return 0; + } + + rcu_read_lock(); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp doesn't exist\n", __func__); + rcu_read_unlock(); + return PTR_ERR(opp_table); + } + + old_opp = dev_pm_opp_find_freq_ceil(dev, &old_freq); + if (!IS_ERR(old_opp)) { + ou_volt = old_opp->u_volt; + ou_volt_min = old_opp->u_volt_min; + ou_volt_max = old_opp->u_volt_max; + } else { + dev_err(dev, "%s: failed to find current OPP for freq %lu (%ld)\n", + __func__, old_freq, PTR_ERR(old_opp)); + } + + opp = dev_pm_opp_find_freq_ceil(dev, &freq); + if (IS_ERR(opp)) { + ret = PTR_ERR(opp); + dev_err(dev, "%s: failed to find OPP for freq %lu (%d)\n", + __func__, freq, ret); + rcu_read_unlock(); + return ret; + } + + u_volt = opp->u_volt; + u_volt_min = opp->u_volt_min; + u_volt_max = opp->u_volt_max; + + reg = opp_table->regulator; + + rcu_read_unlock(); + + /* Scaling up? Scale voltage before frequency */ + if (freq > old_freq) { + ret = _set_opp_voltage(dev, reg, u_volt, u_volt_min, + u_volt_max); + if (ret) + goto restore_voltage; + } + + /* Change frequency */ + + dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n", + __func__, old_freq, freq); + + ret = clk_set_rate(clk, freq); + if (ret) { + dev_err(dev, "%s: failed to set clock rate: %d\n", __func__, + ret); + goto restore_voltage; + } + + /* Scaling down? Scale voltage after frequency */ + if (freq < old_freq) { + ret = _set_opp_voltage(dev, reg, u_volt, u_volt_min, + u_volt_max); + if (ret) + goto restore_freq; + } + + return 0; + +restore_freq: + if (clk_set_rate(clk, old_freq)) + dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n", + __func__, old_freq); +restore_voltage: + /* This shouldn't harm even if the voltages weren't updated earlier */ + if (!IS_ERR(old_opp)) + _set_opp_voltage(dev, reg, ou_volt, ou_volt_min, ou_volt_max); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_rate); + +/* OPP-dev Helpers */ +static void _kfree_opp_dev_rcu(struct rcu_head *head) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; - list_dev = container_of(head, struct device_list_opp, rcu_head); - kfree_rcu(list_dev, rcu_head); + opp_dev = container_of(head, struct opp_device, rcu_head); + kfree_rcu(opp_dev, rcu_head); } -static void _remove_list_dev(struct device_list_opp *list_dev, - struct device_opp *dev_opp) +static void _remove_opp_dev(struct opp_device *opp_dev, + struct opp_table *opp_table) { - list_del(&list_dev->node); - call_srcu(&dev_opp->srcu_head.srcu, &list_dev->rcu_head, - _kfree_list_dev_rcu); + opp_debug_unregister(opp_dev, opp_table); + list_del(&opp_dev->node); + call_srcu(&opp_table->srcu_head.srcu, &opp_dev->rcu_head, + _kfree_opp_dev_rcu); } -struct device_list_opp *_add_list_dev(const struct device *dev, - struct device_opp *dev_opp) +struct opp_device *_add_opp_dev(const struct device *dev, + struct opp_table *opp_table) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; + int ret; - list_dev = kzalloc(sizeof(*list_dev), GFP_KERNEL); - if (!list_dev) + opp_dev = kzalloc(sizeof(*opp_dev), GFP_KERNEL); + if (!opp_dev) return NULL; - /* Initialize list-dev */ - list_dev->dev = dev; - list_add_rcu(&list_dev->node, &dev_opp->dev_list); + /* Initialize opp-dev */ + opp_dev->dev = dev; + list_add_rcu(&opp_dev->node, &opp_table->dev_list); - return list_dev; + /* Create debugfs entries for the opp_table */ + ret = opp_debug_register(opp_dev, opp_table); + if (ret) + dev_err(dev, "%s: Failed to register opp debugfs (%d)\n", + __func__, ret); + + return opp_dev; } /** - * _add_device_opp() - Find device OPP table or allocate a new one + * _add_opp_table() - Find OPP table or allocate a new one * @dev: device for which we do this operation * * It tries to find an existing table first, if it couldn't find one, it * allocates a new OPP table and returns that. * - * Return: valid device_opp pointer if success, else NULL. + * Return: valid opp_table pointer if success, else NULL. */ -static struct device_opp *_add_device_opp(struct device *dev) +static struct opp_table *_add_opp_table(struct device *dev) { - struct device_opp *dev_opp; - struct device_list_opp *list_dev; + struct opp_table *opp_table; + struct opp_device *opp_dev; + struct device_node *np; + int ret; - /* Check for existing list for 'dev' first */ - dev_opp = _find_device_opp(dev); - if (!IS_ERR(dev_opp)) - return dev_opp; + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (!IS_ERR(opp_table)) + return opp_table; /* - * Allocate a new device OPP table. In the infrequent case where a new + * Allocate a new OPP table. In the infrequent case where a new * device is needed to be added, we pay this penalty. */ - dev_opp = kzalloc(sizeof(*dev_opp), GFP_KERNEL); - if (!dev_opp) + opp_table = kzalloc(sizeof(*opp_table), GFP_KERNEL); + if (!opp_table) return NULL; - INIT_LIST_HEAD(&dev_opp->dev_list); + INIT_LIST_HEAD(&opp_table->dev_list); - list_dev = _add_list_dev(dev, dev_opp); - if (!list_dev) { - kfree(dev_opp); + opp_dev = _add_opp_dev(dev, opp_table); + if (!opp_dev) { + kfree(opp_table); return NULL; } - srcu_init_notifier_head(&dev_opp->srcu_head); - INIT_LIST_HEAD(&dev_opp->opp_list); + /* + * Only required for backward compatibility with v1 bindings, but isn't + * harmful for other cases. And so we do it unconditionally. + */ + np = of_node_get(dev->of_node); + if (np) { + u32 val; + + if (!of_property_read_u32(np, "clock-latency", &val)) + opp_table->clock_latency_ns_max = val; + of_property_read_u32(np, "voltage-tolerance", + &opp_table->voltage_tolerance_v1); + of_node_put(np); + } + + /* Set regulator to a non-NULL error value */ + opp_table->regulator = ERR_PTR(-ENXIO); + + /* Find clk for the device */ + opp_table->clk = clk_get(dev, NULL); + if (IS_ERR(opp_table->clk)) { + ret = PTR_ERR(opp_table->clk); + if (ret != -EPROBE_DEFER) + dev_dbg(dev, "%s: Couldn't find clock: %d\n", __func__, + ret); + } + + srcu_init_notifier_head(&opp_table->srcu_head); + INIT_LIST_HEAD(&opp_table->opp_list); - /* Secure the device list modification */ - list_add_rcu(&dev_opp->node, &dev_opp_list); - return dev_opp; + /* Secure the device table modification */ + list_add_rcu(&opp_table->node, &opp_tables); + return opp_table; } /** - * _kfree_device_rcu() - Free device_opp RCU handler + * _kfree_device_rcu() - Free opp_table RCU handler * @head: RCU head */ static void _kfree_device_rcu(struct rcu_head *head) { - struct device_opp *device_opp = container_of(head, struct device_opp, rcu_head); + struct opp_table *opp_table = container_of(head, struct opp_table, + rcu_head); - kfree_rcu(device_opp, rcu_head); + kfree_rcu(opp_table, rcu_head); } /** - * _remove_device_opp() - Removes a device OPP table - * @dev_opp: device OPP table to be removed. + * _remove_opp_table() - Removes a OPP table + * @opp_table: OPP table to be removed. * - * Removes/frees device OPP table it it doesn't contain any OPPs. + * Removes/frees OPP table if it doesn't contain any OPPs. */ -static void _remove_device_opp(struct device_opp *dev_opp) +static void _remove_opp_table(struct opp_table *opp_table) { - struct device_list_opp *list_dev; + struct opp_device *opp_dev; - if (!list_empty(&dev_opp->opp_list)) + if (!list_empty(&opp_table->opp_list)) return; - list_dev = list_first_entry(&dev_opp->dev_list, struct device_list_opp, - node); + if (opp_table->supported_hw) + return; - _remove_list_dev(list_dev, dev_opp); + if (opp_table->prop_name) + return; + + if (!IS_ERR(opp_table->regulator)) + return; + + /* Release clk */ + if (!IS_ERR(opp_table->clk)) + clk_put(opp_table->clk); + + opp_dev = list_first_entry(&opp_table->dev_list, struct opp_device, + node); + + _remove_opp_dev(opp_dev, opp_table); /* dev_list must be empty now */ - WARN_ON(!list_empty(&dev_opp->dev_list)); + WARN_ON(!list_empty(&opp_table->dev_list)); - list_del_rcu(&dev_opp->node); - call_srcu(&dev_opp->srcu_head.srcu, &dev_opp->rcu_head, + list_del_rcu(&opp_table->node); + call_srcu(&opp_table->srcu_head.srcu, &opp_table->rcu_head, _kfree_device_rcu); } @@ -577,17 +883,17 @@ /** * _opp_remove() - Remove an OPP from a table definition - * @dev_opp: points back to the device_opp struct this opp belongs to + * @opp_table: points back to the opp_table struct this opp belongs to * @opp: pointer to the OPP to remove * @notify: OPP_EVENT_REMOVE notification should be sent or not * - * This function removes an opp definition from the opp list. + * This function removes an opp definition from the opp table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * It is assumed that the caller holds required mutex for an RCU updater * strategy. */ -static void _opp_remove(struct device_opp *dev_opp, +static void _opp_remove(struct opp_table *opp_table, struct dev_pm_opp *opp, bool notify) { /* @@ -595,21 +901,23 @@ * frequency/voltage list. */ if (notify) - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_REMOVE, opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_REMOVE, opp); + opp_debug_remove_one(opp); list_del_rcu(&opp->node); - call_srcu(&dev_opp->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); + call_srcu(&opp_table->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); - _remove_device_opp(dev_opp); + _remove_opp_table(opp_table); } /** - * dev_pm_opp_remove() - Remove an OPP from OPP list + * dev_pm_opp_remove() - Remove an OPP from OPP table * @dev: device for which we do this operation * @freq: OPP to remove with matching 'freq' * - * This function removes an opp from the opp list. + * This function removes an opp from the opp table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -618,17 +926,17 @@ void dev_pm_opp_remove(struct device *dev, unsigned long freq) { struct dev_pm_opp *opp; - struct device_opp *dev_opp; + struct opp_table *opp_table; bool found = false; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) goto unlock; - list_for_each_entry(opp, &dev_opp->opp_list, node) { + list_for_each_entry(opp, &opp_table->opp_list, node) { if (opp->rate == freq) { found = true; break; @@ -641,14 +949,14 @@ goto unlock; } - _opp_remove(dev_opp, opp, true); + _opp_remove(opp_table, opp, true); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); } EXPORT_SYMBOL_GPL(dev_pm_opp_remove); static struct dev_pm_opp *_allocate_opp(struct device *dev, - struct device_opp **dev_opp) + struct opp_table **opp_table) { struct dev_pm_opp *opp; @@ -659,8 +967,8 @@ INIT_LIST_HEAD(&opp->node); - *dev_opp = _add_device_opp(dev); - if (!*dev_opp) { + *opp_table = _add_opp_table(dev); + if (!*opp_table) { kfree(opp); return NULL; } @@ -668,21 +976,38 @@ return opp; } +static bool _opp_supported_by_regulators(struct dev_pm_opp *opp, + struct opp_table *opp_table) +{ + struct regulator *reg = opp_table->regulator; + + if (!IS_ERR(reg) && + !regulator_is_supported_voltage(reg, opp->u_volt_min, + opp->u_volt_max)) { + pr_warn("%s: OPP minuV: %lu maxuV: %lu, not supported by regulator\n", + __func__, opp->u_volt_min, opp->u_volt_max); + return false; + } + + return true; +} + static int _opp_add(struct device *dev, struct dev_pm_opp *new_opp, - struct device_opp *dev_opp) + struct opp_table *opp_table) { struct dev_pm_opp *opp; - struct list_head *head = &dev_opp->opp_list; + struct list_head *head = &opp_table->opp_list; + int ret; /* * Insert new OPP in order of increasing frequency and discard if * already present. * - * Need to use &dev_opp->opp_list in the condition part of the 'for' + * Need to use &opp_table->opp_list in the condition part of the 'for' * loop, don't replace it with head otherwise it will become an infinite * loop. */ - list_for_each_entry_rcu(opp, &dev_opp->opp_list, node) { + list_for_each_entry_rcu(opp, &opp_table->opp_list, node) { if (new_opp->rate > opp->rate) { head = &opp->node; continue; @@ -700,9 +1025,20 @@ 0 : -EEXIST; } - new_opp->dev_opp = dev_opp; + new_opp->opp_table = opp_table; list_add_rcu(&new_opp->node, head); + ret = opp_debug_create_one(new_opp, opp_table); + if (ret) + dev_err(dev, "%s: Failed to register opp to debugfs (%d)\n", + __func__, ret); + + if (!_opp_supported_by_regulators(new_opp, opp_table)) { + new_opp->available = false; + dev_warn(dev, "%s: OPP not supported by regulators (%lu)\n", + __func__, new_opp->rate); + } + return 0; } @@ -713,14 +1049,14 @@ * @u_volt: Voltage in uVolts for this OPP * @dynamic: Dynamically added OPPs. * - * This function adds an opp definition to the opp list and returns status. + * This function adds an opp definition to the opp table and returns status. * The opp is made available by default and it can be controlled using * dev_pm_opp_enable/disable functions and may be removed by dev_pm_opp_remove. * * NOTE: "dynamic" parameter impacts OPPs added by the dev_pm_opp_of_add_table * and freed by dev_pm_opp_of_remove_table. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -736,14 +1072,15 @@ static int _opp_add_v1(struct device *dev, unsigned long freq, long u_volt, bool dynamic) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp; + unsigned long tol; int ret; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - new_opp = _allocate_opp(dev, &dev_opp); + new_opp = _allocate_opp(dev, &opp_table); if (!new_opp) { ret = -ENOMEM; goto unlock; @@ -751,60 +1088,77 @@ /* populate the opp table */ new_opp->rate = freq; + tol = u_volt * opp_table->voltage_tolerance_v1 / 100; new_opp->u_volt = u_volt; + new_opp->u_volt_min = u_volt - tol; + new_opp->u_volt_max = u_volt + tol; new_opp->available = true; new_opp->dynamic = dynamic; - ret = _opp_add(dev, new_opp, dev_opp); + ret = _opp_add(dev, new_opp, opp_table); if (ret) goto free_opp; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); /* * Notify the changes in the availability of the operable * frequency/voltage list. */ - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ADD, new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, OPP_EVENT_ADD, new_opp); return 0; free_opp: - _opp_remove(dev_opp, new_opp, false); + _opp_remove(opp_table, new_opp, false); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } /* TODO: Support multiple regulators */ -static int opp_parse_supplies(struct dev_pm_opp *opp, struct device *dev) +static int opp_parse_supplies(struct dev_pm_opp *opp, struct device *dev, + struct opp_table *opp_table) { u32 microvolt[3] = {0}; u32 val; int count, ret; + struct property *prop = NULL; + char name[NAME_MAX]; - /* Missing property isn't a problem, but an invalid entry is */ - if (!of_find_property(opp->np, "opp-microvolt", NULL)) - return 0; + /* Search for "opp-microvolt-" */ + if (opp_table->prop_name) { + snprintf(name, sizeof(name), "opp-microvolt-%s", + opp_table->prop_name); + prop = of_find_property(opp->np, name, NULL); + } - count = of_property_count_u32_elems(opp->np, "opp-microvolt"); + if (!prop) { + /* Search for "opp-microvolt" */ + sprintf(name, "opp-microvolt"); + prop = of_find_property(opp->np, name, NULL); + + /* Missing property isn't a problem, but an invalid entry is */ + if (!prop) + return 0; + } + + count = of_property_count_u32_elems(opp->np, name); if (count < 0) { - dev_err(dev, "%s: Invalid opp-microvolt property (%d)\n", - __func__, count); + dev_err(dev, "%s: Invalid %s property (%d)\n", + __func__, name, count); return count; } /* There can be one or three elements here */ if (count != 1 && count != 3) { - dev_err(dev, "%s: Invalid number of elements in opp-microvolt property (%d)\n", - __func__, count); + dev_err(dev, "%s: Invalid number of elements in %s property (%d)\n", + __func__, name, count); return -EINVAL; } - ret = of_property_read_u32_array(opp->np, "opp-microvolt", microvolt, - count); + ret = of_property_read_u32_array(opp->np, name, microvolt, count); if (ret) { - dev_err(dev, "%s: error parsing opp-microvolt: %d\n", __func__, - ret); + dev_err(dev, "%s: error parsing %s: %d\n", __func__, name, ret); return -EINVAL; } @@ -818,22 +1172,391 @@ opp->u_volt_max = microvolt[2]; } - if (!of_property_read_u32(opp->np, "opp-microamp", &val)) + /* Search for "opp-microamp-" */ + prop = NULL; + if (opp_table->prop_name) { + snprintf(name, sizeof(name), "opp-microamp-%s", + opp_table->prop_name); + prop = of_find_property(opp->np, name, NULL); + } + + if (!prop) { + /* Search for "opp-microamp" */ + sprintf(name, "opp-microamp"); + prop = of_find_property(opp->np, name, NULL); + } + + if (prop && !of_property_read_u32(opp->np, name, &val)) opp->u_amp = val; return 0; } /** + * dev_pm_opp_set_supported_hw() - Set supported platforms + * @dev: Device for which supported-hw has to be set. + * @versions: Array of hierarchy of versions to match. + * @count: Number of elements in the array. + * + * This is required only for the V2 bindings, and it enables a platform to + * specify the hierarchy of versions it supports. OPP layer will then enable + * OPPs, which are available for those versions, based on its 'opp-supported-hw' + * property. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_supported_hw(struct device *dev, const u32 *versions, + unsigned int count) +{ + struct opp_table *opp_table; + int ret = 0; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + /* Do we already have a version hierarchy associated with opp_table? */ + if (opp_table->supported_hw) { + dev_err(dev, "%s: Already have supported hardware list\n", + __func__); + ret = -EBUSY; + goto err; + } + + opp_table->supported_hw = kmemdup(versions, count * sizeof(*versions), + GFP_KERNEL); + if (!opp_table->supported_hw) { + ret = -ENOMEM; + goto err; + } + + opp_table->supported_hw_count = count; + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_supported_hw); + +/** + * dev_pm_opp_put_supported_hw() - Releases resources blocked for supported hw + * @dev: Device for which supported-hw has to be put. + * + * This is required only for the V2 bindings, and is called for a matching + * dev_pm_opp_set_supported_hw(). Until this is called, the opp_table structure + * will not be freed. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_supported_hw(struct device *dev) +{ + struct opp_table *opp_table; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + if (!opp_table->supported_hw) { + dev_err(dev, "%s: Doesn't have supported hardware list\n", + __func__); + goto unlock; + } + + kfree(opp_table->supported_hw); + opp_table->supported_hw = NULL; + opp_table->supported_hw_count = 0; + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_supported_hw); + +/** + * dev_pm_opp_set_prop_name() - Set prop-extn name + * @dev: Device for which the prop-name has to be set. + * @name: name to postfix to properties. + * + * This is required only for the V2 bindings, and it enables a platform to + * specify the extn to be used for certain property names. The properties to + * which the extension will apply are opp-microvolt and opp-microamp. OPP core + * should postfix the property name with - while looking for them. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_prop_name(struct device *dev, const char *name) +{ + struct opp_table *opp_table; + int ret = 0; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + /* Do we already have a prop-name associated with opp_table? */ + if (opp_table->prop_name) { + dev_err(dev, "%s: Already have prop-name %s\n", __func__, + opp_table->prop_name); + ret = -EBUSY; + goto err; + } + + opp_table->prop_name = kstrdup(name, GFP_KERNEL); + if (!opp_table->prop_name) { + ret = -ENOMEM; + goto err; + } + + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_prop_name); + +/** + * dev_pm_opp_put_prop_name() - Releases resources blocked for prop-name + * @dev: Device for which the prop-name has to be put. + * + * This is required only for the V2 bindings, and is called for a matching + * dev_pm_opp_set_prop_name(). Until this is called, the opp_table structure + * will not be freed. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_prop_name(struct device *dev) +{ + struct opp_table *opp_table; + + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + if (!opp_table->prop_name) { + dev_err(dev, "%s: Doesn't have a prop-name\n", __func__); + goto unlock; + } + + kfree(opp_table->prop_name); + opp_table->prop_name = NULL; + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_prop_name); + +/** + * dev_pm_opp_set_regulator() - Set regulator name for the device + * @dev: Device for which regulator name is being set. + * @name: Name of the regulator. + * + * In order to support OPP switching, OPP layer needs to know the name of the + * device's regulator, as the core would be required to switch voltages as well. + * + * This must be called before any OPPs are initialized for the device. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +int dev_pm_opp_set_regulator(struct device *dev, const char *name) +{ + struct opp_table *opp_table; + struct regulator *reg; + int ret; + + mutex_lock(&opp_table_lock); + + opp_table = _add_opp_table(dev); + if (!opp_table) { + ret = -ENOMEM; + goto unlock; + } + + /* This should be called before OPPs are initialized */ + if (WARN_ON(!list_empty(&opp_table->opp_list))) { + ret = -EBUSY; + goto err; + } + + /* Already have a regulator set */ + if (WARN_ON(!IS_ERR(opp_table->regulator))) { + ret = -EBUSY; + goto err; + } + /* Allocate the regulator */ + reg = regulator_get_optional(dev, name); + if (IS_ERR(reg)) { + ret = PTR_ERR(reg); + if (ret != -EPROBE_DEFER) + dev_err(dev, "%s: no regulator (%s) found: %d\n", + __func__, name, ret); + goto err; + } + + opp_table->regulator = reg; + + mutex_unlock(&opp_table_lock); + return 0; + +err: + _remove_opp_table(opp_table); +unlock: + mutex_unlock(&opp_table_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_regulator); + +/** + * dev_pm_opp_put_regulator() - Releases resources blocked for regulator + * @dev: Device for which regulator was set. + * + * Locking: The internal opp_table and opp structures are RCU protected. + * Hence this function internally uses RCU updater strategy with mutex locks + * to keep the integrity of the internal data structures. Callers should ensure + * that this function is *NOT* called under RCU protection or in contexts where + * mutex cannot be locked. + */ +void dev_pm_opp_put_regulator(struct device *dev) +{ + struct opp_table *opp_table; + + mutex_lock(&opp_table_lock); + + /* Check for existing table for 'dev' first */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "Failed to find opp_table: %ld\n", + PTR_ERR(opp_table)); + goto unlock; + } + + if (IS_ERR(opp_table->regulator)) { + dev_err(dev, "%s: Doesn't have regulator set\n", __func__); + goto unlock; + } + + /* Make sure there are no concurrent readers while updating opp_table */ + WARN_ON(!list_empty(&opp_table->opp_list)); + + regulator_put(opp_table->regulator); + opp_table->regulator = ERR_PTR(-ENXIO); + + /* Try freeing opp_table if this was the last blocking resource */ + _remove_opp_table(opp_table); + +unlock: + mutex_unlock(&opp_table_lock); +} +EXPORT_SYMBOL_GPL(dev_pm_opp_put_regulator); + +static bool _opp_is_supported(struct device *dev, struct opp_table *opp_table, + struct device_node *np) +{ + unsigned int count = opp_table->supported_hw_count; + u32 version; + int ret; + + if (!opp_table->supported_hw) + return true; + + while (count--) { + ret = of_property_read_u32_index(np, "opp-supported-hw", count, + &version); + if (ret) { + dev_warn(dev, "%s: failed to read opp-supported-hw property at index %d: %d\n", + __func__, count, ret); + return false; + } + + /* Both of these are bitwise masks of the versions */ + if (!(version & opp_table->supported_hw[count])) + return false; + } + + return true; +} + +/** * _opp_add_static_v2() - Allocate static OPPs (As per 'v2' DT bindings) * @dev: device for which we do this operation * @np: device node * - * This function adds an opp definition to the opp list and returns status. The + * This function adds an opp definition to the opp table and returns status. The * opp can be controlled using dev_pm_opp_enable/disable functions and may be * removed by dev_pm_opp_remove. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -849,16 +1572,16 @@ */ static int _opp_add_static_v2(struct device *dev, struct device_node *np) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp; u64 rate; u32 val; int ret; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - new_opp = _allocate_opp(dev, &dev_opp); + new_opp = _allocate_opp(dev, &opp_table); if (!new_opp) { ret = -ENOMEM; goto unlock; @@ -870,6 +1593,12 @@ goto free_opp; } + /* Check if the OPP supports hardware's hierarchy of versions or not */ + if (!_opp_is_supported(dev, opp_table, np)) { + dev_dbg(dev, "OPP not supported by hardware: %llu\n", rate); + goto free_opp; + } + /* * Rate is defined as an unsigned long in clk API, and so casting * explicitly to its type. Must be fixed once rate is 64 bit @@ -885,28 +1614,30 @@ if (!of_property_read_u32(np, "clock-latency-ns", &val)) new_opp->clock_latency_ns = val; - ret = opp_parse_supplies(new_opp, dev); + ret = opp_parse_supplies(new_opp, dev, opp_table); if (ret) goto free_opp; - ret = _opp_add(dev, new_opp, dev_opp); + ret = _opp_add(dev, new_opp, opp_table); if (ret) goto free_opp; /* OPP to select on device suspend */ if (of_property_read_bool(np, "opp-suspend")) { - if (dev_opp->suspend_opp) + if (opp_table->suspend_opp) { dev_warn(dev, "%s: Multiple suspend OPPs found (%lu %lu)\n", - __func__, dev_opp->suspend_opp->rate, + __func__, opp_table->suspend_opp->rate, new_opp->rate); - else - dev_opp->suspend_opp = new_opp; + } else { + new_opp->suspend = true; + opp_table->suspend_opp = new_opp; + } } - if (new_opp->clock_latency_ns > dev_opp->clock_latency_ns_max) - dev_opp->clock_latency_ns_max = new_opp->clock_latency_ns; + if (new_opp->clock_latency_ns > opp_table->clock_latency_ns_max) + opp_table->clock_latency_ns_max = new_opp->clock_latency_ns; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); pr_debug("%s: turbo:%d rate:%lu uv:%lu uvmin:%lu uvmax:%lu latency:%lu\n", __func__, new_opp->turbo, new_opp->rate, new_opp->u_volt, @@ -917,13 +1648,13 @@ * Notify the changes in the availability of the operable * frequency/voltage list. */ - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ADD, new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, OPP_EVENT_ADD, new_opp); return 0; free_opp: - _opp_remove(dev_opp, new_opp, false); + _opp_remove(opp_table, new_opp, false); unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } @@ -933,11 +1664,11 @@ * @freq: Frequency in Hz for this OPP * @u_volt: Voltage in uVolts for this OPP * - * This function adds an opp definition to the opp list and returns status. + * This function adds an opp definition to the opp table and returns status. * The opp is made available by default and it can be controlled using * dev_pm_opp_enable/disable functions. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -969,7 +1700,7 @@ * copy operation, returns 0 if no modification was done OR modification was * successful. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function internally uses RCU updater strategy with mutex locks to * keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -978,7 +1709,7 @@ static int _opp_set_availability(struct device *dev, unsigned long freq, bool availability_req) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *new_opp, *tmp_opp, *opp = ERR_PTR(-ENODEV); int r = 0; @@ -987,18 +1718,18 @@ if (!new_opp) return -ENOMEM; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - /* Find the device_opp */ - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - r = PTR_ERR(dev_opp); + /* Find the opp_table */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + r = PTR_ERR(opp_table); dev_warn(dev, "%s: Device OPP not found (%d)\n", __func__, r); goto unlock; } /* Do we have the frequency? */ - list_for_each_entry(tmp_opp, &dev_opp->opp_list, node) { + list_for_each_entry(tmp_opp, &opp_table->opp_list, node) { if (tmp_opp->rate == freq) { opp = tmp_opp; break; @@ -1019,21 +1750,21 @@ new_opp->available = availability_req; list_replace_rcu(&opp->node, &new_opp->node); - mutex_unlock(&dev_opp_list_lock); - call_srcu(&dev_opp->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); + mutex_unlock(&opp_table_lock); + call_srcu(&opp_table->srcu_head.srcu, &opp->rcu_head, _kfree_opp_rcu); /* Notify the change of the OPP availability */ if (availability_req) - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_ENABLE, - new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_ENABLE, new_opp); else - srcu_notifier_call_chain(&dev_opp->srcu_head, OPP_EVENT_DISABLE, - new_opp); + srcu_notifier_call_chain(&opp_table->srcu_head, + OPP_EVENT_DISABLE, new_opp); return 0; unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); kfree(new_opp); return r; } @@ -1047,7 +1778,7 @@ * corresponding error value. It is meant to be used for users an OPP available * after being temporarily made unavailable with dev_pm_opp_disable. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the * integrity of the internal data structures. Callers should ensure that * this function is *NOT* called under RCU protection or in contexts where @@ -1073,7 +1804,7 @@ * control by users to make this OPP not available until the circumstances are * right to make it available again (with a call to dev_pm_opp_enable). * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU and mutex locks to keep the * integrity of the internal data structures. Callers should ensure that * this function is *NOT* called under RCU protection or in contexts where @@ -1091,26 +1822,26 @@ /** * dev_pm_opp_get_notifier() - find notifier_head of the device with opp - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Return: pointer to notifier head if found, otherwise -ENODEV or * -EINVAL based on type of error casted as pointer. value must be checked * with IS_ERR to determine valid pointer or error result. * - * Locking: This function must be called under rcu_read_lock(). dev_opp is a RCU - * protected pointer. The reason for the same is that the opp pointer which is - * returned will remain valid for use with opp_get_{voltage, freq} only while + * Locking: This function must be called under rcu_read_lock(). opp_table is a + * RCU protected pointer. The reason for the same is that the opp pointer which + * is returned will remain valid for use with opp_get_{voltage, freq} only while * under the locked area. The pointer returned must be used prior to unlocking * with rcu_read_unlock() to maintain the integrity of the pointer. */ struct srcu_notifier_head *dev_pm_opp_get_notifier(struct device *dev) { - struct device_opp *dev_opp = _find_device_opp(dev); + struct opp_table *opp_table = _find_opp_table(dev); - if (IS_ERR(dev_opp)) - return ERR_CAST(dev_opp); /* matching type */ + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); /* matching type */ - return &dev_opp->srcu_head; + return &opp_table->srcu_head; } EXPORT_SYMBOL_GPL(dev_pm_opp_get_notifier); @@ -1118,11 +1849,11 @@ /** * dev_pm_opp_of_remove_table() - Free OPP table entries created from static DT * entries - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Free OPPs created using static entries present in DT. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where @@ -1130,38 +1861,38 @@ */ void dev_pm_opp_of_remove_table(struct device *dev) { - struct device_opp *dev_opp; + struct opp_table *opp_table; struct dev_pm_opp *opp, *tmp; - /* Hold our list modification lock here */ - mutex_lock(&dev_opp_list_lock); + /* Hold our table modification lock here */ + mutex_lock(&opp_table_lock); - /* Check for existing list for 'dev' */ - dev_opp = _find_device_opp(dev); - if (IS_ERR(dev_opp)) { - int error = PTR_ERR(dev_opp); + /* Check for existing table for 'dev' */ + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int error = PTR_ERR(opp_table); if (error != -ENODEV) - WARN(1, "%s: dev_opp: %d\n", + WARN(1, "%s: opp_table: %d\n", IS_ERR_OR_NULL(dev) ? "Invalid device" : dev_name(dev), error); goto unlock; } - /* Find if dev_opp manages a single device */ - if (list_is_singular(&dev_opp->dev_list)) { + /* Find if opp_table manages a single device */ + if (list_is_singular(&opp_table->dev_list)) { /* Free static OPPs */ - list_for_each_entry_safe(opp, tmp, &dev_opp->opp_list, node) { + list_for_each_entry_safe(opp, tmp, &opp_table->opp_list, node) { if (!opp->dynamic) - _opp_remove(dev_opp, opp, true); + _opp_remove(opp_table, opp, true); } } else { - _remove_list_dev(_find_list_dev(dev, dev_opp), dev_opp); + _remove_opp_dev(_find_opp_dev(dev, opp_table), opp_table); } unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); } EXPORT_SYMBOL_GPL(dev_pm_opp_of_remove_table); @@ -1182,22 +1913,22 @@ static int _of_add_opp_table_v2(struct device *dev, struct device_node *opp_np) { struct device_node *np; - struct device_opp *dev_opp; + struct opp_table *opp_table; int ret = 0, count = 0; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _managed_opp(opp_np); - if (dev_opp) { + opp_table = _managed_opp(opp_np); + if (opp_table) { /* OPPs are already managed */ - if (!_add_list_dev(dev, dev_opp)) + if (!_add_opp_dev(dev, opp_table)) ret = -ENOMEM; - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); - /* We have opp-list node now, iterate over it and add OPPs */ + /* We have opp-table node now, iterate over it and add OPPs */ for_each_available_child_of_node(opp_np, np) { count++; @@ -1213,19 +1944,19 @@ if (WARN_ON(!count)) return -ENOENT; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(dev); - if (WARN_ON(IS_ERR(dev_opp))) { - ret = PTR_ERR(dev_opp); - mutex_unlock(&dev_opp_list_lock); + opp_table = _find_opp_table(dev); + if (WARN_ON(IS_ERR(opp_table))) { + ret = PTR_ERR(opp_table); + mutex_unlock(&opp_table_lock); goto free_table; } - dev_opp->np = opp_np; - dev_opp->shared_opp = of_property_read_bool(opp_np, "opp-shared"); + opp_table->np = opp_np; + opp_table->shared_opp = of_property_read_bool(opp_np, "opp-shared"); - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return 0; @@ -1254,7 +1985,7 @@ */ nr = prop->length / sizeof(u32); if (nr % 2) { - dev_err(dev, "%s: Invalid OPP list\n", __func__); + dev_err(dev, "%s: Invalid OPP table\n", __func__); return -EINVAL; } @@ -1274,11 +2005,11 @@ /** * dev_pm_opp_of_add_table() - Initialize opp table from device tree - * @dev: device pointer used to lookup device OPPs. + * @dev: device pointer used to lookup OPP table. * * Register the initial OPP table with the OPP library for given device. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Hence this function indirectly uses RCU updater strategy with mutex locks * to keep the integrity of the internal data structures. Callers should ensure * that this function is *NOT* called under RCU protection or in contexts where diff -Naur --no-dereference a/drivers/base/power/opp/cpu.c b/drivers/base/power/opp/cpu.c --- a/drivers/base/power/opp/cpu.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/power/opp/cpu.c 2016-05-11 13:31:53.197225234 -0400 @@ -31,7 +31,7 @@ * @table: Cpufreq table returned back to caller * * Generate a cpufreq table for a provided device- this assumes that the - * opp list is already initialized and ready for usage. + * opp table is already initialized and ready for usage. * * This function allocates required memory for the cpufreq table. It is * expected that the caller does the required maintenance such as freeing @@ -44,7 +44,7 @@ * WARNING: It is important for the callers to ensure refreshing their copy of * the table if any of the mentioned functions have been invoked in the interim. * - * Locking: The internal device_opp and opp structures are RCU protected. + * Locking: The internal opp_table and opp structures are RCU protected. * Since we just use the regular accessor functions to access the internal data * structures, we use RCU read lock inside this function. As a result, users of * this function DONOT need to use explicit locks for invoking. @@ -122,15 +122,15 @@ /* Required only for V1 bindings, as v2 can manage it from DT itself */ int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask) { - struct device_list_opp *list_dev; - struct device_opp *dev_opp; + struct opp_device *opp_dev; + struct opp_table *opp_table; struct device *dev; int cpu, ret = 0; - mutex_lock(&dev_opp_list_lock); + mutex_lock(&opp_table_lock); - dev_opp = _find_device_opp(cpu_dev); - if (IS_ERR(dev_opp)) { + opp_table = _find_opp_table(cpu_dev); + if (IS_ERR(opp_table)) { ret = -EINVAL; goto unlock; } @@ -146,15 +146,15 @@ continue; } - list_dev = _add_list_dev(dev, dev_opp); - if (!list_dev) { - dev_err(dev, "%s: failed to add list-dev for cpu%d device\n", + opp_dev = _add_opp_dev(dev, opp_table); + if (!opp_dev) { + dev_err(dev, "%s: failed to add opp-dev for cpu%d device\n", __func__, cpu); continue; } } unlock: - mutex_unlock(&dev_opp_list_lock); + mutex_unlock(&opp_table_lock); return ret; } @@ -214,7 +214,6 @@ /* * Works only for OPP v2 bindings. * - * cpumask should be already set to mask of cpu_dev->id. * Returns -ENOENT if operating-points-v2 bindings aren't supported. */ int dev_pm_opp_of_get_sharing_cpus(struct device *cpu_dev, cpumask_var_t cpumask) @@ -230,6 +229,8 @@ return -ENOENT; } + cpumask_set_cpu(cpu_dev->id, cpumask); + /* OPPs are shared ? */ if (!of_property_read_bool(np, "opp-shared")) goto put_cpu_node; diff -Naur --no-dereference a/drivers/base/power/opp/debugfs.c b/drivers/base/power/opp/debugfs.c --- a/drivers/base/power/opp/debugfs.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/base/power/opp/debugfs.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,218 @@ +/* + * Generic OPP debugfs interface + * + * Copyright (C) 2015-2016 Viresh Kumar + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include + +#include "opp.h" + +static struct dentry *rootdir; + +static void opp_set_dev_name(const struct device *dev, char *name) +{ + if (dev->parent) + snprintf(name, NAME_MAX, "%s-%s", dev_name(dev->parent), + dev_name(dev)); + else + snprintf(name, NAME_MAX, "%s", dev_name(dev)); +} + +void opp_debug_remove_one(struct dev_pm_opp *opp) +{ + debugfs_remove_recursive(opp->dentry); +} + +int opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table) +{ + struct dentry *pdentry = opp_table->dentry; + struct dentry *d; + char name[25]; /* 20 chars for 64 bit value + 5 (opp:\0) */ + + /* Rate is unique to each OPP, use it to give opp-name */ + snprintf(name, sizeof(name), "opp:%lu", opp->rate); + + /* Create per-opp directory */ + d = debugfs_create_dir(name, pdentry); + if (!d) + return -ENOMEM; + + if (!debugfs_create_bool("available", S_IRUGO, d, &opp->available)) + return -ENOMEM; + + if (!debugfs_create_bool("dynamic", S_IRUGO, d, &opp->dynamic)) + return -ENOMEM; + + if (!debugfs_create_bool("turbo", S_IRUGO, d, &opp->turbo)) + return -ENOMEM; + + if (!debugfs_create_bool("suspend", S_IRUGO, d, &opp->suspend)) + return -ENOMEM; + + if (!debugfs_create_ulong("rate_hz", S_IRUGO, d, &opp->rate)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_target", S_IRUGO, d, &opp->u_volt)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_min", S_IRUGO, d, &opp->u_volt_min)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_volt_max", S_IRUGO, d, &opp->u_volt_max)) + return -ENOMEM; + + if (!debugfs_create_ulong("u_amp", S_IRUGO, d, &opp->u_amp)) + return -ENOMEM; + + if (!debugfs_create_ulong("clock_latency_ns", S_IRUGO, d, + &opp->clock_latency_ns)) + return -ENOMEM; + + opp->dentry = d; + return 0; +} + +static int opp_list_debug_create_dir(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + const struct device *dev = opp_dev->dev; + struct dentry *d; + + opp_set_dev_name(dev, opp_table->dentry_name); + + /* Create device specific directory */ + d = debugfs_create_dir(opp_table->dentry_name, rootdir); + if (!d) { + dev_err(dev, "%s: Failed to create debugfs dir\n", __func__); + return -ENOMEM; + } + + opp_dev->dentry = d; + opp_table->dentry = d; + + return 0; +} + +static int opp_list_debug_create_link(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + const struct device *dev = opp_dev->dev; + char name[NAME_MAX]; + struct dentry *d; + + opp_set_dev_name(opp_dev->dev, name); + + /* Create device specific directory link */ + d = debugfs_create_symlink(name, rootdir, opp_table->dentry_name); + if (!d) { + dev_err(dev, "%s: Failed to create link\n", __func__); + return -ENOMEM; + } + + opp_dev->dentry = d; + + return 0; +} + +/** + * opp_debug_register - add a device opp node to the debugfs 'opp' directory + * @opp_dev: opp-dev pointer for device + * @opp_table: the device-opp being added + * + * Dynamically adds device specific directory in debugfs 'opp' directory. If the + * device-opp is shared with other devices, then links will be created for all + * devices except the first. + * + * Return: 0 on success, otherwise negative error. + */ +int opp_debug_register(struct opp_device *opp_dev, struct opp_table *opp_table) +{ + if (!rootdir) { + pr_debug("%s: Uninitialized rootdir\n", __func__); + return -EINVAL; + } + + if (opp_table->dentry) + return opp_list_debug_create_link(opp_dev, opp_table); + + return opp_list_debug_create_dir(opp_dev, opp_table); +} + +static void opp_migrate_dentry(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + struct opp_device *new_dev; + const struct device *dev; + struct dentry *dentry; + + /* Look for next opp-dev */ + list_for_each_entry(new_dev, &opp_table->dev_list, node) + if (new_dev != opp_dev) + break; + + /* new_dev is guaranteed to be valid here */ + dev = new_dev->dev; + debugfs_remove_recursive(new_dev->dentry); + + opp_set_dev_name(dev, opp_table->dentry_name); + + dentry = debugfs_rename(rootdir, opp_dev->dentry, rootdir, + opp_table->dentry_name); + if (!dentry) { + dev_err(dev, "%s: Failed to rename link from: %s to %s\n", + __func__, dev_name(opp_dev->dev), dev_name(dev)); + return; + } + + new_dev->dentry = dentry; + opp_table->dentry = dentry; +} + +/** + * opp_debug_unregister - remove a device opp node from debugfs opp directory + * @opp_dev: opp-dev pointer for device + * @opp_table: the device-opp being removed + * + * Dynamically removes device specific directory from debugfs 'opp' directory. + */ +void opp_debug_unregister(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ + if (opp_dev->dentry == opp_table->dentry) { + /* Move the real dentry object under another device */ + if (!list_is_singular(&opp_table->dev_list)) { + opp_migrate_dentry(opp_dev, opp_table); + goto out; + } + opp_table->dentry = NULL; + } + + debugfs_remove_recursive(opp_dev->dentry); + +out: + opp_dev->dentry = NULL; +} + +static int __init opp_debug_init(void) +{ + /* Create /sys/kernel/debug/opp directory */ + rootdir = debugfs_create_dir("opp", NULL); + if (!rootdir) { + pr_err("%s: Failed to create root directory\n", __func__); + return -ENOMEM; + } + + return 0; +} +core_initcall(opp_debug_init); diff -Naur --no-dereference a/drivers/base/power/opp/Makefile b/drivers/base/power/opp/Makefile --- a/drivers/base/power/opp/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/power/opp/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -1,2 +1,3 @@ ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG obj-y += core.o cpu.o +obj-$(CONFIG_DEBUG_FS) += debugfs.o diff -Naur --no-dereference a/drivers/base/power/opp/opp.h b/drivers/base/power/opp/opp.h --- a/drivers/base/power/opp/opp.h 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/power/opp/opp.h 2016-05-11 13:31:53.197225234 -0400 @@ -17,17 +17,21 @@ #include #include #include +#include #include #include #include +struct clk; +struct regulator; + /* Lock to allow exclusive modification to the device and opp lists */ -extern struct mutex dev_opp_list_lock; +extern struct mutex opp_table_lock; /* * Internal data structure organization with the OPP layer library is as * follows: - * dev_opp_list (root) + * opp_tables (root) * |- device 1 (represents voltage domain 1) * | |- opp 1 (availability, freq, voltage) * | |- opp 2 .. @@ -36,23 +40,24 @@ * |- device 2 (represents the next voltage domain) * ... * `- device m (represents mth voltage domain) - * device 1, 2.. are represented by dev_opp structure while each opp + * device 1, 2.. are represented by opp_table structure while each opp * is represented by the opp structure. */ /** * struct dev_pm_opp - Generic OPP description structure - * @node: opp list node. The nodes are maintained throughout the lifetime + * @node: opp table node. The nodes are maintained throughout the lifetime * of boot. It is expected only an optimal set of OPPs are * added to the library by the SoC framework. - * RCU usage: opp list is traversed with RCU locks. node + * RCU usage: opp table is traversed with RCU locks. node * modification is possible realtime, hence the modifications - * are protected by the dev_opp_list_lock for integrity. + * are protected by the opp_table_lock for integrity. * IMPORTANT: the opp nodes should be maintained in increasing * order. - * @dynamic: not-created from static DT entries. * @available: true/false - marks if this OPP as available or not + * @dynamic: not-created from static DT entries. * @turbo: true if turbo (boost) OPP + * @suspend: true if suspend OPP * @rate: Frequency in hertz * @u_volt: Target voltage in microvolts corresponding to this OPP * @u_volt_min: Minimum voltage in microvolts corresponding to this OPP @@ -60,9 +65,10 @@ * @u_amp: Maximum current drawn by the device in microamperes * @clock_latency_ns: Latency (in nanoseconds) of switching to this OPP's * frequency from any other OPP's frequency. - * @dev_opp: points back to the device_opp struct this opp belongs to + * @opp_table: points back to the opp_table struct this opp belongs to * @rcu_head: RCU callback head used for deferred freeing * @np: OPP's device node. + * @dentry: debugfs dentry pointer (per opp) * * This structure stores the OPP information for a given device. */ @@ -72,6 +78,7 @@ bool available; bool dynamic; bool turbo; + bool suspend; unsigned long rate; unsigned long u_volt; @@ -80,40 +87,60 @@ unsigned long u_amp; unsigned long clock_latency_ns; - struct device_opp *dev_opp; + struct opp_table *opp_table; struct rcu_head rcu_head; struct device_node *np; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; +#endif }; /** - * struct device_list_opp - devices managed by 'struct device_opp' + * struct opp_device - devices managed by 'struct opp_table' * @node: list node * @dev: device to which the struct object belongs * @rcu_head: RCU callback head used for deferred freeing + * @dentry: debugfs dentry pointer (per device) * - * This is an internal data structure maintaining the list of devices that are - * managed by 'struct device_opp'. + * This is an internal data structure maintaining the devices that are managed + * by 'struct opp_table'. */ -struct device_list_opp { +struct opp_device { struct list_head node; const struct device *dev; struct rcu_head rcu_head; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; +#endif }; /** - * struct device_opp - Device opp structure - * @node: list node - contains the devices with OPPs that + * struct opp_table - Device opp structure + * @node: table node - contains the devices with OPPs that * have been registered. Nodes once added are not modified in this - * list. - * RCU usage: nodes are not modified in the list of device_opp, - * however addition is possible and is secured by dev_opp_list_lock + * table. + * RCU usage: nodes are not modified in the table of opp_table, + * however addition is possible and is secured by opp_table_lock * @srcu_head: notifier head to notify the OPP availability changes. * @rcu_head: RCU callback head used for deferred freeing * @dev_list: list of devices that share these OPPs - * @opp_list: list of opps + * @opp_list: table of opps * @np: struct device_node pointer for opp's DT node. + * @clock_latency_ns_max: Max clock latency in nanoseconds. * @shared_opp: OPP is shared between multiple devices. + * @suspend_opp: Pointer to OPP to be used during device suspend. + * @supported_hw: Array of version number to support. + * @supported_hw_count: Number of elements in supported_hw array. + * @prop_name: A name to postfix to many DT properties, while parsing them. + * @clk: Device's clock handle + * @regulator: Supply regulator + * @dentry: debugfs dentry pointer of the real device directory (not links). + * @dentry_name: Name of the real dentry. + * + * @voltage_tolerance_v1: In percentage, for v1 bindings only. * * This is an internal data structure maintaining the link to opps attached to * a device. This structure is not meant to be shared to users as it is @@ -123,7 +150,7 @@ * need to wait for the grace period of both of them before freeing any * resources. And so we have used kfree_rcu() from within call_srcu() handlers. */ -struct device_opp { +struct opp_table { struct list_head node; struct srcu_notifier_head srcu_head; @@ -133,14 +160,48 @@ struct device_node *np; unsigned long clock_latency_ns_max; + + /* For backward compatibility with v1 bindings */ + unsigned int voltage_tolerance_v1; + bool shared_opp; struct dev_pm_opp *suspend_opp; + + unsigned int *supported_hw; + unsigned int supported_hw_count; + const char *prop_name; + struct clk *clk; + struct regulator *regulator; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dentry; + char dentry_name[NAME_MAX]; +#endif }; /* Routines internal to opp core */ -struct device_opp *_find_device_opp(struct device *dev); -struct device_list_opp *_add_list_dev(const struct device *dev, - struct device_opp *dev_opp); +struct opp_table *_find_opp_table(struct device *dev); +struct opp_device *_add_opp_dev(const struct device *dev, struct opp_table *opp_table); struct device_node *_of_get_opp_desc_node(struct device *dev); +#ifdef CONFIG_DEBUG_FS +void opp_debug_remove_one(struct dev_pm_opp *opp); +int opp_debug_create_one(struct dev_pm_opp *opp, struct opp_table *opp_table); +int opp_debug_register(struct opp_device *opp_dev, struct opp_table *opp_table); +void opp_debug_unregister(struct opp_device *opp_dev, struct opp_table *opp_table); +#else +static inline void opp_debug_remove_one(struct dev_pm_opp *opp) {} + +static inline int opp_debug_create_one(struct dev_pm_opp *opp, + struct opp_table *opp_table) +{ return 0; } +static inline int opp_debug_register(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ return 0; } + +static inline void opp_debug_unregister(struct opp_device *opp_dev, + struct opp_table *opp_table) +{ } +#endif /* DEBUG_FS */ + #endif /* __DRIVER_OPP_H__ */ diff -Naur --no-dereference a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c --- a/drivers/base/power/wakeup.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/power/wakeup.c 2016-05-11 13:31:53.197225234 -0400 @@ -246,6 +246,8 @@ return -EEXIST; } dev->power.wakeup = ws; + if (dev->power.wakeirq) + device_wakeup_attach_irq(dev, dev->power.wakeirq); spin_unlock_irq(&dev->power.lock); return 0; } diff -Naur --no-dereference a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c --- a/drivers/base/regmap/regmap-irq.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/base/regmap/regmap-irq.c 2016-05-11 13:31:53.197225234 -0400 @@ -327,6 +327,7 @@ irq_set_chip_data(virq, data); irq_set_chip(virq, &data->irq_chip); irq_set_nested_thread(virq, 1); + irq_set_parent(virq, data->irq); irq_set_noprobe(virq); return 0; diff -Naur --no-dereference a/drivers/block/loop.c b/drivers/block/loop.c --- a/drivers/block/loop.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/block/loop.c 2016-05-11 13:31:53.197225234 -0400 @@ -712,6 +712,24 @@ return i && S_ISBLK(i->i_mode) && MAJOR(i->i_rdev) == LOOP_MAJOR; } +/* + * for AUFS + * no get/put for file. + */ +struct file *loop_backing_file(struct super_block *sb) +{ + struct file *ret; + struct loop_device *l; + + ret = NULL; + if (MAJOR(sb->s_dev) == LOOP_MAJOR) { + l = sb->s_bdev->bd_disk->private_data; + ret = l->lo_backing_file; + } + return ret; +} +EXPORT_SYMBOL_GPL(loop_backing_file); + /* loop sysfs attributes */ static ssize_t loop_attr_show(struct device *dev, char *page, diff -Naur --no-dereference a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c --- a/drivers/block/zram/zram_drv.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/block/zram/zram_drv.c 2016-05-11 13:31:53.197225234 -0400 @@ -520,6 +520,8 @@ goto out_error; } + zram_meta_init_table_locks(meta, disksize); + return meta; out_error: @@ -568,12 +570,12 @@ unsigned long handle; size_t size; - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); handle = meta->table[index].handle; size = zram_get_obj_size(meta, index); if (!handle || zram_test_flag(meta, index, ZRAM_ZERO)) { - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); clear_page(mem); return 0; } @@ -584,7 +586,7 @@ else ret = zcomp_decompress(zram->comp, cmem, size, mem); zs_unmap_object(meta->mem_pool, handle); - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); /* Should NEVER happen. Return bio error if it does. */ if (unlikely(ret)) { @@ -604,14 +606,14 @@ struct zram_meta *meta = zram->meta; page = bvec->bv_page; - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); if (unlikely(!meta->table[index].handle) || zram_test_flag(meta, index, ZRAM_ZERO)) { - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); handle_zero_page(bvec); return 0; } - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); if (is_partial_io(bvec)) /* Use a temporary buffer to decompress the page */ @@ -689,10 +691,10 @@ if (user_mem) kunmap_atomic(user_mem); /* Free memory associated with this sector now. */ - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); zram_free_page(zram, index); zram_set_flag(meta, index, ZRAM_ZERO); - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); atomic64_inc(&zram->stats.zero_pages); ret = 0; @@ -752,12 +754,12 @@ * Free memory associated with this sector * before overwriting unused sectors. */ - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); zram_free_page(zram, index); meta->table[index].handle = handle; zram_set_obj_size(meta, index, clen); - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); /* Update stats */ atomic64_add(clen, &zram->stats.compr_data_size); @@ -800,9 +802,9 @@ } while (n >= PAGE_SIZE) { - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); zram_free_page(zram, index); - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); atomic64_inc(&zram->stats.notify_free); index++; n -= PAGE_SIZE; @@ -928,9 +930,9 @@ zram = bdev->bd_disk->private_data; meta = zram->meta; - bit_spin_lock(ZRAM_ACCESS, &meta->table[index].value); + zram_lock_table(&meta->table[index]); zram_free_page(zram, index); - bit_spin_unlock(ZRAM_ACCESS, &meta->table[index].value); + zram_unlock_table(&meta->table[index]); atomic64_inc(&zram->stats.notify_free); } diff -Naur --no-dereference a/drivers/block/zram/zram_drv.h b/drivers/block/zram/zram_drv.h --- a/drivers/block/zram/zram_drv.h 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/block/zram/zram_drv.h 2016-05-11 13:31:53.197225234 -0400 @@ -72,6 +72,9 @@ struct zram_table_entry { unsigned long handle; unsigned long value; +#ifdef CONFIG_PREEMPT_RT_BASE + spinlock_t lock; +#endif }; struct zram_stats { @@ -119,4 +122,42 @@ */ bool claim; /* Protected by bdev->bd_mutex */ }; + +#ifndef CONFIG_PREEMPT_RT_BASE +static inline void zram_lock_table(struct zram_table_entry *table) +{ + bit_spin_lock(ZRAM_ACCESS, &table->value); +} + +static inline void zram_unlock_table(struct zram_table_entry *table) +{ + bit_spin_unlock(ZRAM_ACCESS, &table->value); +} + +static inline void zram_meta_init_table_locks(struct zram_meta *meta, u64 disksize) { } +#else /* CONFIG_PREEMPT_RT_BASE */ +static inline void zram_lock_table(struct zram_table_entry *table) +{ + spin_lock(&table->lock); + __set_bit(ZRAM_ACCESS, &table->value); +} + +static inline void zram_unlock_table(struct zram_table_entry *table) +{ + __clear_bit(ZRAM_ACCESS, &table->value); + spin_unlock(&table->lock); +} + +static inline void zram_meta_init_table_locks(struct zram_meta *meta, u64 disksize) +{ + size_t num_pages = disksize >> PAGE_SHIFT; + size_t index; + + for (index = 0; index < num_pages; index++) { + spinlock_t *lock = &meta->table[index].lock; + spin_lock_init(lock); + } +} +#endif /* CONFIG_PREEMPT_RT_BASE */ + #endif diff -Naur --no-dereference a/drivers/char/random.c b/drivers/char/random.c --- a/drivers/char/random.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/char/random.c 2016-05-11 13:31:53.197225234 -0400 @@ -796,8 +796,6 @@ } sample; long delta, delta2, delta3; - preempt_disable(); - sample.jiffies = jiffies; sample.cycles = random_get_entropy(); sample.num = num; @@ -838,7 +836,6 @@ */ credit_entropy_bits(r, min_t(int, fls(delta>>1), 11)); } - preempt_enable(); } void add_input_randomness(unsigned int type, unsigned int code, @@ -891,28 +888,27 @@ return *(ptr + f->reg_idx++); } -void add_interrupt_randomness(int irq, int irq_flags) +void add_interrupt_randomness(int irq, int irq_flags, __u64 ip) { struct entropy_store *r; struct fast_pool *fast_pool = this_cpu_ptr(&irq_randomness); - struct pt_regs *regs = get_irq_regs(); unsigned long now = jiffies; cycles_t cycles = random_get_entropy(); __u32 c_high, j_high; - __u64 ip; unsigned long seed; int credit = 0; if (cycles == 0) - cycles = get_reg(fast_pool, regs); + cycles = get_reg(fast_pool, NULL); c_high = (sizeof(cycles) > 4) ? cycles >> 32 : 0; j_high = (sizeof(now) > 4) ? now >> 32 : 0; fast_pool->pool[0] ^= cycles ^ j_high ^ irq; fast_pool->pool[1] ^= now ^ c_high; - ip = regs ? instruction_pointer(regs) : _RET_IP_; + if (!ip) + ip = _RET_IP_; fast_pool->pool[2] ^= ip; fast_pool->pool[3] ^= (sizeof(ip) > 4) ? ip >> 32 : - get_reg(fast_pool, regs); + get_reg(fast_pool, NULL); fast_mix(fast_pool); add_interrupt_bench(cycles); diff -Naur --no-dereference a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c --- a/drivers/clk/at91/clk-generated.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-generated.c 2016-05-11 13:31:53.197225234 -0400 @@ -15,8 +15,8 @@ #include #include #include -#include -#include +#include +#include #include "pmc.h" @@ -28,8 +28,9 @@ struct clk_generated { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; struct clk_range range; + spinlock_t *lock; u32 id; u32 gckdiv; u8 parent_id; @@ -41,49 +42,52 @@ static int clk_generated_enable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); - struct at91_pmc *pmc = gck->pmc; - u32 tmp; + unsigned long flags; pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", __func__, gck->gckdiv, gck->parent_id); - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (gck->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR) & - ~(AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK); - pmc_write(pmc, AT91_PMC_PCR, tmp | AT91_PMC_PCR_GCKCSS(gck->parent_id) - | AT91_PMC_PCR_CMD - | AT91_PMC_PCR_GCKDIV(gck->gckdiv) - | AT91_PMC_PCR_GCKEN); - pmc_unlock(pmc); + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, AT91_PMC_PCR, + (gck->id & AT91_PMC_PCR_PID_MASK)); + regmap_update_bits(gck->regmap, AT91_PMC_PCR, + AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK | + AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN, + AT91_PMC_PCR_GCKCSS(gck->parent_id) | + AT91_PMC_PCR_CMD | + AT91_PMC_PCR_GCKDIV(gck->gckdiv) | + AT91_PMC_PCR_GCKEN); + spin_unlock_irqrestore(gck->lock, flags); return 0; } static void clk_generated_disable(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); - struct at91_pmc *pmc = gck->pmc; - u32 tmp; + unsigned long flags; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (gck->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR) & ~AT91_PMC_PCR_GCKEN; - pmc_write(pmc, AT91_PMC_PCR, tmp | AT91_PMC_PCR_CMD); - pmc_unlock(pmc); + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, AT91_PMC_PCR, + (gck->id & AT91_PMC_PCR_PID_MASK)); + regmap_update_bits(gck->regmap, AT91_PMC_PCR, + AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN, + AT91_PMC_PCR_CMD); + spin_unlock_irqrestore(gck->lock, flags); } static int clk_generated_is_enabled(struct clk_hw *hw) { struct clk_generated *gck = to_clk_generated(hw); - struct at91_pmc *pmc = gck->pmc; - int ret; + unsigned long flags; + unsigned int status; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (gck->id & AT91_PMC_PCR_PID_MASK)); - ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_GCKEN); - pmc_unlock(pmc); + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, AT91_PMC_PCR, + (gck->id & AT91_PMC_PCR_PID_MASK)); + regmap_read(gck->regmap, AT91_PMC_PCR, &status); + spin_unlock_irqrestore(gck->lock, flags); - return ret; + return status & AT91_PMC_PCR_GCKEN ? 1 : 0; } static unsigned long @@ -214,13 +218,14 @@ */ static void clk_generated_startup(struct clk_generated *gck) { - struct at91_pmc *pmc = gck->pmc; u32 tmp; + unsigned long flags; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (gck->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR); - pmc_unlock(pmc); + spin_lock_irqsave(gck->lock, flags); + regmap_write(gck->regmap, AT91_PMC_PCR, + (gck->id & AT91_PMC_PCR_PID_MASK)); + regmap_read(gck->regmap, AT91_PMC_PCR, &tmp); + spin_unlock_irqrestore(gck->lock, flags); gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK) >> AT91_PMC_PCR_GCKCSS_OFFSET; @@ -229,8 +234,8 @@ } static struct clk * __init -at91_clk_register_generated(struct at91_pmc *pmc, const char *name, - const char **parent_names, u8 num_parents, +at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const char + *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_range *range) { struct clk_generated *gck; @@ -249,7 +254,8 @@ gck->id = id; gck->hw.init = &init; - gck->pmc = pmc; + gck->regmap = regmap; + gck->lock = lock; gck->range = *range; clk = clk_register(NULL, &gck->hw); @@ -261,8 +267,7 @@ return clk; } -void __init of_sama5d2_clk_generated_setup(struct device_node *np, - struct at91_pmc *pmc) +void __init of_sama5d2_clk_generated_setup(struct device_node *np) { int num; u32 id; @@ -272,6 +277,7 @@ const char *parent_names[GENERATED_SOURCE_MAX]; struct device_node *gcknp; struct clk_range range = CLK_RANGE(0, 0); + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > GENERATED_SOURCE_MAX) @@ -283,6 +289,10 @@ if (!num || num > PERIPHERAL_MAX) return; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + for_each_child_of_node(np, gcknp) { if (of_property_read_u32(gcknp, "reg", &id)) continue; @@ -296,11 +306,14 @@ of_at91_get_clk_range(gcknp, "atmel,clk-output-range", &range); - clk = at91_clk_register_generated(pmc, name, parent_names, - num_parents, id, &range); + clk = at91_clk_register_generated(regmap, &pmc_pcr_lock, name, + parent_names, num_parents, + id, &range); if (IS_ERR(clk)) continue; of_clk_add_provider(gcknp, of_clk_src_simple_get, clk); } } +CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated", + of_sama5d2_clk_generated_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c --- a/drivers/clk/at91/clk-h32mx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-h32mx.c 2016-05-11 13:31:53.197225234 -0400 @@ -15,15 +15,9 @@ #include #include #include -#include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -31,7 +25,7 @@ struct clk_sama5d4_h32mx { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; #define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw) @@ -40,8 +34,10 @@ unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); + unsigned int mckr; - if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV) + regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); + if (mckr & AT91_PMC_H32MXDIV) return parent_rate / 2; if (parent_rate > H32MX_MAX_FREQ) @@ -70,18 +66,16 @@ unsigned long parent_rate) { struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw); - struct at91_pmc *pmc = h32mxclk->pmc; - u32 tmp; + u32 mckr = 0; if (parent_rate != rate && (parent_rate / 2) != rate) return -EINVAL; - pmc_lock(pmc); - tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV; if ((parent_rate / 2) == rate) - tmp |= AT91_PMC_H32MXDIV; - pmc_write(pmc, AT91_PMC_MCKR, tmp); - pmc_unlock(pmc); + mckr = AT91_PMC_H32MXDIV; + + regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR, + AT91_PMC_H32MXDIV, mckr); return 0; } @@ -92,14 +86,18 @@ .set_rate = clk_sama5d4_h32mx_set_rate, }; -void __init of_sama5d4_clk_h32mx_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) { struct clk_sama5d4_h32mx *h32mxclk; struct clk_init_data init; const char *parent_name; + struct regmap *regmap; struct clk *clk; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL); if (!h32mxclk) return; @@ -113,7 +111,7 @@ init.flags = CLK_SET_RATE_GATE; h32mxclk->hw.init = &init; - h32mxclk->pmc = pmc; + h32mxclk->regmap = regmap; clk = clk_register(NULL, &h32mxclk->hw); if (!clk) { @@ -123,3 +121,5 @@ of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx", + of_sama5d4_clk_h32mx_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c --- a/drivers/clk/at91/clk-main.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-main.c 2016-05-11 13:31:53.197225234 -0400 @@ -13,13 +13,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -34,18 +29,14 @@ struct clk_main_osc { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; }; #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw) struct clk_main_rc_osc { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; unsigned long frequency; unsigned long accuracy; }; @@ -54,51 +45,47 @@ struct clk_rm9200_main { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw) struct clk_sam9x5_main { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; u8 parent; }; #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw) -static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id) +static inline bool clk_main_osc_ready(struct regmap *regmap) { - struct clk_main_osc *osc = dev_id; + unsigned int status; - wake_up(&osc->wait); - disable_irq_nosync(osc->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & AT91_PMC_MOSCS; } static int clk_main_osc_prepare(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); - struct at91_pmc *pmc = osc->pmc; + struct regmap *regmap = osc->regmap; u32 tmp; - tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; + regmap_read(regmap, AT91_CKGR_MOR, &tmp); + tmp &= ~MOR_KEY_MASK; + if (tmp & AT91_PMC_OSCBYPASS) return 0; if (!(tmp & AT91_PMC_MOSCEN)) { tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY; - pmc_write(pmc, AT91_CKGR_MOR, tmp); + regmap_write(regmap, AT91_CKGR_MOR, tmp); } - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) { - enable_irq(osc->irq); - wait_event(osc->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); - } + while (!clk_main_osc_ready(regmap)) + cpu_relax(); return 0; } @@ -106,9 +93,10 @@ static void clk_main_osc_unprepare(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); - struct at91_pmc *pmc = osc->pmc; - u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); + struct regmap *regmap = osc->regmap; + u32 tmp; + regmap_read(regmap, AT91_CKGR_MOR, &tmp); if (tmp & AT91_PMC_OSCBYPASS) return; @@ -116,20 +104,22 @@ return; tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN); - pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); + regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); } static int clk_main_osc_is_prepared(struct clk_hw *hw) { struct clk_main_osc *osc = to_clk_main_osc(hw); - struct at91_pmc *pmc = osc->pmc; - u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); + struct regmap *regmap = osc->regmap; + u32 tmp, status; + regmap_read(regmap, AT91_CKGR_MOR, &tmp); if (tmp & AT91_PMC_OSCBYPASS) return 1; - return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) && - (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN)); + regmap_read(regmap, AT91_PMC_SR, &status); + + return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN); } static const struct clk_ops main_osc_ops = { @@ -139,18 +129,16 @@ }; static struct clk * __init -at91_clk_register_main_osc(struct at91_pmc *pmc, - unsigned int irq, +at91_clk_register_main_osc(struct regmap *regmap, const char *name, const char *parent_name, bool bypass) { - int ret; struct clk_main_osc *osc; struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !irq || !name || !parent_name) + if (!name || !parent_name) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); @@ -164,85 +152,70 @@ init.flags = CLK_IGNORE_UNUSED; osc->hw.init = &init; - osc->pmc = pmc; - osc->irq = irq; - - init_waitqueue_head(&osc->wait); - irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); - ret = request_irq(osc->irq, clk_main_osc_irq_handler, - IRQF_TRIGGER_HIGH, name, osc); - if (ret) { - kfree(osc); - return ERR_PTR(ret); - } + osc->regmap = regmap; if (bypass) - pmc_write(pmc, AT91_CKGR_MOR, - (pmc_read(pmc, AT91_CKGR_MOR) & - ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) | - AT91_PMC_OSCBYPASS | AT91_PMC_KEY); + regmap_update_bits(regmap, + AT91_CKGR_MOR, MOR_KEY_MASK | + AT91_PMC_MOSCEN, + AT91_PMC_OSCBYPASS | AT91_PMC_KEY); clk = clk_register(NULL, &osc->hw); - if (IS_ERR(clk)) { - free_irq(irq, osc); + if (IS_ERR(clk)) kfree(osc); - } return clk; } -void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) { struct clk *clk; - unsigned int irq; const char *name = np->name; const char *parent_name; + struct regmap *regmap; bool bypass; of_property_read_string(np, "clock-output-names", &name); bypass = of_property_read_bool(np, "atmel,osc-bypass"); parent_name = of_clk_get_parent_name(np, 0); - irq = irq_of_parse_and_map(np, 0); - if (!irq) + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) return; - clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); + clk = at91_clk_register_main_osc(regmap, name, parent_name, bypass); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc", + of_at91rm9200_clk_main_osc_setup); -static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id) +static bool clk_main_rc_osc_ready(struct regmap *regmap) { - struct clk_main_rc_osc *osc = dev_id; + unsigned int status; - wake_up(&osc->wait); - disable_irq_nosync(osc->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & AT91_PMC_MOSCRCS; } static int clk_main_rc_osc_prepare(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); - struct at91_pmc *pmc = osc->pmc; - u32 tmp; + struct regmap *regmap = osc->regmap; + unsigned int mor; - tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; + regmap_read(regmap, AT91_CKGR_MOR, &mor); - if (!(tmp & AT91_PMC_MOSCRCEN)) { - tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY; - pmc_write(pmc, AT91_CKGR_MOR, tmp); - } + if (!(mor & AT91_PMC_MOSCRCEN)) + regmap_update_bits(regmap, AT91_CKGR_MOR, + MOR_KEY_MASK | AT91_PMC_MOSCRCEN, + AT91_PMC_MOSCRCEN | AT91_PMC_KEY); - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) { - enable_irq(osc->irq); - wait_event(osc->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS); - } + while (!clk_main_rc_osc_ready(regmap)) + cpu_relax(); return 0; } @@ -250,23 +223,28 @@ static void clk_main_rc_osc_unprepare(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); - struct at91_pmc *pmc = osc->pmc; - u32 tmp = pmc_read(pmc, AT91_CKGR_MOR); + struct regmap *regmap = osc->regmap; + unsigned int mor; - if (!(tmp & AT91_PMC_MOSCRCEN)) + regmap_read(regmap, AT91_CKGR_MOR, &mor); + + if (!(mor & AT91_PMC_MOSCRCEN)) return; - tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN); - pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY); + regmap_update_bits(regmap, AT91_CKGR_MOR, + MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY); } static int clk_main_rc_osc_is_prepared(struct clk_hw *hw) { struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw); - struct at91_pmc *pmc = osc->pmc; + struct regmap *regmap = osc->regmap; + unsigned int mor, status; + + regmap_read(regmap, AT91_CKGR_MOR, &mor); + regmap_read(regmap, AT91_PMC_SR, &status); - return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) && - (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN)); + return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS); } static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw, @@ -294,17 +272,15 @@ }; static struct clk * __init -at91_clk_register_main_rc_osc(struct at91_pmc *pmc, - unsigned int irq, +at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, u32 frequency, u32 accuracy) { - int ret; struct clk_main_rc_osc *osc; struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !irq || !name || !frequency) + if (!name || !frequency) return ERR_PTR(-EINVAL); osc = kzalloc(sizeof(*osc), GFP_KERNEL); @@ -318,63 +294,53 @@ init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED; osc->hw.init = &init; - osc->pmc = pmc; - osc->irq = irq; + osc->regmap = regmap; osc->frequency = frequency; osc->accuracy = accuracy; - init_waitqueue_head(&osc->wait); - irq_set_status_flags(osc->irq, IRQ_NOAUTOEN); - ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler, - IRQF_TRIGGER_HIGH, name, osc); - if (ret) - return ERR_PTR(ret); - clk = clk_register(NULL, &osc->hw); - if (IS_ERR(clk)) { - free_irq(irq, osc); + if (IS_ERR(clk)) kfree(osc); - } return clk; } -void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np) { struct clk *clk; - unsigned int irq; u32 frequency = 0; u32 accuracy = 0; const char *name = np->name; + struct regmap *regmap; of_property_read_string(np, "clock-output-names", &name); of_property_read_u32(np, "clock-frequency", &frequency); of_property_read_u32(np, "clock-accuracy", &accuracy); - irq = irq_of_parse_and_map(np, 0); - if (!irq) + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) return; - clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency, - accuracy); + clk = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc", + of_at91sam9x5_clk_main_rc_osc_setup); -static int clk_main_probe_frequency(struct at91_pmc *pmc) +static int clk_main_probe_frequency(struct regmap *regmap) { unsigned long prep_time, timeout; - u32 tmp; + unsigned int mcfr; timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); do { prep_time = jiffies; - tmp = pmc_read(pmc, AT91_CKGR_MCFR); - if (tmp & AT91_PMC_MAINRDY) + regmap_read(regmap, AT91_CKGR_MCFR, &mcfr); + if (mcfr & AT91_PMC_MAINRDY) return 0; usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); } while (time_before(prep_time, timeout)); @@ -382,34 +348,37 @@ return -ETIMEDOUT; } -static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc, +static unsigned long clk_main_recalc_rate(struct regmap *regmap, unsigned long parent_rate) { - u32 tmp; + unsigned int mcfr; if (parent_rate) return parent_rate; pr_warn("Main crystal frequency not set, using approximate value\n"); - tmp = pmc_read(pmc, AT91_CKGR_MCFR); - if (!(tmp & AT91_PMC_MAINRDY)) + regmap_read(regmap, AT91_CKGR_MCFR, &mcfr); + if (!(mcfr & AT91_PMC_MAINRDY)) return 0; - return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; + return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV; } static int clk_rm9200_main_prepare(struct clk_hw *hw) { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); - return clk_main_probe_frequency(clkmain->pmc); + return clk_main_probe_frequency(clkmain->regmap); } static int clk_rm9200_main_is_prepared(struct clk_hw *hw) { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); + unsigned int status; + + regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status); - return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY); + return status & AT91_PMC_MAINRDY ? 1 : 0; } static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw, @@ -417,7 +386,7 @@ { struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw); - return clk_main_recalc_rate(clkmain->pmc, parent_rate); + return clk_main_recalc_rate(clkmain->regmap, parent_rate); } static const struct clk_ops rm9200_main_ops = { @@ -427,7 +396,7 @@ }; static struct clk * __init -at91_clk_register_rm9200_main(struct at91_pmc *pmc, +at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name) { @@ -435,7 +404,7 @@ struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !name) + if (!name) return ERR_PTR(-EINVAL); if (!parent_name) @@ -452,7 +421,7 @@ init.flags = 0; clkmain->hw.init = &init; - clkmain->pmc = pmc; + clkmain->regmap = regmap; clk = clk_register(NULL, &clkmain->hw); if (IS_ERR(clk)) @@ -461,52 +430,54 @@ return clk; } -void __init of_at91rm9200_clk_main_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_main_setup(struct device_node *np) { struct clk *clk; const char *parent_name; const char *name = np->name; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); - clk = at91_clk_register_rm9200_main(pmc, name, parent_name); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + clk = at91_clk_register_rm9200_main(regmap, name, parent_name); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main", + of_at91rm9200_clk_main_setup); -static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id) +static inline bool clk_sam9x5_main_ready(struct regmap *regmap) { - struct clk_sam9x5_main *clkmain = dev_id; + unsigned int status; - wake_up(&clkmain->wait); - disable_irq_nosync(clkmain->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & AT91_PMC_MOSCSELS ? 1 : 0; } static int clk_sam9x5_main_prepare(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); - struct at91_pmc *pmc = clkmain->pmc; + struct regmap *regmap = clkmain->regmap; - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { - enable_irq(clkmain->irq); - wait_event(clkmain->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); - } + while (!clk_sam9x5_main_ready(regmap)) + cpu_relax(); - return clk_main_probe_frequency(pmc); + return clk_main_probe_frequency(regmap); } static int clk_sam9x5_main_is_prepared(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); - return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); + return clk_sam9x5_main_ready(clkmain->regmap); } static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw, @@ -514,30 +485,28 @@ { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); - return clk_main_recalc_rate(clkmain->pmc, parent_rate); + return clk_main_recalc_rate(clkmain->regmap, parent_rate); } static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); - struct at91_pmc *pmc = clkmain->pmc; - u32 tmp; + struct regmap *regmap = clkmain->regmap; + unsigned int tmp; if (index > 1) return -EINVAL; - tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK; + regmap_read(regmap, AT91_CKGR_MOR, &tmp); + tmp &= ~MOR_KEY_MASK; if (index && !(tmp & AT91_PMC_MOSCSEL)) - pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); + regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL); else if (!index && (tmp & AT91_PMC_MOSCSEL)) - pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); + regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL); - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) { - enable_irq(clkmain->irq); - wait_event(clkmain->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS); - } + while (!clk_sam9x5_main_ready(regmap)) + cpu_relax(); return 0; } @@ -545,8 +514,11 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw) { struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw); + unsigned int status; + + regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); - return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN); + return status & AT91_PMC_MOSCEN ? 1 : 0; } static const struct clk_ops sam9x5_main_ops = { @@ -558,18 +530,17 @@ }; static struct clk * __init -at91_clk_register_sam9x5_main(struct at91_pmc *pmc, - unsigned int irq, +at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, int num_parents) { - int ret; struct clk_sam9x5_main *clkmain; struct clk *clk = NULL; struct clk_init_data init; + unsigned int status; - if (!pmc || !irq || !name) + if (!name) return ERR_PTR(-EINVAL); if (!parent_names || !num_parents) @@ -586,51 +557,42 @@ init.flags = CLK_SET_PARENT_GATE; clkmain->hw.init = &init; - clkmain->pmc = pmc; - clkmain->irq = irq; - clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & - AT91_PMC_MOSCEN); - init_waitqueue_head(&clkmain->wait); - irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN); - ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler, - IRQF_TRIGGER_HIGH, name, clkmain); - if (ret) - return ERR_PTR(ret); + clkmain->regmap = regmap; + regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status); + clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0; clk = clk_register(NULL, &clkmain->hw); - if (IS_ERR(clk)) { - free_irq(clkmain->irq, clkmain); + if (IS_ERR(clk)) kfree(clkmain); - } return clk; } -void __init of_at91sam9x5_clk_main_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_main_setup(struct device_node *np) { struct clk *clk; const char *parent_names[2]; int num_parents; - unsigned int irq; const char *name = np->name; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > 2) return; of_clk_parent_fill(np, parent_names, num_parents); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; of_property_read_string(np, "clock-output-names", &name); - irq = irq_of_parse_and_map(np, 0); - if (!irq) - return; - - clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names, + clk = at91_clk_register_sam9x5_main(regmap, name, parent_names, num_parents); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main", + of_at91sam9x5_clk_main_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c --- a/drivers/clk/at91/clk-master.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-master.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,13 +12,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -44,32 +39,26 @@ struct clk_master { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; const struct clk_master_layout *layout; const struct clk_master_characteristics *characteristics; }; -static irqreturn_t clk_master_irq_handler(int irq, void *dev_id) +static inline bool clk_master_ready(struct regmap *regmap) { - struct clk_master *master = (struct clk_master *)dev_id; + unsigned int status; - wake_up(&master->wait); - disable_irq_nosync(master->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & AT91_PMC_MCKRDY ? 1 : 0; } + static int clk_master_prepare(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); - struct at91_pmc *pmc = master->pmc; - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) { - enable_irq(master->irq); - wait_event(master->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY); - } + while (!clk_master_ready(master->regmap)) + cpu_relax(); return 0; } @@ -78,7 +67,7 @@ { struct clk_master *master = to_clk_master(hw); - return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY); + return clk_master_ready(master->regmap); } static unsigned long clk_master_recalc_rate(struct clk_hw *hw, @@ -88,18 +77,16 @@ u8 div; unsigned long rate = parent_rate; struct clk_master *master = to_clk_master(hw); - struct at91_pmc *pmc = master->pmc; const struct clk_master_layout *layout = master->layout; const struct clk_master_characteristics *characteristics = master->characteristics; - u32 tmp; + unsigned int mckr; - pmc_lock(pmc); - tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask; - pmc_unlock(pmc); + regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); + mckr &= layout->mask; - pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK; - div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) rate /= 3; @@ -119,9 +106,11 @@ static u8 clk_master_get_parent(struct clk_hw *hw) { struct clk_master *master = to_clk_master(hw); - struct at91_pmc *pmc = master->pmc; + unsigned int mckr; - return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS; + regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); + + return mckr & AT91_PMC_CSS; } static const struct clk_ops master_ops = { @@ -132,18 +121,17 @@ }; static struct clk * __init -at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, +at91_clk_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics) { - int ret; struct clk_master *master; struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !irq || !name || !num_parents || !parent_names) + if (!name || !num_parents || !parent_names) return ERR_PTR(-EINVAL); master = kzalloc(sizeof(*master), GFP_KERNEL); @@ -159,20 +147,10 @@ master->hw.init = &init; master->layout = layout; master->characteristics = characteristics; - master->pmc = pmc; - master->irq = irq; - init_waitqueue_head(&master->wait); - irq_set_status_flags(master->irq, IRQ_NOAUTOEN); - ret = request_irq(master->irq, clk_master_irq_handler, - IRQF_TRIGGER_HIGH, "clk-master", master); - if (ret) { - kfree(master); - return ERR_PTR(ret); - } + master->regmap = regmap; clk = clk_register(NULL, &master->hw); if (IS_ERR(clk)) { - free_irq(master->irq, master); kfree(master); } @@ -217,15 +195,15 @@ } static void __init -of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, +of_at91_clk_master_setup(struct device_node *np, const struct clk_master_layout *layout) { struct clk *clk; int num_parents; - unsigned int irq; const char *parent_names[MASTER_SOURCE_MAX]; const char *name = np->name; struct clk_master_characteristics *characteristics; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX) @@ -239,11 +217,11 @@ if (!characteristics) return; - irq = irq_of_parse_and_map(np, 0); - if (!irq) - goto out_free_characteristics; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; - clk = at91_clk_register_master(pmc, irq, name, num_parents, + clk = at91_clk_register_master(regmap, name, num_parents, parent_names, layout, characteristics); if (IS_ERR(clk)) @@ -256,14 +234,16 @@ kfree(characteristics); } -void __init of_at91rm9200_clk_master_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_master_setup(struct device_node *np) { - of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout); + of_at91_clk_master_setup(np, &at91rm9200_master_layout); } +CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master", + of_at91rm9200_clk_master_setup); -void __init of_at91sam9x5_clk_master_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_master_setup(struct device_node *np) { - of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout); + of_at91_clk_master_setup(np, &at91sam9x5_master_layout); } +CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master", + of_at91sam9x5_clk_master_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c --- a/drivers/clk/at91/clk-peripheral.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-peripheral.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,11 +12,13 @@ #include #include #include -#include -#include +#include +#include #include "pmc.h" +DEFINE_SPINLOCK(pmc_pcr_lock); + #define PERIPHERAL_MAX 64 #define PERIPHERAL_AT91RM9200 0 @@ -33,7 +35,7 @@ struct clk_peripheral { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; u32 id; }; @@ -41,8 +43,9 @@ struct clk_sam9x5_peripheral { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; struct clk_range range; + spinlock_t *lock; u32 id; u32 div; bool auto_div; @@ -54,7 +57,6 @@ static int clk_peripheral_enable(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; int offset = AT91_PMC_PCER; u32 id = periph->id; @@ -62,14 +64,14 @@ return 0; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCER1; - pmc_write(pmc, offset, PERIPHERAL_MASK(id)); + regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id)); + return 0; } static void clk_peripheral_disable(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; int offset = AT91_PMC_PCDR; u32 id = periph->id; @@ -77,21 +79,23 @@ return; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCDR1; - pmc_write(pmc, offset, PERIPHERAL_MASK(id)); + regmap_write(periph->regmap, offset, PERIPHERAL_MASK(id)); } static int clk_peripheral_is_enabled(struct clk_hw *hw) { struct clk_peripheral *periph = to_clk_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; int offset = AT91_PMC_PCSR; + unsigned int status; u32 id = periph->id; if (id < PERIPHERAL_ID_MIN) return 1; if (id > PERIPHERAL_ID_MAX) offset = AT91_PMC_PCSR1; - return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id)); + regmap_read(periph->regmap, offset, &status); + + return status & PERIPHERAL_MASK(id) ? 1 : 0; } static const struct clk_ops peripheral_ops = { @@ -101,14 +105,14 @@ }; static struct clk * __init -at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, +at91_clk_register_peripheral(struct regmap *regmap, const char *name, const char *parent_name, u32 id) { struct clk_peripheral *periph; struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) + if (!name || !parent_name || id > PERIPHERAL_ID_MAX) return ERR_PTR(-EINVAL); periph = kzalloc(sizeof(*periph), GFP_KERNEL); @@ -123,7 +127,7 @@ periph->id = id; periph->hw.init = &init; - periph->pmc = pmc; + periph->regmap = regmap; clk = clk_register(NULL, &periph->hw); if (IS_ERR(clk)) @@ -160,53 +164,58 @@ static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; - u32 tmp; + unsigned long flags; if (periph->id < PERIPHERAL_ID_MIN) return 0; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR) & ~AT91_PMC_PCR_DIV_MASK; - pmc_write(pmc, AT91_PMC_PCR, tmp | AT91_PMC_PCR_DIV(periph->div) - | AT91_PMC_PCR_CMD - | AT91_PMC_PCR_EN); - pmc_unlock(pmc); + spin_lock_irqsave(periph->lock, flags); + regmap_write(periph->regmap, AT91_PMC_PCR, + (periph->id & AT91_PMC_PCR_PID_MASK)); + regmap_update_bits(periph->regmap, AT91_PMC_PCR, + AT91_PMC_PCR_DIV_MASK | AT91_PMC_PCR_CMD | + AT91_PMC_PCR_EN, + AT91_PMC_PCR_DIV(periph->div) | + AT91_PMC_PCR_CMD | + AT91_PMC_PCR_EN); + spin_unlock_irqrestore(periph->lock, flags); + return 0; } static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; - u32 tmp; + unsigned long flags; if (periph->id < PERIPHERAL_ID_MIN) return; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR) & ~AT91_PMC_PCR_EN; - pmc_write(pmc, AT91_PMC_PCR, tmp | AT91_PMC_PCR_CMD); - pmc_unlock(pmc); + spin_lock_irqsave(periph->lock, flags); + regmap_write(periph->regmap, AT91_PMC_PCR, + (periph->id & AT91_PMC_PCR_PID_MASK)); + regmap_update_bits(periph->regmap, AT91_PMC_PCR, + AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD, + AT91_PMC_PCR_CMD); + spin_unlock_irqrestore(periph->lock, flags); } static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; - int ret; + unsigned long flags; + unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) return 1; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID_MASK)); - ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN); - pmc_unlock(pmc); + spin_lock_irqsave(periph->lock, flags); + regmap_write(periph->regmap, AT91_PMC_PCR, + (periph->id & AT91_PMC_PCR_PID_MASK)); + regmap_read(periph->regmap, AT91_PMC_PCR, &status); + spin_unlock_irqrestore(periph->lock, flags); - return ret; + return status & AT91_PMC_PCR_EN ? 1 : 0; } static unsigned long @@ -214,19 +223,20 @@ unsigned long parent_rate) { struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); - struct at91_pmc *pmc = periph->pmc; - u32 tmp; + unsigned long flags; + unsigned int status; if (periph->id < PERIPHERAL_ID_MIN) return parent_rate; - pmc_lock(pmc); - pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID_MASK)); - tmp = pmc_read(pmc, AT91_PMC_PCR); - pmc_unlock(pmc); + spin_lock_irqsave(periph->lock, flags); + regmap_write(periph->regmap, AT91_PMC_PCR, + (periph->id & AT91_PMC_PCR_PID_MASK)); + regmap_read(periph->regmap, AT91_PMC_PCR, &status); + spin_unlock_irqrestore(periph->lock, flags); - if (tmp & AT91_PMC_PCR_EN) { - periph->div = PERIPHERAL_RSHIFT(tmp); + if (status & AT91_PMC_PCR_EN) { + periph->div = PERIPHERAL_RSHIFT(status); periph->auto_div = false; } else { clk_sam9x5_peripheral_autodiv(periph); @@ -318,15 +328,15 @@ }; static struct clk * __init -at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, - const char *parent_name, u32 id, - const struct clk_range *range) +at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock, + const char *name, const char *parent_name, + u32 id, const struct clk_range *range) { struct clk_sam9x5_peripheral *periph; struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !name || !parent_name) + if (!name || !parent_name) return ERR_PTR(-EINVAL); periph = kzalloc(sizeof(*periph), GFP_KERNEL); @@ -342,7 +352,8 @@ periph->id = id; periph->hw.init = &init; periph->div = 0; - periph->pmc = pmc; + periph->regmap = regmap; + periph->lock = lock; periph->auto_div = true; periph->range = *range; @@ -356,7 +367,7 @@ } static void __init -of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) +of_at91_clk_periph_setup(struct device_node *np, u8 type) { int num; u32 id; @@ -364,6 +375,7 @@ const char *parent_name; const char *name; struct device_node *periphclknp; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) @@ -373,6 +385,10 @@ if (!num || num > PERIPHERAL_MAX) return; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + for_each_child_of_node(np, periphclknp) { if (of_property_read_u32(periphclknp, "reg", &id)) continue; @@ -384,7 +400,7 @@ name = periphclknp->name; if (type == PERIPHERAL_AT91RM9200) { - clk = at91_clk_register_peripheral(pmc, name, + clk = at91_clk_register_peripheral(regmap, name, parent_name, id); } else { struct clk_range range = CLK_RANGE(0, 0); @@ -393,7 +409,9 @@ "atmel,clk-output-range", &range); - clk = at91_clk_register_sam9x5_peripheral(pmc, name, + clk = at91_clk_register_sam9x5_peripheral(regmap, + &pmc_pcr_lock, + name, parent_name, id, &range); } @@ -405,14 +423,16 @@ } } -void __init of_at91rm9200_clk_periph_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_periph_setup(struct device_node *np) { - of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200); + of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200); } +CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral", + of_at91rm9200_clk_periph_setup); -void __init of_at91sam9x5_clk_periph_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np) { - of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5); + of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5); } +CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral", + of_at91sam9x5_clk_periph_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c --- a/drivers/clk/at91/clk-pll.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-pll.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,14 +12,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -58,9 +52,7 @@ struct clk_pll { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; u8 id; u8 div; u8 range; @@ -69,20 +61,19 @@ const struct clk_pll_characteristics *characteristics; }; -static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id) +static inline bool clk_pll_ready(struct regmap *regmap, int id) { - struct clk_pll *pll = (struct clk_pll *)dev_id; + unsigned int status; - wake_up(&pll->wait); - disable_irq_nosync(pll->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & PLL_STATUS_MASK(id) ? 1 : 0; } static int clk_pll_prepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); - struct at91_pmc *pmc = pll->pmc; + struct regmap *regmap = pll->regmap; const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = pll->characteristics; @@ -90,39 +81,34 @@ u32 mask = PLL_STATUS_MASK(id); int offset = PLL_REG(id); u8 out = 0; - u32 pllr, icpr; + unsigned int pllr; + unsigned int status; u8 div; u16 mul; - pllr = pmc_read(pmc, offset); + regmap_read(regmap, offset, &pllr); div = PLL_DIV(pllr); mul = PLL_MUL(pllr, layout); - if ((pmc_read(pmc, AT91_PMC_SR) & mask) && + regmap_read(regmap, AT91_PMC_SR, &status); + if ((status & mask) && (div == pll->div && mul == pll->mul)) return 0; if (characteristics->out) out = characteristics->out[pll->range]; - if (characteristics->icpll) { - icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id); - icpr |= (characteristics->icpll[pll->range] << - PLL_ICPR_SHIFT(id)); - pmc_write(pmc, AT91_PMC_PLLICPR, icpr); - } - pllr &= ~layout->pllr_mask; - pllr |= layout->pllr_mask & - (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | - (out << PLL_OUT_SHIFT) | - ((pll->mul & layout->mul_mask) << layout->mul_shift)); - pmc_write(pmc, offset, pllr); - - while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) { - enable_irq(pll->irq); - wait_event(pll->wait, - pmc_read(pmc, AT91_PMC_SR) & mask); - } + if (characteristics->icpll) + regmap_update_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), + characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); + + regmap_update_bits(regmap, offset, layout->pllr_mask, + pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | + (out << PLL_OUT_SHIFT) | + ((pll->mul & layout->mul_mask) << layout->mul_shift)); + + while (!clk_pll_ready(regmap, pll->id)) + cpu_relax(); return 0; } @@ -130,32 +116,35 @@ static int clk_pll_is_prepared(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); - struct at91_pmc *pmc = pll->pmc; - return !!(pmc_read(pmc, AT91_PMC_SR) & - PLL_STATUS_MASK(pll->id)); + return clk_pll_ready(pll->regmap, pll->id); } static void clk_pll_unprepare(struct clk_hw *hw) { struct clk_pll *pll = to_clk_pll(hw); - struct at91_pmc *pmc = pll->pmc; - const struct clk_pll_layout *layout = pll->layout; - int offset = PLL_REG(pll->id); - u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask); + unsigned int mask = pll->layout->pllr_mask; - pmc_write(pmc, offset, tmp); + regmap_update_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); } static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pll *pll = to_clk_pll(hw); + unsigned int pllr; + u16 mul; + u8 div; + + regmap_read(pll->regmap, PLL_REG(pll->id), &pllr); + + div = PLL_DIV(pllr); + mul = PLL_MUL(pllr, pll->layout); - if (!pll->div || !pll->mul) + if (!div || !mul) return 0; - return (parent_rate / pll->div) * (pll->mul + 1); + return (parent_rate / div) * (mul + 1); } static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, @@ -308,7 +297,7 @@ }; static struct clk * __init -at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, +at91_clk_register_pll(struct regmap *regmap, const char *name, const char *parent_name, u8 id, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) @@ -316,9 +305,8 @@ struct clk_pll *pll; struct clk *clk = NULL; struct clk_init_data init; - int ret; int offset = PLL_REG(id); - u32 tmp; + unsigned int pllr; if (id > PLL_MAX_ID) return ERR_PTR(-EINVAL); @@ -337,23 +325,13 @@ pll->hw.init = &init; pll->layout = layout; pll->characteristics = characteristics; - pll->pmc = pmc; - pll->irq = irq; - tmp = pmc_read(pmc, offset) & layout->pllr_mask; - pll->div = PLL_DIV(tmp); - pll->mul = PLL_MUL(tmp, layout); - init_waitqueue_head(&pll->wait); - irq_set_status_flags(pll->irq, IRQ_NOAUTOEN); - ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH, - id ? "clk-pllb" : "clk-plla", pll); - if (ret) { - kfree(pll); - return ERR_PTR(ret); - } + pll->regmap = regmap; + regmap_read(regmap, offset, &pllr); + pll->div = PLL_DIV(pllr); + pll->mul = PLL_MUL(pllr, layout); clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { - free_irq(pll->irq, pll); kfree(pll); } @@ -483,12 +461,12 @@ } static void __init -of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, +of_at91_clk_pll_setup(struct device_node *np, const struct clk_pll_layout *layout) { u32 id; - unsigned int irq; struct clk *clk; + struct regmap *regmap; const char *parent_name; const char *name = np->name; struct clk_pll_characteristics *characteristics; @@ -500,15 +478,15 @@ of_property_read_string(np, "clock-output-names", &name); - characteristics = of_at91_clk_pll_get_characteristics(np); - if (!characteristics) + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) return; - irq = irq_of_parse_and_map(np, 0); - if (!irq) + characteristics = of_at91_clk_pll_get_characteristics(np); + if (!characteristics) return; - clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout, + clk = at91_clk_register_pll(regmap, name, parent_name, id, layout, characteristics); if (IS_ERR(clk)) goto out_free_characteristics; @@ -520,26 +498,30 @@ kfree(characteristics); } -void __init of_at91rm9200_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_pll_setup(struct device_node *np) { - of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout); + of_at91_clk_pll_setup(np, &at91rm9200_pll_layout); } +CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll", + of_at91rm9200_clk_pll_setup); -void __init of_at91sam9g45_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np) { - of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout); + of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout); } +CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll", + of_at91sam9g45_clk_pll_setup); -void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np) { - of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout); + of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout); } +CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb", + of_at91sam9g20_clk_pllb_setup); -void __init of_sama5d3_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_sama5d3_clk_pll_setup(struct device_node *np) { - of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout); + of_at91_clk_pll_setup(np, &sama5d3_pll_layout); } +CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll", + of_sama5d3_clk_pll_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c --- a/drivers/clk/at91/clk-plldiv.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-plldiv.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include "pmc.h" @@ -21,16 +21,18 @@ struct clk_plldiv { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_plldiv *plldiv = to_clk_plldiv(hw); - struct at91_pmc *pmc = plldiv->pmc; + unsigned int mckr; - if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2) + regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); + + if (mckr & AT91_PMC_PLLADIV2) return parent_rate / 2; return parent_rate; @@ -57,18 +59,12 @@ unsigned long parent_rate) { struct clk_plldiv *plldiv = to_clk_plldiv(hw); - struct at91_pmc *pmc = plldiv->pmc; - u32 tmp; - if (parent_rate != rate && (parent_rate / 2) != rate) + if ((parent_rate != rate) && (parent_rate / 2 != rate)) return -EINVAL; - pmc_lock(pmc); - tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2; - if ((parent_rate / 2) == rate) - tmp |= AT91_PMC_PLLADIV2; - pmc_write(pmc, AT91_PMC_MCKR, tmp); - pmc_unlock(pmc); + regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2, + parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); return 0; } @@ -80,7 +76,7 @@ }; static struct clk * __init -at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, +at91_clk_register_plldiv(struct regmap *regmap, const char *name, const char *parent_name) { struct clk_plldiv *plldiv; @@ -98,7 +94,7 @@ init.flags = CLK_SET_RATE_GATE; plldiv->hw.init = &init; - plldiv->pmc = pmc; + plldiv->regmap = regmap; clk = clk_register(NULL, &plldiv->hw); @@ -109,27 +105,27 @@ } static void __init -of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) +of_at91sam9x5_clk_plldiv_setup(struct device_node *np) { struct clk *clk; const char *parent_name; const char *name = np->name; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); - clk = at91_clk_register_plldiv(pmc, name, parent_name); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + clk = at91_clk_register_plldiv(regmap, name, parent_name); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); return; } - -void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np, - struct at91_pmc *pmc) -{ - of_at91_clk_plldiv_setup(np, pmc); -} +CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", + of_at91sam9x5_clk_plldiv_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c --- a/drivers/clk/at91/clk-programmable.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-programmable.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,10 +12,8 @@ #include #include #include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -24,6 +22,7 @@ #define PROG_STATUS_MASK(id) (1 << ((id) + 8)) #define PROG_PRES_MASK 0x7 +#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & PROG_PRES_MASK) #define PROG_MAX_RM9200_CSS 3 struct clk_programmable_layout { @@ -34,7 +33,7 @@ struct clk_programmable { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; u8 id; const struct clk_programmable_layout *layout; }; @@ -44,14 +43,12 @@ static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u32 pres; struct clk_programmable *prog = to_clk_programmable(hw); - struct at91_pmc *pmc = prog->pmc; - const struct clk_programmable_layout *layout = prog->layout; + unsigned int pckr; + + regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); - pres = (pmc_read(pmc, AT91_PMC_PCKR(prog->id)) >> layout->pres_shift) & - PROG_PRES_MASK; - return parent_rate >> pres; + return parent_rate >> PROG_PRES(prog->layout, pckr); } static int clk_programmable_determine_rate(struct clk_hw *hw, @@ -101,36 +98,36 @@ { struct clk_programmable *prog = to_clk_programmable(hw); const struct clk_programmable_layout *layout = prog->layout; - struct at91_pmc *pmc = prog->pmc; - u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) & ~layout->css_mask; + unsigned int mask = layout->css_mask; + unsigned int pckr = 0; if (layout->have_slck_mck) - tmp &= AT91_PMC_CSSMCK_MCK; + mask |= AT91_PMC_CSSMCK_MCK; if (index > layout->css_mask) { - if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) { - tmp |= AT91_PMC_CSSMCK_MCK; - return 0; - } else { + if (index > PROG_MAX_RM9200_CSS && !layout->have_slck_mck) return -EINVAL; - } + + pckr |= AT91_PMC_CSSMCK_MCK; } - pmc_write(pmc, AT91_PMC_PCKR(prog->id), tmp | index); + regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), mask, pckr); + return 0; } static u8 clk_programmable_get_parent(struct clk_hw *hw) { - u32 tmp; - u8 ret; struct clk_programmable *prog = to_clk_programmable(hw); - struct at91_pmc *pmc = prog->pmc; const struct clk_programmable_layout *layout = prog->layout; + unsigned int pckr; + u8 ret; + + regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); + + ret = pckr & layout->css_mask; - tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)); - ret = tmp & layout->css_mask; - if (layout->have_slck_mck && (tmp & AT91_PMC_CSSMCK_MCK) && !ret) + if (layout->have_slck_mck && (pckr & AT91_PMC_CSSMCK_MCK) && !ret) ret = PROG_MAX_RM9200_CSS + 1; return ret; @@ -140,26 +137,27 @@ unsigned long parent_rate) { struct clk_programmable *prog = to_clk_programmable(hw); - struct at91_pmc *pmc = prog->pmc; const struct clk_programmable_layout *layout = prog->layout; unsigned long div = parent_rate / rate; + unsigned int pckr; int shift = 0; - u32 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)) & - ~(PROG_PRES_MASK << layout->pres_shift); + + regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr); if (!div) return -EINVAL; shift = fls(div) - 1; - if (div != (1<= PROG_PRES_MASK) return -EINVAL; - pmc_write(pmc, AT91_PMC_PCKR(prog->id), - tmp | (shift << layout->pres_shift)); + regmap_update_bits(prog->regmap, AT91_PMC_PCKR(prog->id), + PROG_PRES_MASK << layout->pres_shift, + shift << layout->pres_shift); return 0; } @@ -173,7 +171,7 @@ }; static struct clk * __init -at91_clk_register_programmable(struct at91_pmc *pmc, +at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout) @@ -198,7 +196,7 @@ prog->id = id; prog->layout = layout; prog->hw.init = &init; - prog->pmc = pmc; + prog->regmap = regmap; clk = clk_register(NULL, &prog->hw); if (IS_ERR(clk)) @@ -226,7 +224,7 @@ }; static void __init -of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, +of_at91_clk_prog_setup(struct device_node *np, const struct clk_programmable_layout *layout) { int num; @@ -236,6 +234,7 @@ const char *parent_names[PROG_SOURCE_MAX]; const char *name; struct device_node *progclknp; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX) @@ -247,6 +246,10 @@ if (!num || num > (PROG_ID_MAX + 1)) return; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + for_each_child_of_node(np, progclknp) { if (of_property_read_u32(progclknp, "reg", &id)) continue; @@ -254,7 +257,7 @@ if (of_property_read_string(np, "clock-output-names", &name)) name = progclknp->name; - clk = at91_clk_register_programmable(pmc, name, + clk = at91_clk_register_programmable(regmap, name, parent_names, num_parents, id, layout); if (IS_ERR(clk)) @@ -265,20 +268,23 @@ } -void __init of_at91rm9200_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_prog_setup(struct device_node *np) { - of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout); + of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout); } +CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable", + of_at91rm9200_clk_prog_setup); -void __init of_at91sam9g45_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np) { - of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout); + of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout); } +CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable", + of_at91sam9g45_clk_prog_setup); -void __init of_at91sam9x5_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np) { - of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout); + of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout); } +CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable", + of_at91sam9x5_clk_prog_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c --- a/drivers/clk/at91/clk-slow.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-slow.c 2016-05-11 13:31:53.197225234 -0400 @@ -13,17 +13,11 @@ #include #include #include -#include #include #include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" #include "sckc.h" @@ -59,7 +53,7 @@ struct clk_sam9260_slow { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; #define to_clk_sam9260_slow(hw) container_of(hw, struct clk_sam9260_slow, hw) @@ -393,8 +387,11 @@ static u8 clk_sam9260_slow_get_parent(struct clk_hw *hw) { struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw); + unsigned int status; - return !!(pmc_read(slowck->pmc, AT91_PMC_SR) & AT91_PMC_OSCSEL); + regmap_read(slowck->regmap, AT91_PMC_SR, &status); + + return status & AT91_PMC_OSCSEL ? 1 : 0; } static const struct clk_ops sam9260_slow_ops = { @@ -402,7 +399,7 @@ }; static struct clk * __init -at91_clk_register_sam9260_slow(struct at91_pmc *pmc, +at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, int num_parents) @@ -411,7 +408,7 @@ struct clk *clk = NULL; struct clk_init_data init; - if (!pmc || !name) + if (!name) return ERR_PTR(-EINVAL); if (!parent_names || !num_parents) @@ -428,7 +425,7 @@ init.flags = 0; slowck->hw.init = &init; - slowck->pmc = pmc; + slowck->regmap = regmap; clk = clk_register(NULL, &slowck->hw); if (IS_ERR(clk)) @@ -439,29 +436,34 @@ return clk; } -void __init of_at91sam9260_clk_slow_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) { struct clk *clk; const char *parent_names[2]; int num_parents; const char *name = np->name; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents != 2) return; of_clk_parent_fill(np, parent_names, num_parents); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; of_property_read_string(np, "clock-output-names", &name); - clk = at91_clk_register_sam9260_slow(pmc, name, parent_names, + clk = at91_clk_register_sam9260_slow(regmap, name, parent_names, num_parents); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow", + of_at91sam9260_clk_slow_setup); /* * FIXME: All slow clk users are not properly claiming it (get + prepare + diff -Naur --no-dereference a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c --- a/drivers/clk/at91/clk-smd.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-smd.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include "pmc.h" @@ -24,7 +24,7 @@ struct at91sam9x5_clk_smd { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; #define to_at91sam9x5_clk_smd(hw) \ @@ -33,13 +33,13 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u32 tmp; - u8 smddiv; struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); - struct at91_pmc *pmc = smd->pmc; + unsigned int smdr; + u8 smddiv; + + regmap_read(smd->regmap, AT91_PMC_SMD, &smdr); + smddiv = (smdr & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT; - tmp = pmc_read(pmc, AT91_PMC_SMD); - smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT; return parent_rate / (smddiv + 1); } @@ -67,40 +67,38 @@ static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index) { - u32 tmp; struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); - struct at91_pmc *pmc = smd->pmc; if (index > 1) return -EINVAL; - tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS; - if (index) - tmp |= AT91_PMC_SMDS; - pmc_write(pmc, AT91_PMC_SMD, tmp); + + regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMDS, + index ? AT91_PMC_SMDS : 0); + return 0; } static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw) { struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); - struct at91_pmc *pmc = smd->pmc; + unsigned int smdr; - return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS; + regmap_read(smd->regmap, AT91_PMC_SMD, &smdr); + + return smdr & AT91_PMC_SMDS; } static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - u32 tmp; struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); - struct at91_pmc *pmc = smd->pmc; unsigned long div = parent_rate / rate; if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1)) return -EINVAL; - tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV; - tmp |= (div - 1) << SMD_DIV_SHIFT; - pmc_write(pmc, AT91_PMC_SMD, tmp); + + regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMD_DIV, + (div - 1) << SMD_DIV_SHIFT); return 0; } @@ -114,7 +112,7 @@ }; static struct clk * __init -at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, +at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_smd *smd; @@ -132,7 +130,7 @@ init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; smd->hw.init = &init; - smd->pmc = pmc; + smd->regmap = regmap; clk = clk_register(NULL, &smd->hw); if (IS_ERR(clk)) @@ -141,13 +139,13 @@ return clk; } -void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np) { struct clk *clk; int num_parents; const char *parent_names[SMD_SOURCE_MAX]; const char *name = np->name; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX) @@ -157,10 +155,16 @@ of_property_read_string(np, "clock-output-names", &name); - clk = at91sam9x5_clk_register_smd(pmc, name, parent_names, + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + clk = at91sam9x5_clk_register_smd(regmap, name, parent_names, num_parents); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd", + of_at91sam9x5_clk_smd_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c --- a/drivers/clk/at91/clk-system.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-system.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,13 +12,8 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -29,9 +24,7 @@ #define to_clk_system(hw) container_of(hw, struct clk_system, hw) struct clk_system { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; u8 id; }; @@ -39,58 +32,54 @@ { return (id >= 8) && (id <= 15); } -static irqreturn_t clk_system_irq_handler(int irq, void *dev_id) + +static inline bool clk_system_ready(struct regmap *regmap, int id) { - struct clk_system *sys = (struct clk_system *)dev_id; + unsigned int status; - wake_up(&sys->wait); - disable_irq_nosync(sys->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & (1 << id) ? 1 : 0; } static int clk_system_prepare(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); - struct at91_pmc *pmc = sys->pmc; - u32 mask = 1 << sys->id; - pmc_write(pmc, AT91_PMC_SCER, mask); + regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); if (!is_pck(sys->id)) return 0; - while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) { - if (sys->irq) { - enable_irq(sys->irq); - wait_event(sys->wait, - pmc_read(pmc, AT91_PMC_SR) & mask); - } else - cpu_relax(); - } + while (!clk_system_ready(sys->regmap, sys->id)) + cpu_relax(); + return 0; } static void clk_system_unprepare(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); - struct at91_pmc *pmc = sys->pmc; - pmc_write(pmc, AT91_PMC_SCDR, 1 << sys->id); + regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); } static int clk_system_is_prepared(struct clk_hw *hw) { struct clk_system *sys = to_clk_system(hw); - struct at91_pmc *pmc = sys->pmc; + unsigned int status; + + regmap_read(sys->regmap, AT91_PMC_SCSR, &status); - if (!(pmc_read(pmc, AT91_PMC_SCSR) & (1 << sys->id))) + if (!(status & (1 << sys->id))) return 0; if (!is_pck(sys->id)) return 1; - return !!(pmc_read(pmc, AT91_PMC_SR) & (1 << sys->id)); + regmap_read(sys->regmap, AT91_PMC_SR, &status); + + return status & (1 << sys->id) ? 1 : 0; } static const struct clk_ops system_ops = { @@ -100,13 +89,12 @@ }; static struct clk * __init -at91_clk_register_system(struct at91_pmc *pmc, const char *name, - const char *parent_name, u8 id, int irq) +at91_clk_register_system(struct regmap *regmap, const char *name, + const char *parent_name, u8 id) { struct clk_system *sys; struct clk *clk = NULL; struct clk_init_data init; - int ret; if (!parent_name || id > SYSTEM_MAX_ID) return ERR_PTR(-EINVAL); @@ -123,44 +111,33 @@ sys->id = id; sys->hw.init = &init; - sys->pmc = pmc; - sys->irq = irq; - if (irq) { - init_waitqueue_head(&sys->wait); - irq_set_status_flags(sys->irq, IRQ_NOAUTOEN); - ret = request_irq(sys->irq, clk_system_irq_handler, - IRQF_TRIGGER_HIGH, name, sys); - if (ret) { - kfree(sys); - return ERR_PTR(ret); - } - } + sys->regmap = regmap; clk = clk_register(NULL, &sys->hw); - if (IS_ERR(clk)) { - if (irq) - free_irq(sys->irq, sys); + if (IS_ERR(clk)) kfree(sys); - } return clk; } -static void __init -of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_sys_setup(struct device_node *np) { int num; - int irq = 0; u32 id; struct clk *clk; const char *name; struct device_node *sysclknp; const char *parent_name; + struct regmap *regmap; num = of_get_child_count(np); if (num > (SYSTEM_MAX_ID + 1)) return; + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + for_each_child_of_node(np, sysclknp) { if (of_property_read_u32(sysclknp, "reg", &id)) continue; @@ -168,21 +145,14 @@ if (of_property_read_string(np, "clock-output-names", &name)) name = sysclknp->name; - if (is_pck(id)) - irq = irq_of_parse_and_map(sysclknp, 0); - parent_name = of_clk_get_parent_name(sysclknp, 0); - clk = at91_clk_register_system(pmc, name, parent_name, id, irq); + clk = at91_clk_register_system(regmap, name, parent_name, id); if (IS_ERR(clk)) continue; of_clk_add_provider(sysclknp, of_clk_src_simple_get, clk); } } - -void __init of_at91rm9200_clk_sys_setup(struct device_node *np, - struct at91_pmc *pmc) -{ - of_at91_clk_sys_setup(np, pmc); -} +CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system", + of_at91rm9200_clk_sys_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c --- a/drivers/clk/at91/clk-usb.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-usb.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,8 +12,8 @@ #include #include #include -#include -#include +#include +#include #include "pmc.h" @@ -27,7 +27,7 @@ struct at91sam9x5_clk_usb { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; }; #define to_at91sam9x5_clk_usb(hw) \ @@ -35,7 +35,7 @@ struct at91rm9200_clk_usb { struct clk_hw hw; - struct at91_pmc *pmc; + struct regmap *regmap; u32 divisors[4]; }; @@ -45,13 +45,12 @@ static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - u32 tmp; - u8 usbdiv; struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; + unsigned int usbr; + u8 usbdiv; - tmp = pmc_read(pmc, AT91_PMC_USB); - usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; + regmap_read(usb->regmap, AT91_PMC_USB, &usbr); + usbdiv = (usbr & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1)); } @@ -109,33 +108,31 @@ static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) { - u32 tmp; struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; if (index > 1) return -EINVAL; - tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS; - if (index) - tmp |= AT91_PMC_USBS; - pmc_write(pmc, AT91_PMC_USB, tmp); + + regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, + index ? AT91_PMC_USBS : 0); + return 0; } static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; + unsigned int usbr; - return pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS; + regmap_read(usb->regmap, AT91_PMC_USB, &usbr); + + return usbr & AT91_PMC_USBS; } static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - u32 tmp; struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; unsigned long div; if (!rate) @@ -145,9 +142,8 @@ if (div > SAM9X5_USB_MAX_DIV + 1 || !div) return -EINVAL; - tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV; - tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT; - pmc_write(pmc, AT91_PMC_USB, tmp); + regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_OHCIUSBDIV, + (div - 1) << SAM9X5_USB_DIV_SHIFT); return 0; } @@ -163,28 +159,28 @@ static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; - pmc_write(pmc, AT91_PMC_USB, - pmc_read(pmc, AT91_PMC_USB) | AT91_PMC_USBS); + regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, + AT91_PMC_USBS); + return 0; } static void at91sam9n12_clk_usb_disable(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; - pmc_write(pmc, AT91_PMC_USB, - pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS); + regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, 0); } static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw) { struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; + unsigned int usbr; - return !!(pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS); + regmap_read(usb->regmap, AT91_PMC_USB, &usbr); + + return usbr & AT91_PMC_USBS; } static const struct clk_ops at91sam9n12_usb_ops = { @@ -197,7 +193,7 @@ }; static struct clk * __init -at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, +at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents) { struct at91sam9x5_clk_usb *usb; @@ -216,7 +212,7 @@ CLK_SET_RATE_PARENT; usb->hw.init = &init; - usb->pmc = pmc; + usb->regmap = regmap; clk = clk_register(NULL, &usb->hw); if (IS_ERR(clk)) @@ -226,7 +222,7 @@ } static struct clk * __init -at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, +at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name) { struct at91sam9x5_clk_usb *usb; @@ -244,7 +240,7 @@ init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; usb->hw.init = &init; - usb->pmc = pmc; + usb->regmap = regmap; clk = clk_register(NULL, &usb->hw); if (IS_ERR(clk)) @@ -257,12 +253,12 @@ unsigned long parent_rate) { struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; - u32 tmp; + unsigned int pllbr; u8 usbdiv; - tmp = pmc_read(pmc, AT91_CKGR_PLLBR); - usbdiv = (tmp & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT; + regmap_read(usb->regmap, AT91_CKGR_PLLBR, &pllbr); + + usbdiv = (pllbr & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT; if (usb->divisors[usbdiv]) return parent_rate / usb->divisors[usbdiv]; @@ -310,10 +306,8 @@ static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - u32 tmp; int i; struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); - struct at91_pmc *pmc = usb->pmc; unsigned long div; if (!rate) @@ -323,10 +317,10 @@ for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { if (usb->divisors[i] == div) { - tmp = pmc_read(pmc, AT91_CKGR_PLLBR) & - ~AT91_PMC_USBDIV; - tmp |= i << RM9200_USB_DIV_SHIFT; - pmc_write(pmc, AT91_CKGR_PLLBR, tmp); + regmap_update_bits(usb->regmap, AT91_CKGR_PLLBR, + AT91_PMC_USBDIV, + i << RM9200_USB_DIV_SHIFT); + return 0; } } @@ -341,7 +335,7 @@ }; static struct clk * __init -at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, +at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, const char *parent_name, const u32 *divisors) { struct at91rm9200_clk_usb *usb; @@ -359,7 +353,7 @@ init.flags = CLK_SET_RATE_PARENT; usb->hw.init = &init; - usb->pmc = pmc; + usb->regmap = regmap; memcpy(usb->divisors, divisors, sizeof(usb->divisors)); clk = clk_register(NULL, &usb->hw); @@ -369,13 +363,13 @@ return clk; } -void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np) { struct clk *clk; int num_parents; const char *parent_names[USB_SOURCE_MAX]; const char *name = np->name; + struct regmap *regmap; num_parents = of_clk_get_parent_count(np); if (num_parents <= 0 || num_parents > USB_SOURCE_MAX) @@ -385,19 +379,26 @@ of_property_read_string(np, "clock-output-names", &name); - clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + clk = at91sam9x5_clk_register_usb(regmap, name, parent_names, + num_parents); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb", + of_at91sam9x5_clk_usb_setup); -void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np) { struct clk *clk; const char *parent_name; const char *name = np->name; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) @@ -405,20 +406,26 @@ of_property_read_string(np, "clock-output-names", &name); - clk = at91sam9n12_clk_register_usb(pmc, name, parent_name); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + clk = at91sam9n12_clk_register_usb(regmap, name, parent_name); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb", + of_at91sam9n12_clk_usb_setup); -void __init of_at91rm9200_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc) +static void __init of_at91rm9200_clk_usb_setup(struct device_node *np) { struct clk *clk; const char *parent_name; const char *name = np->name; u32 divisors[4] = {0, 0, 0, 0}; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); if (!parent_name) @@ -430,9 +437,15 @@ of_property_read_string(np, "clock-output-names", &name); - clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors); + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) + return; + + clk = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); } +CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb", + of_at91rm9200_clk_usb_setup); diff -Naur --no-dereference a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c --- a/drivers/clk/at91/clk-utmi.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/clk-utmi.c 2016-05-11 13:31:53.197225234 -0400 @@ -11,14 +11,9 @@ #include #include #include -#include -#include #include -#include -#include -#include -#include -#include +#include +#include #include "pmc.h" @@ -26,37 +21,30 @@ struct clk_utmi { struct clk_hw hw; - struct at91_pmc *pmc; - unsigned int irq; - wait_queue_head_t wait; + struct regmap *regmap; }; #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) -static irqreturn_t clk_utmi_irq_handler(int irq, void *dev_id) +static inline bool clk_utmi_ready(struct regmap *regmap) { - struct clk_utmi *utmi = (struct clk_utmi *)dev_id; + unsigned int status; - wake_up(&utmi->wait); - disable_irq_nosync(utmi->irq); + regmap_read(regmap, AT91_PMC_SR, &status); - return IRQ_HANDLED; + return status & AT91_PMC_LOCKU; } static int clk_utmi_prepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); - struct at91_pmc *pmc = utmi->pmc; - u32 tmp = pmc_read(pmc, AT91_CKGR_UCKR) | AT91_PMC_UPLLEN | - AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; - - pmc_write(pmc, AT91_CKGR_UCKR, tmp); - - while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) { - enable_irq(utmi->irq); - wait_event(utmi->wait, - pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU); - } + unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | + AT91_PMC_BIASEN; + + regmap_update_bits(utmi->regmap, AT91_CKGR_UCKR, uckr, uckr); + + while (!clk_utmi_ready(utmi->regmap)) + cpu_relax(); return 0; } @@ -64,18 +52,15 @@ static int clk_utmi_is_prepared(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); - struct at91_pmc *pmc = utmi->pmc; - return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU); + return clk_utmi_ready(utmi->regmap); } static void clk_utmi_unprepare(struct clk_hw *hw) { struct clk_utmi *utmi = to_clk_utmi(hw); - struct at91_pmc *pmc = utmi->pmc; - u32 tmp = pmc_read(pmc, AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN; - pmc_write(pmc, AT91_CKGR_UCKR, tmp); + regmap_update_bits(utmi->regmap, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); } static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, @@ -93,10 +78,9 @@ }; static struct clk * __init -at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, +at91_clk_register_utmi(struct regmap *regmap, const char *name, const char *parent_name) { - int ret; struct clk_utmi *utmi; struct clk *clk = NULL; struct clk_init_data init; @@ -112,52 +96,36 @@ init.flags = CLK_SET_RATE_GATE; utmi->hw.init = &init; - utmi->pmc = pmc; - utmi->irq = irq; - init_waitqueue_head(&utmi->wait); - irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN); - ret = request_irq(utmi->irq, clk_utmi_irq_handler, - IRQF_TRIGGER_HIGH, "clk-utmi", utmi); - if (ret) { - kfree(utmi); - return ERR_PTR(ret); - } + utmi->regmap = regmap; clk = clk_register(NULL, &utmi->hw); - if (IS_ERR(clk)) { - free_irq(utmi->irq, utmi); + if (IS_ERR(clk)) kfree(utmi); - } return clk; } -static void __init -of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) +static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np) { - unsigned int irq; struct clk *clk; const char *parent_name; const char *name = np->name; + struct regmap *regmap; parent_name = of_clk_get_parent_name(np, 0); of_property_read_string(np, "clock-output-names", &name); - irq = irq_of_parse_and_map(np, 0); - if (!irq) + regmap = syscon_node_to_regmap(of_get_parent(np)); + if (IS_ERR(regmap)) return; - clk = at91_clk_register_utmi(pmc, irq, name, parent_name); + clk = at91_clk_register_utmi(regmap, name, parent_name); if (IS_ERR(clk)) return; of_clk_add_provider(np, of_clk_src_simple_get, clk); return; } - -void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np, - struct at91_pmc *pmc) -{ - of_at91_clk_utmi_setup(np, pmc); -} +CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi", + of_at91sam9x5_clk_utmi_setup); diff -Naur --no-dereference a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c --- a/drivers/clk/at91/pmc.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/pmc.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,36 +12,13 @@ #include #include #include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include #include "pmc.h" -void __iomem *at91_pmc_base; -EXPORT_SYMBOL_GPL(at91_pmc_base); - -void at91rm9200_idle(void) -{ - /* - * Disable the processor clock. The processor will be automatically - * re-enabled by an interrupt or by a reset. - */ - at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); -} - -void at91sam9_idle(void) -{ - at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); - cpu_do_idle(); -} - int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk_range *range) { @@ -64,402 +41,3 @@ return 0; } EXPORT_SYMBOL_GPL(of_at91_get_clk_range); - -static void pmc_irq_mask(struct irq_data *d) -{ - struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); - - pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq); -} - -static void pmc_irq_unmask(struct irq_data *d) -{ - struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); - - pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq); -} - -static int pmc_irq_set_type(struct irq_data *d, unsigned type) -{ - if (type != IRQ_TYPE_LEVEL_HIGH) { - pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n"); - return -EINVAL; - } - - return 0; -} - -static void pmc_irq_suspend(struct irq_data *d) -{ - struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); - - pmc->imr = pmc_read(pmc, AT91_PMC_IMR); - pmc_write(pmc, AT91_PMC_IDR, pmc->imr); -} - -static void pmc_irq_resume(struct irq_data *d) -{ - struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); - - pmc_write(pmc, AT91_PMC_IER, pmc->imr); -} - -static struct irq_chip pmc_irq = { - .name = "PMC", - .irq_disable = pmc_irq_mask, - .irq_mask = pmc_irq_mask, - .irq_unmask = pmc_irq_unmask, - .irq_set_type = pmc_irq_set_type, - .irq_suspend = pmc_irq_suspend, - .irq_resume = pmc_irq_resume, -}; - -static struct lock_class_key pmc_lock_class; - -static int pmc_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - struct at91_pmc *pmc = h->host_data; - - irq_set_lockdep_class(virq, &pmc_lock_class); - - irq_set_chip_and_handler(virq, &pmc_irq, - handle_level_irq); - irq_set_chip_data(virq, pmc); - - return 0; -} - -static int pmc_irq_domain_xlate(struct irq_domain *d, - struct device_node *ctrlr, - const u32 *intspec, unsigned int intsize, - irq_hw_number_t *out_hwirq, - unsigned int *out_type) -{ - struct at91_pmc *pmc = d->host_data; - const struct at91_pmc_caps *caps = pmc->caps; - - if (WARN_ON(intsize < 1)) - return -EINVAL; - - *out_hwirq = intspec[0]; - - if (!(caps->available_irqs & (1 << *out_hwirq))) - return -EINVAL; - - *out_type = IRQ_TYPE_LEVEL_HIGH; - - return 0; -} - -static const struct irq_domain_ops pmc_irq_ops = { - .map = pmc_irq_map, - .xlate = pmc_irq_domain_xlate, -}; - -static irqreturn_t pmc_irq_handler(int irq, void *data) -{ - struct at91_pmc *pmc = (struct at91_pmc *)data; - unsigned long sr; - int n; - - sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR); - if (!sr) - return IRQ_NONE; - - for_each_set_bit(n, &sr, BITS_PER_LONG) - generic_handle_irq(irq_find_mapping(pmc->irqdomain, n)); - - return IRQ_HANDLED; -} - -static const struct at91_pmc_caps at91rm9200_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | - AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY | - AT91_PMC_PCK3RDY, -}; - -static const struct at91_pmc_caps at91sam9260_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | - AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY, -}; - -static const struct at91_pmc_caps at91sam9g45_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | - AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY, -}; - -static const struct at91_pmc_caps at91sam9n12_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | - AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS | - AT91_PMC_MOSCRCS | AT91_PMC_CFDEV, -}; - -static const struct at91_pmc_caps at91sam9x5_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | - AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS | - AT91_PMC_MOSCRCS | AT91_PMC_CFDEV, -}; - -static const struct at91_pmc_caps sama5d2_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | - AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY | - AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS | - AT91_PMC_CFDEV | AT91_PMC_GCKRDY, -}; - -static const struct at91_pmc_caps sama5d3_caps = { - .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | - AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | - AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY | - AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS | - AT91_PMC_CFDEV, -}; - -static struct at91_pmc *__init at91_pmc_init(struct device_node *np, - void __iomem *regbase, int virq, - const struct at91_pmc_caps *caps) -{ - struct at91_pmc *pmc; - - if (!regbase || !virq || !caps) - return NULL; - - at91_pmc_base = regbase; - - pmc = kzalloc(sizeof(*pmc), GFP_KERNEL); - if (!pmc) - return NULL; - - spin_lock_init(&pmc->lock); - pmc->regbase = regbase; - pmc->virq = virq; - pmc->caps = caps; - - pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc); - - if (!pmc->irqdomain) - goto out_free_pmc; - - pmc_write(pmc, AT91_PMC_IDR, 0xffffffff); - if (request_irq(pmc->virq, pmc_irq_handler, - IRQF_SHARED | IRQF_COND_SUSPEND, "pmc", pmc)) - goto out_remove_irqdomain; - - return pmc; - -out_remove_irqdomain: - irq_domain_remove(pmc->irqdomain); -out_free_pmc: - kfree(pmc); - - return NULL; -} - -static const struct of_device_id pmc_clk_ids[] __initconst = { - /* Slow oscillator */ - { - .compatible = "atmel,at91sam9260-clk-slow", - .data = of_at91sam9260_clk_slow_setup, - }, - /* Main clock */ - { - .compatible = "atmel,at91rm9200-clk-main-osc", - .data = of_at91rm9200_clk_main_osc_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-main-rc-osc", - .data = of_at91sam9x5_clk_main_rc_osc_setup, - }, - { - .compatible = "atmel,at91rm9200-clk-main", - .data = of_at91rm9200_clk_main_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-main", - .data = of_at91sam9x5_clk_main_setup, - }, - /* PLL clocks */ - { - .compatible = "atmel,at91rm9200-clk-pll", - .data = of_at91rm9200_clk_pll_setup, - }, - { - .compatible = "atmel,at91sam9g45-clk-pll", - .data = of_at91sam9g45_clk_pll_setup, - }, - { - .compatible = "atmel,at91sam9g20-clk-pllb", - .data = of_at91sam9g20_clk_pllb_setup, - }, - { - .compatible = "atmel,sama5d3-clk-pll", - .data = of_sama5d3_clk_pll_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-plldiv", - .data = of_at91sam9x5_clk_plldiv_setup, - }, - /* Master clock */ - { - .compatible = "atmel,at91rm9200-clk-master", - .data = of_at91rm9200_clk_master_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-master", - .data = of_at91sam9x5_clk_master_setup, - }, - /* System clocks */ - { - .compatible = "atmel,at91rm9200-clk-system", - .data = of_at91rm9200_clk_sys_setup, - }, - /* Peripheral clocks */ - { - .compatible = "atmel,at91rm9200-clk-peripheral", - .data = of_at91rm9200_clk_periph_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-peripheral", - .data = of_at91sam9x5_clk_periph_setup, - }, - /* Programmable clocks */ - { - .compatible = "atmel,at91rm9200-clk-programmable", - .data = of_at91rm9200_clk_prog_setup, - }, - { - .compatible = "atmel,at91sam9g45-clk-programmable", - .data = of_at91sam9g45_clk_prog_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-programmable", - .data = of_at91sam9x5_clk_prog_setup, - }, - /* UTMI clock */ -#if defined(CONFIG_HAVE_AT91_UTMI) - { - .compatible = "atmel,at91sam9x5-clk-utmi", - .data = of_at91sam9x5_clk_utmi_setup, - }, -#endif - /* USB clock */ -#if defined(CONFIG_HAVE_AT91_USB_CLK) - { - .compatible = "atmel,at91rm9200-clk-usb", - .data = of_at91rm9200_clk_usb_setup, - }, - { - .compatible = "atmel,at91sam9x5-clk-usb", - .data = of_at91sam9x5_clk_usb_setup, - }, - { - .compatible = "atmel,at91sam9n12-clk-usb", - .data = of_at91sam9n12_clk_usb_setup, - }, -#endif - /* SMD clock */ -#if defined(CONFIG_HAVE_AT91_SMD) - { - .compatible = "atmel,at91sam9x5-clk-smd", - .data = of_at91sam9x5_clk_smd_setup, - }, -#endif -#if defined(CONFIG_HAVE_AT91_H32MX) - { - .compatible = "atmel,sama5d4-clk-h32mx", - .data = of_sama5d4_clk_h32mx_setup, - }, -#endif -#if defined(CONFIG_HAVE_AT91_GENERATED_CLK) - { - .compatible = "atmel,sama5d2-clk-generated", - .data = of_sama5d2_clk_generated_setup, - }, -#endif - { /*sentinel*/ } -}; - -static void __init of_at91_pmc_setup(struct device_node *np, - const struct at91_pmc_caps *caps) -{ - struct at91_pmc *pmc; - struct device_node *childnp; - void (*clk_setup)(struct device_node *, struct at91_pmc *); - const struct of_device_id *clk_id; - void __iomem *regbase = of_iomap(np, 0); - int virq; - - if (!regbase) - return; - - virq = irq_of_parse_and_map(np, 0); - if (!virq) - return; - - pmc = at91_pmc_init(np, regbase, virq, caps); - if (!pmc) - return; - for_each_child_of_node(np, childnp) { - clk_id = of_match_node(pmc_clk_ids, childnp); - if (!clk_id) - continue; - clk_setup = clk_id->data; - clk_setup(childnp, pmc); - } -} - -static void __init of_at91rm9200_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &at91rm9200_caps); -} -CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc", - of_at91rm9200_pmc_setup); - -static void __init of_at91sam9260_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &at91sam9260_caps); -} -CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc", - of_at91sam9260_pmc_setup); - -static void __init of_at91sam9g45_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &at91sam9g45_caps); -} -CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc", - of_at91sam9g45_pmc_setup); - -static void __init of_at91sam9n12_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &at91sam9n12_caps); -} -CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc", - of_at91sam9n12_pmc_setup); - -static void __init of_at91sam9x5_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &at91sam9x5_caps); -} -CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc", - of_at91sam9x5_pmc_setup); - -static void __init of_sama5d2_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &sama5d2_caps); -} -CLK_OF_DECLARE(sama5d2_clk_pmc, "atmel,sama5d2-pmc", - of_sama5d2_pmc_setup); - -static void __init of_sama5d3_pmc_setup(struct device_node *np) -{ - of_at91_pmc_setup(np, &sama5d3_caps); -} -CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc", - of_sama5d3_pmc_setup); diff -Naur --no-dereference a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h --- a/drivers/clk/at91/pmc.h 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/at91/pmc.h 2016-05-11 13:31:53.197225234 -0400 @@ -14,8 +14,11 @@ #include #include +#include #include +extern spinlock_t pmc_pcr_lock; + struct clk_range { unsigned long min; unsigned long max; @@ -23,102 +26,7 @@ #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} -struct at91_pmc_caps { - u32 available_irqs; -}; - -struct at91_pmc { - void __iomem *regbase; - int virq; - spinlock_t lock; - const struct at91_pmc_caps *caps; - struct irq_domain *irqdomain; - u32 imr; -}; - -static inline void pmc_lock(struct at91_pmc *pmc) -{ - spin_lock(&pmc->lock); -} - -static inline void pmc_unlock(struct at91_pmc *pmc) -{ - spin_unlock(&pmc->lock); -} - -static inline u32 pmc_read(struct at91_pmc *pmc, int offset) -{ - return readl(pmc->regbase + offset); -} - -static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value) -{ - writel(value, pmc->regbase + offset); -} - int of_at91_get_clk_range(struct device_node *np, const char *propname, struct clk_range *range); -void of_at91sam9260_clk_slow_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_main_osc_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91rm9200_clk_main_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_main_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9g45_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9g20_clk_pllb_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_sama5d3_clk_pll_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_plldiv_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_master_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_master_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_sys_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_periph_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_periph_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9g45_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_prog_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91sam9x5_clk_utmi_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91rm9200_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9x5_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc); -void of_at91sam9n12_clk_usb_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_at91sam9x5_clk_smd_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_sama5d4_clk_h32mx_setup(struct device_node *np, - struct at91_pmc *pmc); - -void of_sama5d2_clk_generated_setup(struct device_node *np, - struct at91_pmc *pmc); - #endif /* __PMC_H_ */ diff -Naur --no-dereference a/drivers/clk/clk.c b/drivers/clk/clk.c --- a/drivers/clk/clk.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/clk.c 2016-05-11 13:31:53.197225234 -0400 @@ -753,6 +753,76 @@ return 0; } +void clk_dflt_restore_context(struct clk_hw *hw) +{ + if (hw->clk->core->enable_count) + hw->clk->core->ops->enable(hw); + else + hw->clk->core->ops->disable(hw); +} +EXPORT_SYMBOL_GPL(clk_dflt_restore_context); + +static int clk_save_context(struct clk_core *clk) +{ + struct clk_core *child; + int ret = 0; + + hlist_for_each_entry(child, &clk->children, child_node) { + ret = clk_save_context(child); + if (ret < 0) + return ret; + } + + if (clk->ops && clk->ops->save_context) + ret = clk->ops->save_context(clk->hw); + + return ret; +} + +static void clk_restore_context(struct clk_core *clk) +{ + struct clk_core *child; + + if (clk->ops && clk->ops->restore_context) + clk->ops->restore_context(clk->hw); + + hlist_for_each_entry(child, &clk->children, child_node) + clk_restore_context(child); +} + +int clks_save_context(void) +{ + struct clk_core *clk; + int ret; + + hlist_for_each_entry(clk, &clk_root_list, child_node) { + ret = clk_save_context(clk); + if (ret < 0) + return ret; + } + + hlist_for_each_entry(clk, &clk_orphan_list, child_node) { + ret = clk_save_context(clk); + if (ret < 0) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(clks_save_context); + +void clks_restore_context(void) +{ + struct clk_core *clk; + + hlist_for_each_entry(clk, &clk_root_list, child_node) + clk_restore_context(clk); + + hlist_for_each_entry(clk, &clk_orphan_list, child_node) + clk_restore_context(clk); +} +EXPORT_SYMBOL_GPL(clks_restore_context); + /** * clk_enable - ungate a clock * @clk: the clk being ungated @@ -3044,6 +3114,7 @@ { return __of_clk_get_from_provider(clkspec, NULL, __func__); } +EXPORT_SYMBOL_GPL(of_clk_get_from_provider); int of_clk_get_parent_count(struct device_node *np) { diff -Naur --no-dereference a/drivers/clk/Kconfig b/drivers/clk/Kconfig --- a/drivers/clk/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -161,6 +161,19 @@ Supports clock drivers for Keystone based SOCs. These SOCs have local a power sleep control module that gate the clock to the IPs and PLLs. +if COMMON_CLK_KEYSTONE + +config TI_SCI_CLK + tristate "TI System Control Interface clock drivers" + depends on TI_SCI_PROTOCOL || COMPILE_TEST + default y + help + This adds the clock driver support over TI System Control Interface. + If you wish to use clock resources from the PMMC firmware, say Y. + Otherwise, say N. + +endif # COMMON_CLK_KEYSTONE + config COMMON_CLK_PALMAS tristate "Clock driver for TI Palmas devices" depends on MFD_PALMAS diff -Naur --no-dereference a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile --- a/drivers/clk/keystone/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/keystone/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -1 +1,2 @@ obj-y += pll.o gate.o +obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o diff -Naur --no-dereference a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c --- a/drivers/clk/keystone/sci-clk.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/clk/keystone/sci-clk.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,541 @@ +/* + * SCI Clock driver for keystone based devices + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SCI_CLK_SSC_ENABLE BIT(0) +#define SCI_CLK_ALLOW_FREQ_CHANGE BIT(1) +#define SCI_CLK_INPUT_TERMINATION BIT(2) + +/** + * struct sci_clk_provider - TI SCI clock provider representation + * @sci: Handle to the System Control Interface protocol handler + * @ops: Pointer to the SCI ops to be used by the clocks + * @dev: Device pointer for the clock provider + * @clocks: List of all registered clocks + * @lock: Mutex for locking access to the @clocks list + */ +struct sci_clk_provider { + const struct ti_sci_handle *sci; + const struct ti_sci_clk_ops *ops; + struct device *dev; + struct list_head clocks; + struct mutex lock; /* Protects access to the @clocks list */ +}; + +/** + * struct sci_clk - TI SCI clock representation + * @hw: Hardware clock cookie for common clock framework + * @dev_id: Device index + * @clk_id: Clock index + * @node: Clocks list link + * @provider: Master clock provider + * @flags: Flags for the clock + */ +struct sci_clk { + struct clk_hw hw; + u16 dev_id; + u8 clk_id; + struct list_head node; + struct sci_clk_provider *provider; + u8 flags; +}; + +#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw) + +/** + * sci_clk_prepare - Prepare (enable) a TI SCI clock + * @hw: clock to prepare + * + * Prepares a clock to be actively used. Returns the SCI protocol status. + */ +static int sci_clk_prepare(struct clk_hw *hw) +{ + struct sci_clk *clk = to_sci_clk(hw); + bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE; + bool allow_freq_change = clk->flags & SCI_CLK_ALLOW_FREQ_CHANGE; + bool input_termination = clk->flags & SCI_CLK_INPUT_TERMINATION; + + return clk->provider->ops->get_clock(clk->provider->sci, clk->dev_id, + clk->clk_id, enable_ssc, + allow_freq_change, + input_termination); +} + +/** + * sci_clk_unprepare - Un-prepares (disables) a TI SCI clock + * @hw: clock to unprepare + * + * Un-prepares a clock from active state. + */ +static void sci_clk_unprepare(struct clk_hw *hw) +{ + struct sci_clk *clk = to_sci_clk(hw); + int ret; + + ret = clk->provider->ops->put_clock(clk->provider->sci, clk->dev_id, + clk->clk_id); + if (ret) + dev_err(clk->provider->dev, + "unprepare failed for dev=%d, clk=%d, ret=%d\n", + clk->dev_id, clk->clk_id, ret); +} + +/** + * sci_clk_is_prepared - Check if a TI SCI clock is prepared or not + * @hw: clock to check status for + * + * Checks if a clock is prepared (enabled) in hardware. Returns non-zero + * value if clock is enabled, zero otherwise. + */ +static int sci_clk_is_prepared(struct clk_hw *hw) +{ + struct sci_clk *clk = to_sci_clk(hw); + bool req_state, current_state; + int ret; + + ret = clk->provider->ops->is_on(clk->provider->sci, clk->dev_id, + clk->clk_id, &req_state, + ¤t_state); + if (ret) { + dev_err(clk->provider->dev, + "prepare failed for dev=%d, clk=%d, ret=%d\n", + clk->dev_id, clk->clk_id, ret); + return 0; + } + + return req_state; +} + +/** + * sci_clk_recalc_rate - Get clock rate for a TI SCI clock + * @hw: clock to get rate for + * @parent_rate: parent rate provided by common clock framework, not used + * + * Gets the current clock rate of a TI SCI clock. Returns the current + * clock rate, or zero in failure. + */ +static unsigned long sci_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sci_clk *clk = to_sci_clk(hw); + u64 freq; + int ret; + + ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id, + clk->clk_id, &freq); + if (ret) { + dev_err(clk->provider->dev, + "recalc-rate failed for dev=%d, clk=%d, ret=%d\n", + clk->dev_id, clk->clk_id, ret); + return 0; + } + + return (u32)freq; +} + +/** + * sci_clk_determine_rate - Determines a clock rate a clock can be set to + * @hw: clock to change rate for + * @req: requested rate configuration for the clock + * + * Determines a suitable clock rate and parent for a TI SCI clock. + * The parent handling is un-used, as generally the parent clock rates + * are not known by the kernel; instead these are internally handled + * by the firmware. Returns the new clock rate that can be set for the + * clock, or 0 in failure. + */ +static int sci_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct sci_clk *clk = to_sci_clk(hw); + u64 new_rate; + int ret; + + ret = clk->provider->ops->get_best_match_freq(clk->provider->sci, + clk->dev_id, + clk->clk_id, + req->min_rate, + req->rate, + req->max_rate, + &new_rate); + if (ret) { + dev_err(clk->provider->dev, + "determine-rate failed for dev=%d, clk=%d, ret=%d\n", + clk->dev_id, clk->clk_id, ret); + return 0; + } + + return (int)new_rate; +} + +/** + * sci_clk_set_rate - Set rate for a TI SCI clock + * @hw: clock to change rate for + * @rate: target rate for the clock + * @parent_rate: rate of the clock parent, not used for TI SCI clocks + * + * Sets a clock frequency for a TI SCI clock. Returns the TI SCI + * protocol status. + */ +static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct sci_clk *clk = to_sci_clk(hw); + u64 freq = rate; + + return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id, + clk->clk_id, freq, freq, freq); +} + +/** + * sci_clk_get_parent - Get the current parent of a TI SCI clock + * @hw: clock to get parent for + * + * Returns the index of the currently selected parent for a TI SCI clock. + */ +static u8 sci_clk_get_parent(struct clk_hw *hw) +{ + struct sci_clk *clk = to_sci_clk(hw); + u8 parent_id; + int ret; + + ret = clk->provider->ops->get_parent(clk->provider->sci, clk->dev_id, + clk->clk_id, &parent_id); + if (ret) { + dev_err(clk->provider->dev, + "get-parent failed for dev=%d, clk=%d, ret=%d\n", + clk->dev_id, clk->clk_id, ret); + return 0; + } + + parent_id = parent_id - clk->clk_id - 1; + + return parent_id; +} + +/** + * sci_clk_set_parent - Set the parent of a TI SCI clock + * @hw: clock to set parent for + * @index: new parent index for the clock + * + * Sets the parent of a TI SCI clock. Return TI SCI protocol status. + */ +static int sci_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct sci_clk *clk = to_sci_clk(hw); + + return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id, + clk->clk_id, + index + 1 + clk->clk_id); +} + +static const struct clk_ops sci_clk_ops = { + .prepare = sci_clk_prepare, + .unprepare = sci_clk_unprepare, + .is_prepared = sci_clk_is_prepared, + .recalc_rate = sci_clk_recalc_rate, + .determine_rate = sci_clk_determine_rate, + .set_rate = sci_clk_set_rate, + .get_parent = sci_clk_get_parent, + .set_parent = sci_clk_set_parent, +}; + +/** + * _sci_clk_get - Gets a handle for an SCI clock + * @provider: Handle to SCI clock provider + * @dev_id: device ID for the clock to register + * @clk_id: clock ID for the clock to register + * @parse_parents: indicator whether parents for this clock should be handled + * + * Gets a handle to an existing TI SCI clock, or builds a new clock + * entry and registers it with the common clock framework. Called from + * the common clock framework, when a corresponding of_clk_get call is + * executed, or recursively from itself when parsing parent clocks. + * Returns a pointer to the clock struct, or ERR_PTR value in failure. + */ +static struct clk *_sci_clk_get(struct sci_clk_provider *provider, + u16 dev_id, u8 clk_id, bool parse_parents) +{ + struct clk_init_data init = { NULL }; + struct clk *clk; + struct sci_clk *sci_clk = NULL; + char name[20]; + char **parent_names = NULL; + int i; + int ret; + + list_for_each_entry(sci_clk, &provider->clocks, node) + if (sci_clk->dev_id == dev_id && sci_clk->clk_id == clk_id) + return sci_clk->hw.clk; + + sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL); + if (!sci_clk) { + ret = -ENOMEM; + goto err; + } + + sci_clk->dev_id = dev_id; + sci_clk->clk_id = clk_id; + sci_clk->provider = provider; + + if (parse_parents) { + ret = provider->ops->get_num_parents(provider->sci, dev_id, + clk_id, + &init.num_parents); + if (ret) + goto err; + } + + snprintf(name, 20, "%s:%d:%d", dev_name(provider->dev), sci_clk->dev_id, + sci_clk->clk_id); + + init.name = name; + + if (init.num_parents < 2) { + init.num_parents = 0; + init.flags = CLK_IS_ROOT; + } + + if (init.num_parents) { + parent_names = devm_kcalloc(provider->dev, init.num_parents, + sizeof(char *), GFP_KERNEL); + + if (!parent_names) { + ret = -ENOMEM; + goto err; + } + + for (i = 0; i < init.num_parents; i++) { + char *parent_name; + + parent_name = devm_kzalloc(provider->dev, 20, + GFP_KERNEL); + if (!parent_name) { + ret = -ENOMEM; + goto err; + } + snprintf(parent_name, 20, "%s:%d:%d", + dev_name(provider->dev), sci_clk->dev_id, + sci_clk->clk_id + 1 + i); + parent_names[i] = parent_name; + + _sci_clk_get(provider, dev_id, clk_id + 1 + i, false); + } + init.parent_names = (const char * const *)parent_names; + } + + init.ops = &sci_clk_ops; + sci_clk->hw.init = &init; + + clk = devm_clk_register(provider->dev, &sci_clk->hw); + + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err(provider->dev, "failed clk register with %d\n", ret); + goto err; + } else { + list_add(&sci_clk->node, &provider->clocks); + } + + return clk; + +err: + if (parent_names) { + for (i = 0; i < init.num_parents; i++) + devm_kfree(provider->dev, parent_names[i]); + + devm_kfree(provider->dev, parent_names); + } + + devm_kfree(provider->dev, sci_clk); + + return ERR_PTR(ret); +} + +/** + * sci_clk_get - Xlate function for getting clock handles + * @clkspec: device tree clock specifier + * @data: pointer to the clock provider + * + * Xlate function for retrieving clock TI SCI clock handles based on + * device tree clock specifier. Called from the common clock framework, + * when a corresponding of_clk_get call is executed. Returns a pointer + * to the TI SCI clock struct, or ERR_PTR value in failure. + */ +static struct clk *sci_clk_get(struct of_phandle_args *clkspec, void *data) +{ + struct sci_clk_provider *provider = data; + struct clk *clk; + u16 dev_id; + u8 clk_id; + + if (clkspec->args_count != 2) + return ERR_PTR(-EINVAL); + + mutex_lock(&provider->lock); + + dev_id = clkspec->args[0]; + clk_id = clkspec->args[1]; + + clk = _sci_clk_get(provider, dev_id, clk_id, true); + + mutex_unlock(&provider->lock); + + return clk; +} + +static const struct of_device_id ti_sci_clk_of_match[] = { + { .compatible = "ti,sci-clk" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ti_sci_clk_of_match); + +/** + * ti_sci_clk_parse_flags - Helper function to parse clock flag arrays + * @dev: clock provider device + * @np: device node pointer for the clock provider + * @list_name: property name containing the clocks list + * @flag: flag to apply to the list of clocks + * + * Parses a DT list based on the provided data, and applies the flag value + * for each of the clocks identified by the list. Return 0 for success, + * negative error value for failure. + */ +static int ti_sci_clk_parse_flags(struct device *dev, struct device_node *np, + const char *list_name, u8 flag) +{ + int num_clks; + int i; + + num_clks = of_count_phandle_with_args(np, list_name, "#clock-cells"); + + for (i = 0; i < num_clks; i++) { + struct of_phandle_args clkspec; + struct clk_hw *hw; + struct sci_clk *sci_clk; + struct clk *clk; + int ret; + + ret = of_parse_phandle_with_args(np, list_name, "#clock-cells", + i, &clkspec); + if (ret) { + dev_err(dev, "Failed to parse %s[%d] = %d\n", list_name, + i, ret); + return ret; + } + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) { + dev_err(dev, "clk_get failed for %s[%d] = %ld\n", + list_name, i, PTR_ERR(clk)); + return PTR_ERR(clk); + } + hw = __clk_get_hw(clk); + sci_clk = to_sci_clk(hw); + + sci_clk->flags |= flag; + } + + return 0; +} + +/** + * ti_sci_clk_probe - Probe function for the TI SCI clock driver + * @pdev: platform device pointer to be probed + * + * Probes the TI SCI clock device. Allocates a new clock provider + * and registers this to the common clock framework. Also applies + * any required flags to the identified clocks via clock lists + * supplied from DT. Returns 0 for success, negative error value + * for failure. + */ +static int ti_sci_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct sci_clk_provider *provider; + const struct ti_sci_handle *handle; + + if (!np) { + dev_err(dev, "OF data missing\n"); + return -EINVAL; + } + + handle = devm_ti_sci_get_handle(dev); + if (IS_ERR(handle)) + return PTR_ERR(handle); + + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + INIT_LIST_HEAD(&provider->clocks); + mutex_init(&provider->lock); + + provider->sci = handle; + provider->ops = &handle->ops.clk_ops; + provider->dev = dev; + + of_clk_add_provider(np, sci_clk_get, provider); + + ti_sci_clk_parse_flags(dev, np, "ti,ssc-clocks", SCI_CLK_SSC_ENABLE); + ti_sci_clk_parse_flags(dev, np, "ti,allow-freq-change-clocks", + SCI_CLK_ALLOW_FREQ_CHANGE); + ti_sci_clk_parse_flags(dev, np, "ti,input-term-clocks", + SCI_CLK_INPUT_TERMINATION); + + dev_info(dev, "initialized.\n"); + + return 0; +} + +/** + * ti_sci_clk_remove - Remove TI SCI clock device + * @pdev: platform device pointer for the device to be removed + * + * Removes the TI SCI device. Unregisters the clock provider registered + * via common clock framework. Any memory allocated for the device will + * be free'd silently via the devm framework. Returns 0 always. + */ +static int ti_sci_clk_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + + return 0; +} + +static struct platform_driver ti_sci_clk_driver = { + .probe = ti_sci_clk_probe, + .remove = ti_sci_clk_remove, + .driver = { + .name = "ti-sci-clk", + .of_match_table = of_match_ptr(ti_sci_clk_of_match), + }, +}; +module_platform_driver(ti_sci_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TI System Control Interface(SCI) Clock driver"); +MODULE_AUTHOR("Tero Kristo"); +MODULE_ALIAS("platform:ti-sci-clk"); diff -Naur --no-dereference a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c --- a/drivers/clk/ti/clk-43xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/clk-43xx.c 2016-05-11 13:31:53.197225234 -0400 @@ -58,6 +58,7 @@ DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"), DT_CLK(NULL, "sha0_fck", "sha0_fck"), DT_CLK(NULL, "aes0_fck", "aes0_fck"), + DT_CLK(NULL, "rng_fck", "rng_fck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "timer3_fck", "timer3_fck"), diff -Naur --no-dereference a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c --- a/drivers/clk/ti/clk-7xx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/clk-7xx.c 2016-05-11 13:31:53.197225234 -0400 @@ -223,7 +223,7 @@ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), + DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"), DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), diff -Naur --no-dereference a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c --- a/drivers/clk/ti/clk-dra7-atl.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/clk-dra7-atl.c 2016-05-11 13:31:53.197225234 -0400 @@ -265,6 +265,7 @@ /* Get configuration for the ATL instances */ snprintf(prop, sizeof(prop), "atl%u", i); + of_node_get(node); cfg_node = of_find_node_by_name(node, prop); if (cfg_node) { ret = of_property_read_u32(cfg_node, "bws", @@ -278,6 +279,7 @@ atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i), cdesc->aws); } + of_node_put(cfg_node); } cdesc->probed = true; diff -Naur --no-dereference a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c --- a/drivers/clk/ti/clkt_dpll.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/clkt_dpll.c 2016-05-11 13:31:53.197225234 -0400 @@ -301,6 +301,9 @@ dd = clk->dpll_data; + if (dd->max_rate && target_rate > dd->max_rate) + target_rate = dd->max_rate; + ref_rate = clk_get_rate(dd->clk_ref); clk_name = clk_hw_get_name(hw); pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n", diff -Naur --no-dereference a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c --- a/drivers/clk/ti/divider.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/divider.c 2016-05-11 13:31:53.197225234 -0400 @@ -239,10 +239,46 @@ return 0; } +/** + * clk_divider_save_context - Save the divider value + * @hw: pointer struct clk_hw + * + * Save the divider value + */ +static int clk_divider_save_context(struct clk_hw *hw) +{ + struct clk_divider *divider = to_clk_divider(hw); + u32 val; + + val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; + divider->context = val & div_mask(divider); + + return 0; +} + +/** + * clk_divider_restore_context - restore the saved the divider value + * @hw: pointer struct clk_hw + * + * Restore the saved the divider value + */ +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct clk_divider *divider = to_clk_divider(hw); + u32 val; + + val = ti_clk_ll_ops->clk_readl(divider->reg); + val &= ~(div_mask(divider) << divider->shift); + val |= divider->context << divider->shift; + ti_clk_ll_ops->clk_writel(val, divider->reg); +} + const struct clk_ops ti_clk_divider_ops = { .recalc_rate = ti_clk_divider_recalc_rate, .round_rate = ti_clk_divider_round_rate, .set_rate = ti_clk_divider_set_rate, + .save_context = clk_divider_save_context, + .restore_context = clk_divider_restore_context, }; static struct clk *_register_divider(struct device *dev, const char *name, diff -Naur --no-dereference a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c --- a/drivers/clk/ti/dpll3xxx.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/dpll3xxx.c 2016-05-11 13:31:53.197225234 -0400 @@ -305,8 +305,9 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) { struct dpll_data *dd = clk->dpll_data; - u8 dco, sd_div; + u8 dco, sd_div, ai = 0; u32 v; + bool errata_i810; /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ _omap3_noncore_dpll_bypass(clk); @@ -350,6 +351,25 @@ v |= sd_div << __ffs(dd->sddiv_mask); } + /* + * Errata i810 - DPLL controller can get stuck while transitioning + * to a power saving state. Software must ensure the DPLL can not + * transition to a low power state while changing M/N values. + * Easiest way to accomplish this is to prevent DPLL autoidle + * before doing the M/N re-program. + */ + errata_i810 = ti_clk_get_features()->flags & TI_CLK_ERRATA_I810; + + if (errata_i810) { + ai = omap3_dpll_autoidle_read(clk); + if (ai) { + omap3_dpll_deny_idle(clk); + + /* OCP barrier */ + omap3_dpll_autoidle_read(clk); + } + } + ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); /* Set 4X multiplier and low-power mode */ @@ -379,6 +399,9 @@ _omap3_noncore_dpll_lock(clk); + if (errata_i810 && ai) + omap3_dpll_allow_idle(clk); + return 0; } @@ -759,6 +782,130 @@ return rate; } +/** + * omap3_core_dpll_save_context - Save the m and n values of the divider + * @hw: pointer struct clk_hw + * + * Before the dpll registers are lost save the last rounded rate m and n + * and the enable mask. + */ +int omap3_core_dpll_save_context(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + u32 v; + + dd = clk->dpll_data; + + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); + + if (clk->context == DPLL_LOCKED) { + v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + dd->last_rounded_m = (v & dd->mult_mask) >> + __ffs(dd->mult_mask); + dd->last_rounded_n = ((v & dd->div1_mask) >> + __ffs(dd->div1_mask)) + 1; + } + + return 0; +} + +/** + * omap3_core_dpll_restore_context - restore the m and n values of the divider + * @hw: pointer struct clk_hw + * + * Restore the last rounded rate m and n + * and the enable mask. + */ +void omap3_core_dpll_restore_context(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + const struct dpll_data *dd; + u32 v; + + dd = clk->dpll_data; + + if (clk->context == DPLL_LOCKED) { + _omap3_dpll_write_clken(clk, 0x4); + _omap3_wait_dpll_status(clk, 0); + + v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + v &= ~(dd->mult_mask | dd->div1_mask); + v |= dd->last_rounded_m << __ffs(dd->mult_mask); + v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask); + ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); + + _omap3_dpll_write_clken(clk, DPLL_LOCKED); + _omap3_wait_dpll_status(clk, 1); + } else { + _omap3_dpll_write_clken(clk, clk->context); + } +} + +/** + * omap3_non_core_dpll_save_context - Save the m and n values of the divider + * @hw: pointer struct clk_hw + * + * Before the dpll registers are lost save the last rounded rate m and n + * and the enable mask. + */ +int omap3_noncore_dpll_save_context(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd; + u32 v; + + dd = clk->dpll_data; + + v = ti_clk_ll_ops->clk_readl(dd->control_reg); + clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask); + + if (clk->context == DPLL_LOCKED) { + v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + dd->last_rounded_m = (v & dd->mult_mask) >> + __ffs(dd->mult_mask); + dd->last_rounded_n = ((v & dd->div1_mask) >> + __ffs(dd->div1_mask)) + 1; + } + + return 0; +} + +/** + * omap3_core_dpll_restore_context - restore the m and n values of the divider + * @hw: pointer struct clk_hw + * + * Restore the last rounded rate m and n + * and the enable mask. + */ +void omap3_noncore_dpll_restore_context(struct clk_hw *hw) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + const struct dpll_data *dd; + u32 ctrl, mult_div1; + + dd = clk->dpll_data; + + ctrl = ti_clk_ll_ops->clk_readl(dd->control_reg); + mult_div1 = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + + if (clk->context == ((ctrl & dd->enable_mask) >> + __ffs(dd->enable_mask)) && + dd->last_rounded_m == ((mult_div1 & dd->mult_mask) >> + __ffs(dd->mult_mask)) && + dd->last_rounded_n == ((mult_div1 & dd->div1_mask) >> + __ffs(dd->div1_mask)) + 1) { + /* nothing to be done */ + return; + } + + if (clk->context == DPLL_LOCKED) + omap3_noncore_dpll_program(clk, 0); + else + _omap3_dpll_write_clken(clk, clk->context); +} + /* OMAP3/4 non-CORE DPLL clkops */ const struct clk_hw_omap_ops clkhwops_omap3_dpll = { .allow_idle = omap3_dpll_allow_idle, diff -Naur --no-dereference a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c --- a/drivers/clk/ti/dpll.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/dpll.c 2016-05-11 13:31:53.197225234 -0400 @@ -39,6 +39,8 @@ .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap4_dpll_regm4xen_determine_rate, .get_parent = &omap2_init_dpll_parent, + .save_context = &omap3_core_dpll_save_context, + .restore_context = &omap3_core_dpll_restore_context, }; #else static const struct clk_ops dpll_m4xen_ck_ops = {}; @@ -62,6 +64,8 @@ .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, .get_parent = &omap2_init_dpll_parent, + .save_context = &omap3_noncore_dpll_save_context, + .restore_context = &omap3_noncore_dpll_restore_context, }; static const struct clk_ops dpll_no_gate_ck_ops = { @@ -72,6 +76,8 @@ .set_parent = &omap3_noncore_dpll_set_parent, .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, + .save_context = &omap3_noncore_dpll_save_context, + .restore_context = &omap3_noncore_dpll_restore_context }; #else static const struct clk_ops dpll_core_ck_ops = {}; @@ -642,6 +648,7 @@ .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -661,6 +668,7 @@ .max_divider = 256, .min_divider = 2, .flags = DPLL_J_TYPE, + .max_rate = 2000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -679,6 +687,7 @@ .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 2000000000, .flags = DPLL_J_TYPE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -699,6 +708,7 @@ .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -716,6 +726,7 @@ .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; diff -Naur --no-dereference a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c --- a/drivers/clk/ti/gate.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/gate.c 2016-05-11 13:31:53.197225234 -0400 @@ -35,6 +35,7 @@ .init = &omap2_init_clk_clkdm, .enable = &omap2_clkops_enable_clkdm, .disable = &omap2_clkops_disable_clkdm, + .restore_context = clk_dflt_restore_context, }; static const struct clk_ops omap_gate_clk_ops = { @@ -42,6 +43,7 @@ .enable = &omap2_dflt_clk_enable, .disable = &omap2_dflt_clk_disable, .is_enabled = &omap2_dflt_clk_is_enabled, + .restore_context = clk_dflt_restore_context, }; static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = { @@ -49,6 +51,7 @@ .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore, .disable = &omap2_dflt_clk_disable, .is_enabled = &omap2_dflt_clk_is_enabled, + .restore_context = clk_dflt_restore_context, }; /** diff -Naur --no-dereference a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c --- a/drivers/clk/ti/mux.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clk/ti/mux.c 2016-05-11 13:31:53.197225234 -0400 @@ -92,10 +92,40 @@ return 0; } +/** + * clk_mux_save_context - Save the parent selcted in the mux + * @hw: pointer struct clk_hw + * + * Save the parent mux value. + */ +static int clk_mux_save_context(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + + mux->saved_parent = ti_clk_mux_get_parent(hw); + return 0; +} + +/** + * clk_mux_restore_context - Restore the parent in the mux + * @hw: pointer struct clk_hw + * + * Restore the saved parent mux value. + */ +static void clk_mux_restore_context(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + + ti_clk_mux_set_parent(hw, mux->saved_parent); +} + const struct clk_ops ti_clk_mux_ops = { .get_parent = ti_clk_mux_get_parent, .set_parent = ti_clk_mux_set_parent, .determine_rate = __clk_mux_determine_rate, + .save_context = clk_mux_save_context, + .restore_context = clk_mux_restore_context, + }; static struct clk *_register_mux(struct device *dev, const char *name, diff -Naur --no-dereference a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c --- a/drivers/clocksource/arm_global_timer.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clocksource/arm_global_timer.c 2016-05-11 13:31:53.197225234 -0400 @@ -195,12 +195,23 @@ return gt_counter_read(); } +static void gt_resume(struct clocksource *cs) +{ + unsigned long ctrl; + + ctrl = readl(gt_base + GT_CONTROL); + if (!(ctrl & GT_CONTROL_TIMER_ENABLE)) + /* re-enable timer on resume */ + writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); +} + static struct clocksource gt_clocksource = { .name = "arm_global_timer", .rating = 300, .read = gt_clocksource_read, .mask = CLOCKSOURCE_MASK(64), .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .resume = gt_resume, }; #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK diff -Naur --no-dereference a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig --- a/drivers/clocksource/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clocksource/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -159,7 +159,7 @@ hardware anomalies of missing events. config ARM_GLOBAL_TIMER - bool + bool "Support for the ARM global timer unit" select CLKSRC_OF if OF help This options enables support for the ARM global timer unit diff -Naur --no-dereference a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c --- a/drivers/clocksource/tcb_clksrc.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clocksource/tcb_clksrc.c 2016-05-11 13:31:53.197225234 -0400 @@ -23,8 +23,7 @@ * this 32 bit free-running counter. the second channel is not used. * * - The third channel may be used to provide a 16-bit clockevent - * source, used in either periodic or oneshot mode. This runs - * at 32 KiHZ, and can handle delays of up to two seconds. + * source, used in either periodic or oneshot mode. * * A boot clocksource and clockevent source are also currently needed, * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so @@ -74,6 +73,8 @@ struct tc_clkevt_device { struct clock_event_device clkevt; struct clk *clk; + bool clk_enabled; + u32 freq; void __iomem *regs; }; @@ -82,15 +83,26 @@ return container_of(clkevt, struct tc_clkevt_device, clkevt); } -/* For now, we always use the 32K clock ... this optimizes for NO_HZ, - * because using one of the divided clocks would usually mean the - * tick rate can never be less than several dozen Hz (vs 0.5 Hz). - * - * A divided clock could be good for high resolution timers, since - * 30.5 usec resolution can seem "low". - */ static u32 timer_clock; +static void tc_clk_disable(struct clock_event_device *d) +{ + struct tc_clkevt_device *tcd = to_tc_clkevt(d); + + clk_disable(tcd->clk); + tcd->clk_enabled = false; +} + +static void tc_clk_enable(struct clock_event_device *d) +{ + struct tc_clkevt_device *tcd = to_tc_clkevt(d); + + if (tcd->clk_enabled) + return; + clk_enable(tcd->clk); + tcd->clk_enabled = true; +} + static int tc_shutdown(struct clock_event_device *d) { struct tc_clkevt_device *tcd = to_tc_clkevt(d); @@ -98,8 +110,14 @@ __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); + return 0; +} + +static int tc_shutdown_clk_off(struct clock_event_device *d) +{ + tc_shutdown(d); if (!clockevent_state_detached(d)) - clk_disable(tcd->clk); + tc_clk_disable(d); return 0; } @@ -112,9 +130,9 @@ if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) tc_shutdown(d); - clk_enable(tcd->clk); + tc_clk_enable(d); - /* slow clock, count up to RC, then irq and stop */ + /* count up to RC, then irq and stop */ __raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); @@ -134,12 +152,12 @@ /* By not making the gentime core emulate periodic mode on top * of oneshot, we get lower overhead and improved accuracy. */ - clk_enable(tcd->clk); + tc_clk_enable(d); - /* slow clock, count up to RC, then irq and restart */ + /* count up to RC, then irq and restart */ __raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); - __raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); + __raw_writel((tcd->freq + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); /* Enable clock and interrupts on RC compare */ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); @@ -166,9 +184,13 @@ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, /* Should be lower than at91rm9200's system timer */ +#ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK .rating = 125, +#else + .rating = 200, +#endif .set_next_event = tc_next_event, - .set_state_shutdown = tc_shutdown, + .set_state_shutdown = tc_shutdown_clk_off, .set_state_periodic = tc_set_periodic, .set_state_oneshot = tc_set_oneshot, }, @@ -188,8 +210,9 @@ return IRQ_NONE; } -static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx) +static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx) { + unsigned divisor = atmel_tc_divisors[divisor_idx]; int ret; struct clk *t2_clk = tc->clk[2]; int irq = tc->irq[2]; @@ -210,7 +233,11 @@ clkevt.regs = tc->regs; clkevt.clk = t2_clk; - timer_clock = clk32k_divisor_idx; + timer_clock = divisor_idx; + if (!divisor) + clkevt.freq = 32768; + else + clkevt.freq = clk_get_rate(t2_clk) / divisor; clkevt.clkevt.cpumask = cpumask_of(0); @@ -221,7 +248,7 @@ return ret; } - clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff); + clockevents_config_and_register(&clkevt.clkevt, clkevt.freq, 1, 0xffff); return ret; } @@ -358,7 +385,11 @@ goto err_disable_t1; /* channel 2: periodic and oneshot timer support */ +#ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK ret = setup_clkevents(tc, clk32k_divisor_idx); +#else + ret = setup_clkevents(tc, best_divisor_idx); +#endif if (ret) goto err_unregister_clksrc; diff -Naur --no-dereference a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c --- a/drivers/clocksource/timer-atmel-pit.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clocksource/timer-atmel-pit.c 2016-05-11 13:31:53.197225234 -0400 @@ -46,6 +46,7 @@ u32 cycle; u32 cnt; unsigned int irq; + bool irq_requested; struct clk *mck; }; @@ -96,15 +97,29 @@ /* disable irq, leaving the clocksource active */ pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); + if (data->irq_requested) { + free_irq(data->irq, data); + data->irq_requested = false; + } return 0; } +static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id); /* * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) */ static int pit_clkevt_set_periodic(struct clock_event_device *dev) { struct pit_data *data = clkevt_to_pit_data(dev); + int ret; + + ret = request_irq(data->irq, at91sam926x_pit_interrupt, + IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, + "at91_tick", data); + if (ret) + panic(pr_fmt("Unable to setup IRQ\n")); + + data->irq_requested = true; /* update clocksource counter */ data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); @@ -181,7 +196,6 @@ { unsigned long pit_rate; unsigned bits; - int ret; /* * Use our actual MCK to figure out how many MCK/16 ticks per @@ -206,13 +220,6 @@ data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; clocksource_register_hz(&data->clksrc, pit_rate); - /* Set up irq handler */ - ret = request_irq(data->irq, at91sam926x_pit_interrupt, - IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, - "at91_tick", data); - if (ret) - panic(pr_fmt("Unable to setup IRQ\n")); - /* Set up and register clockevents */ data->clkevt.name = "pit"; data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; diff -Naur --no-dereference a/drivers/clocksource/timer-atmel-st.c b/drivers/clocksource/timer-atmel-st.c --- a/drivers/clocksource/timer-atmel-st.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/clocksource/timer-atmel-st.c 2016-05-11 13:31:53.197225234 -0400 @@ -115,18 +115,29 @@ last_crtr = read_CRTR(); } +static int atmel_st_irq; + static int clkevt32k_shutdown(struct clock_event_device *evt) { clkdev32k_disable_and_flush_irq(); irqmask = 0; regmap_write(regmap_st, AT91_ST_IER, irqmask); + free_irq(atmel_st_irq, regmap_st); return 0; } static int clkevt32k_set_oneshot(struct clock_event_device *dev) { + int ret; + clkdev32k_disable_and_flush_irq(); + ret = request_irq(atmel_st_irq, at91rm9200_timer_interrupt, + IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, + "at91_tick", regmap_st); + if (ret) + panic(pr_fmt("Unable to setup IRQ\n")); + /* * ALM for oneshot irqs, set by next_event() * before 32 seconds have passed. @@ -139,8 +150,16 @@ static int clkevt32k_set_periodic(struct clock_event_device *dev) { + int ret; + clkdev32k_disable_and_flush_irq(); + ret = request_irq(atmel_st_irq, at91rm9200_timer_interrupt, + IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, + "at91_tick", regmap_st); + if (ret) + panic(pr_fmt("Unable to setup IRQ\n")); + /* PIT for periodic irqs; fixed rate of 1/HZ */ irqmask = AT91_ST_PITS; regmap_write(regmap_st, AT91_ST_PIMR, timer_latch); @@ -198,7 +217,7 @@ { struct clk *sclk; unsigned int sclk_rate, val; - int irq, ret; + int ret; regmap_st = syscon_node_to_regmap(node); if (IS_ERR(regmap_st)) @@ -210,17 +229,10 @@ regmap_read(regmap_st, AT91_ST_SR, &val); /* Get the interrupts property */ - irq = irq_of_parse_and_map(node, 0); - if (!irq) + atmel_st_irq = irq_of_parse_and_map(node, 0); + if (!atmel_st_irq) panic(pr_fmt("Unable to get IRQ from DT\n")); - /* Make IRQs happen for the system timer */ - ret = request_irq(irq, at91rm9200_timer_interrupt, - IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, - "at91_tick", regmap_st); - if (ret) - panic(pr_fmt("Unable to setup IRQ\n")); - sclk = of_clk_get(node, 0); if (IS_ERR(sclk)) panic(pr_fmt("Unable to get slow clock\n")); diff -Naur --no-dereference a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c --- a/drivers/cpufreq/cpufreq-dt.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/cpufreq/cpufreq-dt.c 2016-05-11 13:31:53.197225234 -0400 @@ -31,9 +31,8 @@ struct private_data { struct device *cpu_dev; - struct regulator *cpu_reg; struct thermal_cooling_device *cdev; - unsigned int voltage_tolerance; /* in percentage */ + const char *reg_name; }; static struct freq_attr *cpufreq_dt_attr[] = { @@ -44,175 +43,128 @@ static int set_target(struct cpufreq_policy *policy, unsigned int index) { - struct dev_pm_opp *opp; - struct cpufreq_frequency_table *freq_table = policy->freq_table; - struct clk *cpu_clk = policy->clk; struct private_data *priv = policy->driver_data; - struct device *cpu_dev = priv->cpu_dev; - struct regulator *cpu_reg = priv->cpu_reg; - unsigned long volt = 0, volt_old = 0, tol = 0; - unsigned int old_freq, new_freq; - long freq_Hz, freq_exact; - int ret; - freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); - if (freq_Hz <= 0) - freq_Hz = freq_table[index].frequency * 1000; - - freq_exact = freq_Hz; - new_freq = freq_Hz / 1000; - old_freq = clk_get_rate(cpu_clk) / 1000; - - if (!IS_ERR(cpu_reg)) { - unsigned long opp_freq; - - rcu_read_lock(); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); - if (IS_ERR(opp)) { - rcu_read_unlock(); - dev_err(cpu_dev, "failed to find OPP for %ld\n", - freq_Hz); - return PTR_ERR(opp); - } - volt = dev_pm_opp_get_voltage(opp); - opp_freq = dev_pm_opp_get_freq(opp); - rcu_read_unlock(); - tol = volt * priv->voltage_tolerance / 100; - volt_old = regulator_get_voltage(cpu_reg); - dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n", - opp_freq / 1000, volt); - } - - dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", - old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1, - new_freq / 1000, volt ? volt / 1000 : -1); - - /* scaling up? scale voltage before frequency */ - if (!IS_ERR(cpu_reg) && new_freq > old_freq) { - ret = regulator_set_voltage_tol(cpu_reg, volt, tol); - if (ret) { - dev_err(cpu_dev, "failed to scale voltage up: %d\n", - ret); - return ret; - } - } + return dev_pm_opp_set_rate(priv->cpu_dev, + policy->freq_table[index].frequency * 1000); +} - ret = clk_set_rate(cpu_clk, freq_exact); - if (ret) { - dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); - if (!IS_ERR(cpu_reg) && volt_old > 0) - regulator_set_voltage_tol(cpu_reg, volt_old, tol); - return ret; - } +/* + * An earlier version of opp-v1 bindings used to name the regulator + * "cpu0-supply", we still need to handle that for backwards compatibility. + */ +static const char *find_supply_name(struct device *dev) +{ + struct device_node *np; + struct property *pp; + int cpu = dev->id; + const char *name = NULL; - /* scaling down? scale voltage after frequency */ - if (!IS_ERR(cpu_reg) && new_freq < old_freq) { - ret = regulator_set_voltage_tol(cpu_reg, volt, tol); - if (ret) { - dev_err(cpu_dev, "failed to scale voltage down: %d\n", - ret); - clk_set_rate(cpu_clk, old_freq * 1000); + np = of_node_get(dev->of_node); + + /* This must be valid for sure */ + if (WARN_ON(!np)) + return NULL; + + /* Try "cpu0" for older DTs */ + if (!cpu) { + pp = of_find_property(np, "cpu0-supply", NULL); + if (pp) { + name = "cpu0"; + goto node_put; } } - return ret; + pp = of_find_property(np, "cpu-supply", NULL); + if (pp) { + name = "cpu"; + goto node_put; + } + + dev_dbg(dev, "no regulator for cpu%d\n", cpu); +node_put: + of_node_put(np); + return name; } -static int allocate_resources(int cpu, struct device **cdev, - struct regulator **creg, struct clk **cclk) +static int resources_available(void) { struct device *cpu_dev; struct regulator *cpu_reg; struct clk *cpu_clk; int ret = 0; - char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg; + const char *name; - cpu_dev = get_cpu_device(cpu); + cpu_dev = get_cpu_device(0); if (!cpu_dev) { - pr_err("failed to get cpu%d device\n", cpu); + pr_err("failed to get cpu0 device\n"); return -ENODEV; } - /* Try "cpu0" for older DTs */ - if (!cpu) - reg = reg_cpu0; - else - reg = reg_cpu; - -try_again: - cpu_reg = regulator_get_optional(cpu_dev, reg); - if (IS_ERR(cpu_reg)) { + cpu_clk = clk_get(cpu_dev, NULL); + ret = PTR_ERR_OR_ZERO(cpu_clk); + if (ret) { /* - * If cpu's regulator supply node is present, but regulator is - * not yet registered, we should try defering probe. + * If cpu's clk node is present, but clock is not yet + * registered, we should try defering probe. */ - if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { - dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n", - cpu); - return -EPROBE_DEFER; - } - - /* Try with "cpu-supply" */ - if (reg == reg_cpu0) { - reg = reg_cpu; - goto try_again; - } + if (ret == -EPROBE_DEFER) + dev_dbg(cpu_dev, "clock not ready, retry\n"); + else + dev_err(cpu_dev, "failed to get clock: %d\n", ret); - dev_dbg(cpu_dev, "no regulator for cpu%d: %ld\n", - cpu, PTR_ERR(cpu_reg)); + return ret; } - cpu_clk = clk_get(cpu_dev, NULL); - if (IS_ERR(cpu_clk)) { - /* put regulator */ - if (!IS_ERR(cpu_reg)) - regulator_put(cpu_reg); + clk_put(cpu_clk); - ret = PTR_ERR(cpu_clk); + name = find_supply_name(cpu_dev); + /* Platform doesn't require regulator */ + if (!name) + return 0; + cpu_reg = regulator_get_optional(cpu_dev, name); + ret = PTR_ERR_OR_ZERO(cpu_reg); + if (ret) { /* - * If cpu's clk node is present, but clock is not yet - * registered, we should try defering probe. + * If cpu's regulator supply node is present, but regulator is + * not yet registered, we should try defering probe. */ if (ret == -EPROBE_DEFER) - dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu); + dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n"); else - dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu, - ret); - } else { - *cdev = cpu_dev; - *creg = cpu_reg; - *cclk = cpu_clk; + dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret); + + return ret; } - return ret; + regulator_put(cpu_reg); + return 0; } static int cpufreq_init(struct cpufreq_policy *policy) { struct cpufreq_frequency_table *freq_table; - struct device_node *np; struct private_data *priv; struct device *cpu_dev; - struct regulator *cpu_reg; struct clk *cpu_clk; struct dev_pm_opp *suspend_opp; - unsigned long min_uV = ~0, max_uV = 0; unsigned int transition_latency; - bool need_update = false; + bool opp_v1 = false; + const char *name; int ret; - ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk); - if (ret) { - pr_err("%s: Failed to allocate resources: %d\n", __func__, ret); - return ret; + cpu_dev = get_cpu_device(policy->cpu); + if (!cpu_dev) { + pr_err("failed to get cpu%d device\n", policy->cpu); + return -ENODEV; } - np = of_node_get(cpu_dev->of_node); - if (!np) { - dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu); - ret = -ENOENT; - goto out_put_reg_clk; + cpu_clk = clk_get(cpu_dev, NULL); + if (IS_ERR(cpu_clk)) { + ret = PTR_ERR(cpu_clk); + dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret); + return ret; } /* Get OPP-sharing information from "operating-points-v2" bindings */ @@ -223,9 +175,23 @@ * finding shared-OPPs for backward compatibility. */ if (ret == -ENOENT) - need_update = true; + opp_v1 = true; else - goto out_node_put; + goto out_put_clk; + } + + /* + * OPP layer will be taking care of regulators now, but it needs to know + * the name of the regulator first. + */ + name = find_supply_name(cpu_dev); + if (name) { + ret = dev_pm_opp_set_regulator(cpu_dev, name); + if (ret) { + dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n", + policy->cpu, ret); + goto out_put_clk; + } } /* @@ -246,12 +212,12 @@ */ ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) { - pr_debug("OPP table is not ready, deferring probe\n"); + dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n"); ret = -EPROBE_DEFER; goto out_free_opp; } - if (need_update) { + if (opp_v1) { struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data(); if (!pd || !pd->independent_clocks) @@ -265,10 +231,6 @@ if (ret) dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n", __func__, ret); - - of_property_read_u32(np, "clock-latency", &transition_latency); - } else { - transition_latency = dev_pm_opp_get_max_clock_latency(cpu_dev); } priv = kzalloc(sizeof(*priv), GFP_KERNEL); @@ -277,62 +239,16 @@ goto out_free_opp; } - of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance); - - if (!transition_latency) - transition_latency = CPUFREQ_ETERNAL; - - if (!IS_ERR(cpu_reg)) { - unsigned long opp_freq = 0; - - /* - * Disable any OPPs where the connected regulator isn't able to - * provide the specified voltage and record minimum and maximum - * voltage levels. - */ - while (1) { - struct dev_pm_opp *opp; - unsigned long opp_uV, tol_uV; - - rcu_read_lock(); - opp = dev_pm_opp_find_freq_ceil(cpu_dev, &opp_freq); - if (IS_ERR(opp)) { - rcu_read_unlock(); - break; - } - opp_uV = dev_pm_opp_get_voltage(opp); - rcu_read_unlock(); - - tol_uV = opp_uV * priv->voltage_tolerance / 100; - if (regulator_is_supported_voltage(cpu_reg, - opp_uV - tol_uV, - opp_uV + tol_uV)) { - if (opp_uV < min_uV) - min_uV = opp_uV; - if (opp_uV > max_uV) - max_uV = opp_uV; - } else { - dev_pm_opp_disable(cpu_dev, opp_freq); - } - - opp_freq++; - } - - ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); - if (ret > 0) - transition_latency += ret * 1000; - } + priv->reg_name = name; ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); if (ret) { - pr_err("failed to init cpufreq table: %d\n", ret); + dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); goto out_free_priv; } priv->cpu_dev = cpu_dev; - priv->cpu_reg = cpu_reg; policy->driver_data = priv; - policy->clk = cpu_clk; rcu_read_lock(); @@ -357,9 +273,11 @@ cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs; } - policy->cpuinfo.transition_latency = transition_latency; + transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); + if (!transition_latency) + transition_latency = CPUFREQ_ETERNAL; - of_node_put(np); + policy->cpuinfo.transition_latency = transition_latency; return 0; @@ -369,12 +287,10 @@ kfree(priv); out_free_opp: dev_pm_opp_of_cpumask_remove_table(policy->cpus); -out_node_put: - of_node_put(np); -out_put_reg_clk: + if (name) + dev_pm_opp_put_regulator(cpu_dev); +out_put_clk: clk_put(cpu_clk); - if (!IS_ERR(cpu_reg)) - regulator_put(cpu_reg); return ret; } @@ -386,9 +302,10 @@ cpufreq_cooling_unregister(priv->cdev); dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); + if (priv->reg_name) + dev_pm_opp_put_regulator(priv->cpu_dev); + clk_put(policy->clk); - if (!IS_ERR(priv->cpu_reg)) - regulator_put(priv->cpu_reg); kfree(priv); return 0; @@ -407,8 +324,13 @@ * thermal DT code takes care of matching them. */ if (of_find_property(np, "#cooling-cells", NULL)) { - priv->cdev = of_cpufreq_cooling_register(np, - policy->related_cpus); + u32 power_coefficient = 0; + + of_property_read_u32(np, "dynamic-power-coefficient", + &power_coefficient); + + priv->cdev = of_cpufreq_power_cooling_register(np, + policy->related_cpus, power_coefficient, NULL); if (IS_ERR(priv->cdev)) { dev_err(priv->cpu_dev, "running cpufreq without cooling device: %ld\n", @@ -436,9 +358,6 @@ static int dt_cpufreq_probe(struct platform_device *pdev) { - struct device *cpu_dev; - struct regulator *cpu_reg; - struct clk *cpu_clk; int ret; /* @@ -448,19 +367,15 @@ * * FIXME: Is checking this only for CPU0 sufficient ? */ - ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk); + ret = resources_available(); if (ret) return ret; - clk_put(cpu_clk); - if (!IS_ERR(cpu_reg)) - regulator_put(cpu_reg); - dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev); ret = cpufreq_register_driver(&dt_cpufreq_driver); if (ret) - dev_err(cpu_dev, "failed register driver: %d\n", ret); + dev_err(&pdev->dev, "failed register driver: %d\n", ret); return ret; } diff -Naur --no-dereference a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 --- a/drivers/cpufreq/Kconfig.x86 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/cpufreq/Kconfig.x86 2016-05-11 13:31:53.197225234 -0400 @@ -123,7 +123,7 @@ config X86_POWERNOW_K8 tristate "AMD Opteron/Athlon64 PowerNow!" - depends on ACPI && ACPI_PROCESSOR && X86_ACPI_CPUFREQ + depends on ACPI && ACPI_PROCESSOR && X86_ACPI_CPUFREQ && !PREEMPT_RT_BASE help This adds the CPUFreq driver for K8/early Opteron/Athlon64 processors. Support for K10 and newer processors is now in acpi-cpufreq. diff -Naur --no-dereference a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c --- a/drivers/cpuidle/coupled.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/cpuidle/coupled.c 2016-05-11 13:31:53.197225234 -0400 @@ -119,7 +119,6 @@ #define CPUIDLE_COUPLED_NOT_IDLE (-1) -static DEFINE_MUTEX(cpuidle_coupled_lock); static DEFINE_PER_CPU(struct call_single_data, cpuidle_coupled_poke_cb); /* diff -Naur --no-dereference a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig --- a/drivers/crypto/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/crypto/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -293,6 +293,10 @@ depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP2PLUS select CRYPTO_AES select CRYPTO_BLKCIPHER + select CRYPTO_AEAD + select CRYPTO_CBC + select CRYPTO_ECB + select CRYPTO_CTR help OMAP processors have AES module accelerator. Select this if you want to use the OMAP module for AES algorithms. diff -Naur --no-dereference a/drivers/crypto/Makefile b/drivers/crypto/Makefile --- a/drivers/crypto/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/crypto/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -14,7 +14,8 @@ obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o n2_crypto-y := n2_core.o n2_asm.o obj-$(CONFIG_CRYPTO_DEV_NX) += nx/ -obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o +obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes-driver.o +omap-aes-driver-objs := omap-aes.o omap-aes-gcm.o obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o diff -Naur --no-dereference a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c --- a/drivers/crypto/omap-aes.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/crypto/omap-aes.c 2016-05-11 13:31:53.197225234 -0400 @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -36,157 +35,9 @@ #include #include #include - -#define DST_MAXBURST 4 -#define DMA_MIN (DST_MAXBURST * sizeof(u32)) - -#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) - -/* OMAP TRM gives bitfields as start:end, where start is the higher bit - number. For example 7:0 */ -#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) -#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) - -#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ - ((x ^ 0x01) * 0x04)) -#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) - -#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) -#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7) -#define AES_REG_CTRL_CTR_WIDTH_32 0 -#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) -#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) -#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7) -#define AES_REG_CTRL_CTR BIT(6) -#define AES_REG_CTRL_CBC BIT(5) -#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3) -#define AES_REG_CTRL_DIRECTION BIT(2) -#define AES_REG_CTRL_INPUT_READY BIT(1) -#define AES_REG_CTRL_OUTPUT_READY BIT(0) -#define AES_REG_CTRL_MASK GENMASK(24, 2) - -#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) - -#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) - -#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) -#define AES_REG_MASK_SIDLE BIT(6) -#define AES_REG_MASK_START BIT(5) -#define AES_REG_MASK_DMA_OUT_EN BIT(3) -#define AES_REG_MASK_DMA_IN_EN BIT(2) -#define AES_REG_MASK_SOFTRESET BIT(1) -#define AES_REG_AUTOIDLE BIT(0) - -#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) - -#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) -#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) -#define AES_REG_IRQ_DATA_IN BIT(1) -#define AES_REG_IRQ_DATA_OUT BIT(2) -#define DEFAULT_TIMEOUT (5*HZ) - -#define FLAGS_MODE_MASK 0x000f -#define FLAGS_ENCRYPT BIT(0) -#define FLAGS_CBC BIT(1) -#define FLAGS_GIV BIT(2) -#define FLAGS_CTR BIT(3) - -#define FLAGS_INIT BIT(4) -#define FLAGS_FAST BIT(5) -#define FLAGS_BUSY BIT(6) - -#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) - -struct omap_aes_ctx { - struct omap_aes_dev *dd; - - int keylen; - u32 key[AES_KEYSIZE_256 / sizeof(u32)]; - unsigned long flags; -}; - -struct omap_aes_reqctx { - unsigned long mode; -}; - -#define OMAP_AES_QUEUE_LENGTH 1 -#define OMAP_AES_CACHE_SIZE 0 - -struct omap_aes_algs_info { - struct crypto_alg *algs_list; - unsigned int size; - unsigned int registered; -}; - -struct omap_aes_pdata { - struct omap_aes_algs_info *algs_info; - unsigned int algs_info_size; - - void (*trigger)(struct omap_aes_dev *dd, int length); - - u32 key_ofs; - u32 iv_ofs; - u32 ctrl_ofs; - u32 data_ofs; - u32 rev_ofs; - u32 mask_ofs; - u32 irq_enable_ofs; - u32 irq_status_ofs; - - u32 dma_enable_in; - u32 dma_enable_out; - u32 dma_start; - - u32 major_mask; - u32 major_shift; - u32 minor_mask; - u32 minor_shift; -}; - -struct omap_aes_dev { - struct list_head list; - unsigned long phys_base; - void __iomem *io_base; - struct omap_aes_ctx *ctx; - struct device *dev; - unsigned long flags; - int err; - - spinlock_t lock; - struct crypto_queue queue; - - struct tasklet_struct done_task; - struct tasklet_struct queue_task; - - struct ablkcipher_request *req; - - /* - * total is used by PIO mode for book keeping so introduce - * variable total_save as need it to calc page_order - */ - size_t total; - size_t total_save; - - struct scatterlist *in_sg; - struct scatterlist *out_sg; - - /* Buffers for copying for unaligned cases */ - struct scatterlist in_sgl; - struct scatterlist out_sgl; - struct scatterlist *orig_out; - int sgs_copied; - - struct scatter_walk in_walk; - struct scatter_walk out_walk; - int dma_in; - struct dma_chan *dma_lch_in; - int dma_out; - struct dma_chan *dma_lch_out; - int in_sg_len; - int out_sg_len; - int pio_only; - const struct omap_aes_pdata *pdata; -}; +#include +#include +#include "omap-aes.h" /* keep registered devices data here */ static LIST_HEAD(dev_list); @@ -202,7 +53,7 @@ _read_ret; \ }) #else -static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) +inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) { return __raw_readl(dd->io_base + offset); } @@ -216,7 +67,7 @@ __raw_writel(value, dd->io_base + offset); \ } while (0) #else -static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, +inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value) { __raw_writel(value, dd->io_base + offset); @@ -251,8 +102,9 @@ return 0; } -static int omap_aes_write_ctrl(struct omap_aes_dev *dd) +int omap_aes_write_ctrl(struct omap_aes_dev *dd) { + struct omap_aes_reqctx *rctx; unsigned int key32; int i, err; u32 val; @@ -263,7 +115,11 @@ key32 = dd->ctx->keylen / sizeof(u32); - /* it seems a key should always be set even if it has not changed */ + /* RESET the key as previous HASH keys should not get affected*/ + if (dd->flags & FLAGS_GCM) + for (i = 0; i < 0x40; i = i + 4) + omap_aes_write(dd, i, 0x0); + for (i = 0; i < key32; i++) { omap_aes_write(dd, AES_REG_KEY(dd, i), __le32_to_cpu(dd->ctx->key[i])); @@ -272,12 +128,21 @@ if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); + if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) { + rctx = aead_request_ctx(dd->aead_req); + omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4); + } + val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); if (dd->flags & FLAGS_CBC) val |= AES_REG_CTRL_CBC; - if (dd->flags & FLAGS_CTR) + + if (dd->flags & (FLAGS_CTR | FLAGS_GCM)) val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128; + if (dd->flags & FLAGS_GCM) + val |= AES_REG_CTRL_GCM; + if (dd->flags & FLAGS_ENCRYPT) val |= AES_REG_CTRL_DIRECTION; @@ -308,6 +173,8 @@ { omap_aes_write(dd, AES_REG_LENGTH_N(0), length); omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); + if (dd->flags & FLAGS_GCM) + omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len); omap_aes_dma_trigger_omap2(dd, length); } @@ -322,22 +189,14 @@ omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); } -static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) +struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) { - struct omap_aes_dev *dd = NULL, *tmp; + struct omap_aes_dev *dd; spin_lock_bh(&list_lock); - if (!ctx->dd) { - list_for_each_entry(tmp, &dev_list, list) { - /* FIXME: take fist available aes core */ - dd = tmp; - break; - } - ctx->dd = dd; - } else { - /* already found before */ - dd = ctx->dd; - } + dd = list_first_entry(&dev_list, struct omap_aes_dev, list); + list_move_tail(&dd->list, &dev_list); + ctx->dd = dd; spin_unlock_bh(&list_lock); return dd; @@ -353,30 +212,21 @@ static int omap_aes_dma_init(struct omap_aes_dev *dd) { - int err = -ENOMEM; - dma_cap_mask_t mask; + int err; dd->dma_lch_out = NULL; dd->dma_lch_in = NULL; - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); - - dd->dma_lch_in = dma_request_slave_channel_compat(mask, - omap_dma_filter_fn, - &dd->dma_in, - dd->dev, "rx"); - if (!dd->dma_lch_in) { + dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); + if (IS_ERR(dd->dma_lch_in)) { dev_err(dd->dev, "Unable to request in DMA channel\n"); - goto err_dma_in; + return PTR_ERR(dd->dma_lch_in); } - dd->dma_lch_out = dma_request_slave_channel_compat(mask, - omap_dma_filter_fn, - &dd->dma_out, - dd->dev, "tx"); - if (!dd->dma_lch_out) { + dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); + if (IS_ERR(dd->dma_lch_out)) { dev_err(dd->dev, "Unable to request out DMA channel\n"); + err = PTR_ERR(dd->dma_lch_out); goto err_dma_out; } @@ -384,14 +234,15 @@ err_dma_out: dma_release_channel(dd->dma_lch_in); -err_dma_in: - if (err) - pr_err("error: %d\n", err); + return err; } static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) { + if (dd->pio_only) + return; + dma_release_channel(dd->dma_lch_out); dma_release_channel(dd->dma_lch_in); } @@ -410,12 +261,11 @@ scatterwalk_done(&walk, out, 0); } -static int omap_aes_crypt_dma(struct crypto_tfm *tfm, - struct scatterlist *in_sg, struct scatterlist *out_sg, - int in_sg_len, int out_sg_len) +static int omap_aes_crypt_dma(struct omap_aes_dev *dd, + struct scatterlist *in_sg, + struct scatterlist *out_sg, + int in_sg_len, int out_sg_len) { - struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); - struct omap_aes_dev *dd = ctx->dd; struct dma_async_tx_descriptor *tx_in, *tx_out; struct dma_slave_config cfg; int ret; @@ -476,7 +326,10 @@ return -EINVAL; } - tx_out->callback = omap_aes_dma_out_callback; + if (dd->flags & FLAGS_GCM) + tx_out->callback = omap_aes_gcm_dma_out_callback; + else + tx_out->callback = omap_aes_dma_out_callback; tx_out->callback_param = dd; dmaengine_submit(tx_in); @@ -491,10 +344,8 @@ return 0; } -static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) +int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) { - struct crypto_tfm *tfm = crypto_ablkcipher_tfm( - crypto_ablkcipher_reqtfm(dd->req)); int err; pr_debug("total: %d\n", dd->total); @@ -515,7 +366,7 @@ } } - err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, + err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len, dd->out_sg_len); if (err && !dd->pio_only) { dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); @@ -537,21 +388,17 @@ req->base.complete(&req->base, err); } -static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) +int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) { - int err = 0; - pr_debug("total: %d\n", dd->total); omap_aes_dma_stop(dd); - dmaengine_terminate_all(dd->dma_lch_in); - dmaengine_terminate_all(dd->dma_lch_out); - return err; + return 0; } -static int omap_aes_check_aligned(struct scatterlist *sg, int total) +int omap_aes_check_aligned(struct scatterlist *sg, int total) { int len = 0; @@ -566,6 +413,9 @@ len += sg->length; sg = sg_next(sg); + + if (len >= total) + break; } if (len != total) @@ -594,9 +444,9 @@ sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0); - sg_init_table(&dd->in_sgl, 1); - sg_set_buf(&dd->in_sgl, buf_in, total); - dd->in_sg = &dd->in_sgl; + sg_init_table(dd->in_sgl, 1); + sg_set_buf(dd->in_sgl, buf_in, total); + dd->in_sg = dd->in_sgl; sg_init_table(&dd->out_sgl, 1); sg_set_buf(&dd->out_sgl, buf_out, total); @@ -665,6 +515,7 @@ ctx->dd = dd; err = omap_aes_write_ctrl(dd); + if (!err) err = omap_aes_crypt_dma_start(dd); if (err) { @@ -694,7 +545,7 @@ } if (dd->sgs_copied) { - buf_in = sg_virt(&dd->in_sgl); + buf_in = sg_virt(dd->in_sgl); buf_out = sg_virt(&dd->out_sgl); sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1); @@ -720,15 +571,28 @@ static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) { + struct crypto_tfm *tfm = + crypto_ablkcipher_tfm(crypto_ablkcipher_reqtfm(req)); struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( crypto_ablkcipher_reqtfm(req)); struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); struct omap_aes_dev *dd; + int ret; pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC)); + if (req->nbytes < 200) { + ablkcipher_request_set_tfm(req, ctx->fallback); + + if (mode & FLAGS_ENCRYPT) + ret = crypto_ablkcipher_encrypt(req); + else + ret = crypto_ablkcipher_decrypt(req); + ablkcipher_request_set_tfm(req, __crypto_ablkcipher_cast(tfm)); + return ret; + } dd = omap_aes_find_dev(ctx); if (!dd) return -ENODEV; @@ -744,6 +608,7 @@ unsigned int keylen) { struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + int ret; if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256) @@ -754,6 +619,14 @@ memcpy(ctx->key, key, keylen); ctx->keylen = keylen; + ctx->fallback->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; + ctx->fallback->base.crt_flags |= + tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK; + + ret = crypto_ablkcipher_setkey(ctx->fallback, key, keylen); + if (!ret) + return 0; + return 0; } @@ -791,38 +664,80 @@ { struct omap_aes_dev *dd = NULL; int err; + const char *name = crypto_tfm_alg_name(tfm); + const u32 flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK; + struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); + struct crypto_ablkcipher *blk; + - /* Find AES device, currently picks the first device */ - spin_lock_bh(&list_lock); list_for_each_entry(dd, &dev_list, list) { - break; + err = pm_runtime_get_sync(dd->dev); + if (err < 0) { + dev_err(dd->dev, "%s: failed to get_sync(%d)\n", + __func__, err); + return err; + } } - spin_unlock_bh(&list_lock); - err = pm_runtime_get_sync(dd->dev); - if (err < 0) { - dev_err(dd->dev, "%s: failed to get_sync(%d)\n", - __func__, err); - return err; - } + blk = crypto_alloc_ablkcipher(name, 0, flags); + if (IS_ERR(blk)) + return PTR_ERR(blk); + + ctx->fallback = blk; tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); return 0; } +static int omap_aes_gcm_cra_init(struct crypto_aead *tfm) +{ + struct omap_aes_dev *dd = NULL; + struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); + int err; + + list_for_each_entry(dd, &dev_list, list) { + err = pm_runtime_get_sync(dd->dev); + if (err < 0) { + dev_err(dd->dev, "%s: failed to get_sync(%d)\n", + __func__, err); + return err; + } + } + + tfm->reqsize = sizeof(struct omap_aes_reqctx); + ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0); + if (IS_ERR(ctx->ctr)) { + pr_warn("could not load aes driver for encrypting IV\n"); + return PTR_ERR(ctx->ctr); + } + + return 0; +} + static void omap_aes_cra_exit(struct crypto_tfm *tfm) { struct omap_aes_dev *dd = NULL; + struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); - /* Find AES device, currently picks the first device */ - spin_lock_bh(&list_lock); list_for_each_entry(dd, &dev_list, list) { - break; + pm_runtime_put_sync(dd->dev); } - spin_unlock_bh(&list_lock); - pm_runtime_put_sync(dd->dev); + if (ctx->fallback) + crypto_free_ablkcipher(ctx->fallback); + + ctx->fallback = NULL; +} + +static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); + + omap_aes_cra_exit(crypto_aead_tfm(tfm)); + + if (ctx->ctr) + crypto_free_skcipher(ctx->ctr); } /* ********************** ALGS ************************************ */ @@ -834,7 +749,7 @@ .cra_priority = 300, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct omap_aes_ctx), .cra_alignmask = 0, @@ -856,7 +771,7 @@ .cra_priority = 300, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct omap_aes_ctx), .cra_alignmask = 0, @@ -882,7 +797,7 @@ .cra_priority = 300, .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | - CRYPTO_ALG_ASYNC, + CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, .cra_blocksize = AES_BLOCK_SIZE, .cra_ctxsize = sizeof(struct omap_aes_ctx), .cra_alignmask = 0, @@ -909,6 +824,54 @@ }, }; +static struct aead_alg algs_aead_gcm[] = { +{ + .base = { + .cra_name = "gcm(aes)", + .cra_driver_name = "gcm-aes-omap", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct omap_aes_ctx), + .cra_alignmask = 0xf, + .cra_module = THIS_MODULE, + }, + .init = omap_aes_gcm_cra_init, + .exit = omap_aes_gcm_cra_exit, + .ivsize = 12, + .maxauthsize = AES_BLOCK_SIZE, + .setkey = omap_aes_gcm_setkey, + .encrypt = omap_aes_gcm_encrypt, + .decrypt = omap_aes_gcm_decrypt, +}, +{ + .base = { + .cra_name = "rfc4106(gcm(aes))", + .cra_driver_name = "rfc4106-gcm-aes-omap", + .cra_priority = 300, + .cra_flags = CRYPTO_ALG_ASYNC | + CRYPTO_ALG_KERN_DRIVER_ONLY, + .cra_blocksize = 1, + .cra_ctxsize = sizeof(struct omap_aes_ctx), + .cra_alignmask = 0xf, + .cra_module = THIS_MODULE, + }, + .init = omap_aes_gcm_cra_init, + .exit = omap_aes_gcm_cra_exit, + .maxauthsize = AES_BLOCK_SIZE, + .ivsize = 8, + .setkey = omap_aes_4106gcm_setkey, + .encrypt = omap_aes_4106gcm_encrypt, + .decrypt = omap_aes_4106gcm_decrypt, +}, +}; + +static struct omap_aes_aead_algs omap_aes_aead_info = { + .algs_list = algs_aead_gcm, + .size = ARRAY_SIZE(algs_aead_gcm), +}; + static const struct omap_aes_pdata omap_aes_pdata_omap2 = { .algs_info = omap_aes_algs_info_ecb_cbc, .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), @@ -962,6 +925,7 @@ static const struct omap_aes_pdata omap_aes_pdata_omap4 = { .algs_info = omap_aes_algs_info_ecb_cbc_ctr, .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), + .aead_algs_info = &omap_aes_aead_info, .trigger = omap_aes_dma_trigger_omap4, .key_ofs = 0x3c, .iv_ofs = 0x40, @@ -1099,9 +1063,6 @@ goto err; } - dd->dma_out = -1; /* Dummy value that's unused */ - dd->dma_in = -1; /* Dummy value that's unused */ - dd->pdata = match->data; err: @@ -1135,24 +1096,6 @@ } memcpy(res, r, sizeof(*res)); - /* Get the DMA out channel */ - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (!r) { - dev_err(dev, "no DMA out resource info\n"); - err = -ENODEV; - goto err; - } - dd->dma_out = r->start; - - /* Get the DMA in channel */ - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (!r) { - dev_err(dev, "no DMA in resource info\n"); - err = -ENODEV; - goto err; - } - dd->dma_in = r->start; - /* Only OMAP2/3 can be non-DT */ dd->pdata = &omap_aes_pdata_omap2; @@ -1165,6 +1108,7 @@ struct device *dev = &pdev->dev; struct omap_aes_dev *dd; struct crypto_alg *algp; + struct aead_alg *aalg; struct resource res; int err = -ENOMEM, i, j, irq = -1; u32 reg; @@ -1179,6 +1123,7 @@ spin_lock_init(&dd->lock); crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH); + aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH); err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : omap_aes_get_res_pdev(dd, pdev, &res); @@ -1214,7 +1159,9 @@ tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd); err = omap_aes_dma_init(dd); - if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { + if (err == -EPROBE_DEFER) { + goto err_irq; + } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) { dd->pio_only = 1; irq = platform_get_irq(pdev, 0); @@ -1238,28 +1185,51 @@ spin_unlock(&list_lock); for (i = 0; i < dd->pdata->algs_info_size; i++) { - for (j = 0; j < dd->pdata->algs_info[i].size; j++) { - algp = &dd->pdata->algs_info[i].algs_list[j]; + if (!dd->pdata->algs_info[i].registered) { + for (j = 0; j < dd->pdata->algs_info[i].size; j++) { + algp = &dd->pdata->algs_info[i].algs_list[j]; + + pr_debug("reg alg: %s\n", algp->cra_name); + INIT_LIST_HEAD(&algp->cra_list); + + err = crypto_register_alg(algp); + if (err) + goto err_algs; + + dd->pdata->algs_info[i].registered++; + } + } + } + + if (!dd->pdata->aead_algs_info->registered) { + for (i = 0; i < dd->pdata->aead_algs_info->size; i++) { + aalg = &dd->pdata->aead_algs_info->algs_list[i]; + algp = &aalg->base; pr_debug("reg alg: %s\n", algp->cra_name); INIT_LIST_HEAD(&algp->cra_list); - err = crypto_register_alg(algp); + err = crypto_register_aead(aalg); if (err) - goto err_algs; + goto err_aead_algs; - dd->pdata->algs_info[i].registered++; + dd->pdata->aead_algs_info->registered++; } } return 0; +err_aead_algs: + for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) { + aalg = &dd->pdata->aead_algs_info->algs_list[i]; + crypto_unregister_aead(aalg); + } err_algs: for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) crypto_unregister_alg( &dd->pdata->algs_info[i].algs_list[j]); - if (!dd->pio_only) - omap_aes_dma_cleanup(dd); + + omap_aes_dma_cleanup(dd); err_irq: tasklet_kill(&dd->done_task); tasklet_kill(&dd->queue_task); @@ -1274,6 +1244,7 @@ static int omap_aes_remove(struct platform_device *pdev) { struct omap_aes_dev *dd = platform_get_drvdata(pdev); + struct aead_alg *aalg; int i, j; if (!dd) @@ -1288,6 +1259,11 @@ crypto_unregister_alg( &dd->pdata->algs_info[i].algs_list[j]); + for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) { + aalg = &dd->pdata->aead_algs_info->algs_list[i]; + crypto_unregister_aead(aalg); + } + tasklet_kill(&dd->done_task); tasklet_kill(&dd->queue_task); omap_aes_dma_cleanup(dd); diff -Naur --no-dereference a/drivers/crypto/omap-aes-gcm.c b/drivers/crypto/omap-aes-gcm.c --- a/drivers/crypto/omap-aes-gcm.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/crypto/omap-aes-gcm.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,433 @@ +/* + * Cryptographic API. + * + * Support for OMAP AES GCM HW acceleration. + * + * Copyright (c) 2016 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "omap-aes.h" + +static int omap_aes_gcm_handle_queue(struct omap_aes_dev *dd, + struct aead_request *req); + +static void omap_aes_gcm_finish_req(struct omap_aes_dev *dd, int ret) +{ + struct aead_request *req = dd->aead_req; + + dd->flags &= ~FLAGS_BUSY; + dd->in_sg = NULL; + dd->out_sg = NULL; + + req->base.complete(&req->base, ret); +} + +static void omap_aes_gcm_done_task(struct omap_aes_dev *dd) +{ + void *buf; + u8 *tag; + int pages, alen, clen, i, ret = 0, nsg; + struct omap_aes_reqctx *rctx; + + alen = ALIGN(dd->assoc_len, AES_BLOCK_SIZE); + clen = ALIGN(dd->total, AES_BLOCK_SIZE); + rctx = aead_request_ctx(dd->aead_req); + + nsg = !!(dd->assoc_len && dd->total); + + dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len, + DMA_FROM_DEVICE); + dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); + dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); + omap_aes_crypt_dma_stop(dd); + + if (dd->sgs_copied & AES_OUT_DATA_COPIED) { + buf = sg_virt(&dd->out_sgl); + scatterwalk_map_and_copy(buf, dd->orig_out, + dd->aead_req->assoclen, dd->total, 1); + + pages = get_order(clen); + free_pages((unsigned long)buf, pages); + } + + if (dd->flags & FLAGS_ENCRYPT) + scatterwalk_map_and_copy(rctx->auth_tag, + dd->aead_req->dst, + dd->total + dd->aead_req->assoclen, + dd->authsize, 1); + + if (dd->sgs_copied & AES_ASSOC_DATA_COPIED) { + buf = sg_virt(&dd->in_sgl[0]); + pages = get_order(alen); + free_pages((unsigned long)buf, pages); + } + if (dd->sgs_copied & AES_IN_DATA_COPIED) { + buf = sg_virt(&dd->in_sgl[nsg]); + pages = get_order(clen); + free_pages((unsigned long)buf, pages); + } + + if (!(dd->flags & FLAGS_ENCRYPT)) { + tag = (u8 *)rctx->auth_tag; + for (i = 0; i < dd->authsize; i++) { + if (tag[i]) { + dev_err(dd->dev, "GCM decryption: Tag Message is wrong\n"); + ret = -EBADMSG; + } + } + } + + omap_aes_gcm_finish_req(dd, ret); + omap_aes_gcm_handle_queue(dd, NULL); +} + +static int omap_aes_gcm_copy_buffers(struct omap_aes_dev *dd, + struct aead_request *req) +{ + void *buf_in; + int pages, alen, clen, cryptlen, nsg, assoclen; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + unsigned int authlen = crypto_aead_authsize(aead); + u32 dec = !(dd->flags & FLAGS_ENCRYPT); + struct scatterlist *input, *assoc, tmp[2]; + + if (dd->flags & FLAGS_RFC4106_GCM) + assoclen = req->assoclen - 8; + else + assoclen = req->assoclen; + alen = ALIGN(assoclen, AES_BLOCK_SIZE); + cryptlen = req->cryptlen - (dec * authlen); + clen = ALIGN(cryptlen, AES_BLOCK_SIZE); + + dd->sgs_copied = 0; + + nsg = !!(assoclen && req->cryptlen); + + assoc = &req->src[0]; + sg_init_table(dd->in_sgl, nsg + 1); + if (assoclen) { + if (omap_aes_check_aligned(assoc, assoclen)) { + dd->sgs_copied |= AES_ASSOC_DATA_COPIED; + pages = get_order(alen); + buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); + if (!buf_in) { + pr_err("Couldn't allocate for unaligncases.\n"); + return -1; + } + + scatterwalk_map_and_copy(buf_in, assoc, 0, + assoclen, 0); + memset(buf_in + assoclen, 0, alen - assoclen); + } else { + buf_in = sg_virt(assoc); + } + sg_set_buf(dd->in_sgl, buf_in, alen); + } + + if (req->cryptlen) { + input = scatterwalk_ffwd(tmp, req->src, req->assoclen); + + if (omap_aes_check_aligned(input, req->cryptlen)) { + dd->sgs_copied |= AES_IN_DATA_COPIED; + pages = get_order(clen); + buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); + if (!buf_in) { + pr_err("Couldn't allocate for unaligncases.\n"); + return -1; + } + + scatterwalk_map_and_copy(buf_in, input, 0, cryptlen, 0); + memset(buf_in + cryptlen, 0, clen - cryptlen); + } else { + buf_in = sg_virt(input); + } + sg_set_buf(&dd->in_sgl[nsg], buf_in, clen); + } + + dd->in_sg = dd->in_sgl; + dd->total = cryptlen; + dd->assoc_len = assoclen; + dd->authsize = authlen; + + if (omap_aes_check_aligned(req->dst, cryptlen + assoclen)) { + pages = get_order(clen); + + buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); + + if (!buf_in) { + pr_err("Couldn't allocate for unaligned cases.\n"); + return -1; + } + + sg_init_one(&dd->out_sgl, buf_in, clen); + dd->out_sg = &dd->out_sgl; + dd->orig_out = req->dst; + dd->sgs_copied |= AES_OUT_DATA_COPIED; + } else { + dd->out_sg = scatterwalk_ffwd(tmp, req->dst, req->assoclen); + } + + dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, alen + clen); + dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, clen); + + return 0; +} + +static void omap_aes_gcm_complete(struct crypto_async_request *req, int err) +{ + struct omap_aes_gcm_result *res = req->data; + + if (err == -EINPROGRESS) + return; + + res->err = err; + complete(&res->completion); +} + +static int do_encrypt_iv(struct aead_request *req, u32 *tag, u32 *iv) +{ + struct scatterlist iv_sg, tag_sg; + struct skcipher_request *sk_req; + struct omap_aes_gcm_result result; + struct omap_aes_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + int ret = 0; + + sk_req = skcipher_request_alloc(ctx->ctr, GFP_KERNEL); + if (!sk_req) { + pr_err("skcipher: Failed to allocate request\n"); + return -1; + } + + init_completion(&result.completion); + + sg_init_one(&iv_sg, iv, AES_BLOCK_SIZE); + sg_init_one(&tag_sg, tag, AES_BLOCK_SIZE); + skcipher_request_set_callback(sk_req, CRYPTO_TFM_REQ_MAY_BACKLOG, + omap_aes_gcm_complete, &result); + ret = crypto_skcipher_setkey(ctx->ctr, (u8 *)ctx->key, ctx->keylen); + skcipher_request_set_crypt(sk_req, &iv_sg, &tag_sg, AES_BLOCK_SIZE, + NULL); + ret = crypto_skcipher_encrypt(sk_req); + switch (ret) { + case 0: + break; + case -EINPROGRESS: + case -EBUSY: + ret = wait_for_completion_interruptible(&result.completion); + if (!ret) { + ret = result.err; + if (!ret) { + reinit_completion(&result.completion); + break; + } + } + /* fall through */ + default: + pr_err("Encryptio of IV failed for GCM mode"); + break; + } + + skcipher_request_free(sk_req); + return ret; +} + +void omap_aes_gcm_dma_out_callback(void *data) +{ + struct omap_aes_dev *dd = data; + struct omap_aes_reqctx *rctx; + int i, val; + u32 *auth_tag, tag[4]; + + if (!(dd->flags & FLAGS_ENCRYPT)) + scatterwalk_map_and_copy(tag, dd->aead_req->src, + dd->total + dd->aead_req->assoclen, + dd->authsize, 0); + + rctx = aead_request_ctx(dd->aead_req); + auth_tag = (u32 *)rctx->auth_tag; + for (i = 0; i < 4; i++) { + val = omap_aes_read(dd, AES_REG_TAG_N(dd, i)); + auth_tag[i] = val ^ auth_tag[i]; + if (!(dd->flags & FLAGS_ENCRYPT)) + auth_tag[i] = auth_tag[i] ^ tag[i]; + } + + omap_aes_gcm_done_task(dd); +} + +static int omap_aes_gcm_handle_queue(struct omap_aes_dev *dd, + struct aead_request *req) +{ + struct omap_aes_ctx *ctx; + struct aead_request *backlog; + struct omap_aes_reqctx *rctx; + unsigned long flags; + int err, ret = 0; + + spin_lock_irqsave(&dd->lock, flags); + if (req) + ret = aead_enqueue_request(&dd->aead_queue, req); + if (dd->flags & FLAGS_BUSY) { + spin_unlock_irqrestore(&dd->lock, flags); + return ret; + } + + backlog = aead_get_backlog(&dd->aead_queue); + req = aead_dequeue_request(&dd->aead_queue); + if (req) + dd->flags |= FLAGS_BUSY; + spin_unlock_irqrestore(&dd->lock, flags); + + if (!req) + return ret; + + if (backlog) + backlog->base.complete(&backlog->base, -EINPROGRESS); + + ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + rctx = aead_request_ctx(req); + + dd->ctx = ctx; + ctx->dd = dd; + dd->aead_req = req; + + rctx->mode &= FLAGS_MODE_MASK; + dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; + + err = omap_aes_gcm_copy_buffers(dd, req); + if (err) + return err; + + err = omap_aes_write_ctrl(dd); + if (!err) + err = omap_aes_crypt_dma_start(dd); + + if (err) { + omap_aes_gcm_finish_req(dd, err); + omap_aes_gcm_handle_queue(dd, NULL); + } + + return ret; +} + +static int omap_aes_gcm_crypt(struct aead_request *req, unsigned long mode) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct omap_aes_reqctx *rctx = aead_request_ctx(req); + struct crypto_aead *aead = crypto_aead_reqtfm(req); + unsigned int authlen = crypto_aead_authsize(aead); + struct omap_aes_dev *dd; + __be32 counter = cpu_to_be32(1); + int err, assoclen; + + memset(rctx->auth_tag, 0, sizeof(rctx->auth_tag)); + memcpy(rctx->iv + 12, &counter, 4); + + err = do_encrypt_iv(req, (u32 *)rctx->auth_tag, (u32 *)rctx->iv); + if (err) + return err; + + if (mode & FLAGS_RFC4106_GCM) + assoclen = req->assoclen - 8; + else + assoclen = req->assoclen; + if (assoclen + req->cryptlen == 0) { + scatterwalk_map_and_copy(rctx->auth_tag, req->dst, 0, authlen, + 1); + return 0; + } + + dd = omap_aes_find_dev(ctx); + if (!dd) + return -ENODEV; + rctx->mode = mode; + + return omap_aes_gcm_handle_queue(dd, req); +} + +int omap_aes_gcm_encrypt(struct aead_request *req) +{ + struct omap_aes_reqctx *rctx = aead_request_ctx(req); + + memcpy(rctx->iv, req->iv, 12); + return omap_aes_gcm_crypt(req, FLAGS_ENCRYPT | FLAGS_GCM); +} + +int omap_aes_gcm_decrypt(struct aead_request *req) +{ + struct omap_aes_reqctx *rctx = aead_request_ctx(req); + + memcpy(rctx->iv, req->iv, 12); + return omap_aes_gcm_crypt(req, FLAGS_GCM); +} + +int omap_aes_4106gcm_encrypt(struct aead_request *req) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct omap_aes_reqctx *rctx = aead_request_ctx(req); + + memcpy(rctx->iv, ctx->nonce, 4); + memcpy(rctx->iv + 4, req->iv, 8); + return omap_aes_gcm_crypt(req, FLAGS_ENCRYPT | FLAGS_GCM | + FLAGS_RFC4106_GCM); +} + +int omap_aes_4106gcm_decrypt(struct aead_request *req) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct omap_aes_reqctx *rctx = aead_request_ctx(req); + + memcpy(rctx->iv, ctx->nonce, 4); + memcpy(rctx->iv + 4, req->iv, 8); + return omap_aes_gcm_crypt(req, FLAGS_GCM | FLAGS_RFC4106_GCM); +} + +int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && + keylen != AES_KEYSIZE_256) + return -EINVAL; + + memcpy(ctx->key, key, keylen); + ctx->keylen = keylen; + + return 0; +} + +int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen) +{ + struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm); + + if (keylen < 4) + return -EINVAL; + + keylen -= 4; + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && + keylen != AES_KEYSIZE_256) + return -EINVAL; + + memcpy(ctx->key, key, keylen); + memcpy(ctx->nonce, key + keylen, 4); + ctx->keylen = keylen; + + return 0; +} diff -Naur --no-dereference a/drivers/crypto/omap-aes.h b/drivers/crypto/omap-aes.h --- a/drivers/crypto/omap-aes.h 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/crypto/omap-aes.h 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,218 @@ +/* + * Cryptographic API. + * + * Support for OMAP AES HW ACCELERATOR defines + * + * Copyright (c) 2015 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ +#ifndef __OMAP_AES_REGS_H__ +#define __OMAP_AES_REGS_H__ + +#define DST_MAXBURST 4 +#define DMA_MIN (DST_MAXBURST * sizeof(u32)) + +#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset) + +#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) + +#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ + ((x ^ 0x01) * 0x04)) +#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) + +#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) +#define AES_REG_CTRL_CONTEXT_READY BIT(31) +#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7) +#define AES_REG_CTRL_CTR_WIDTH_32 0 +#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7) +#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8) +#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7) +#define AES_REG_CTRL_GCM GENMASK(17, 16) +#define AES_REG_CTRL_CTR BIT(6) +#define AES_REG_CTRL_CBC BIT(5) +#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3) +#define AES_REG_CTRL_DIRECTION BIT(2) +#define AES_REG_CTRL_INPUT_READY BIT(1) +#define AES_REG_CTRL_OUTPUT_READY BIT(0) +#define AES_REG_CTRL_MASK GENMASK(24, 2) + +#define AES_REG_C_LEN_0 0x54 +#define AES_REG_C_LEN_1 0x58 +#define AES_REG_A_LEN 0x5C + +#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) +#define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04)) + +#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) + +#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) +#define AES_REG_MASK_SIDLE BIT(6) +#define AES_REG_MASK_START BIT(5) +#define AES_REG_MASK_DMA_OUT_EN BIT(3) +#define AES_REG_MASK_DMA_IN_EN BIT(2) +#define AES_REG_MASK_SOFTRESET BIT(1) +#define AES_REG_AUTOIDLE BIT(0) + +#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) + +#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) +#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) +#define AES_REG_IRQ_DATA_IN BIT(1) +#define AES_REG_IRQ_DATA_OUT BIT(2) +#define DEFAULT_TIMEOUT (5 * HZ) + +#define FLAGS_MODE_MASK 0x001f +#define FLAGS_ENCRYPT BIT(0) +#define FLAGS_CBC BIT(1) +#define FLAGS_CTR BIT(2) +#define FLAGS_GCM BIT(3) +#define FLAGS_RFC4106_GCM BIT(4) + +#define FLAGS_INIT BIT(5) +#define FLAGS_FAST BIT(6) +#define FLAGS_BUSY BIT(7) + +#define AES_ASSOC_DATA_COPIED BIT(0) +#define AES_IN_DATA_COPIED BIT(1) +#define AES_OUT_DATA_COPIED BIT(2) + +#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2) + +struct omap_aes_gcm_result { + struct completion completion; + int err; +}; + +struct omap_aes_ctx { + struct omap_aes_dev *dd; + + int keylen; + u32 key[AES_KEYSIZE_256 / sizeof(u32)]; + u8 nonce[4]; + unsigned long flags; + struct crypto_skcipher *ctr; + struct crypto_ablkcipher *fallback; +}; + +struct omap_aes_reqctx { + unsigned long mode; + u8 iv[AES_BLOCK_SIZE]; + u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)]; +}; + +#define OMAP_AES_QUEUE_LENGTH 10 +#define OMAP_AES_CACHE_SIZE 0 + +struct omap_aes_algs_info { + struct crypto_alg *algs_list; + unsigned int size; + unsigned int registered; +}; + +struct omap_aes_aead_algs { + struct aead_alg *algs_list; + unsigned int size; + unsigned int registered; +}; + +struct omap_aes_pdata { + struct omap_aes_algs_info *algs_info; + unsigned int algs_info_size; + struct omap_aes_aead_algs *aead_algs_info; + + void (*trigger)(struct omap_aes_dev *dd, int length); + + u32 key_ofs; + u32 iv_ofs; + u32 ctrl_ofs; + u32 data_ofs; + u32 rev_ofs; + u32 mask_ofs; + u32 irq_enable_ofs; + u32 irq_status_ofs; + + u32 dma_enable_in; + u32 dma_enable_out; + u32 dma_start; + + u32 major_mask; + u32 major_shift; + u32 minor_mask; + u32 minor_shift; +}; + +struct omap_aes_dev { + struct list_head list; + unsigned long phys_base; + void __iomem *io_base; + struct omap_aes_ctx *ctx; + struct device *dev; + unsigned long flags; + int err; + + /* Lock to acquire omap_aes_dd */ + spinlock_t lock; + struct crypto_queue queue; + struct aead_queue aead_queue; + + struct tasklet_struct done_task; + struct tasklet_struct queue_task; + + struct ablkcipher_request *req; + struct aead_request *aead_req; + + /* + * total is used by PIO mode for book keeping so introduce + * variable total_save as need it to calc page_order + */ + size_t total; + size_t total_save; + size_t assoc_len; + size_t authsize; + + struct scatterlist *in_sg; + struct scatterlist *assoc_sg; + struct scatterlist *out_sg; + + /* Buffers for copying for unaligned cases */ + struct scatterlist in_sgl[2]; + struct scatterlist out_sgl; + struct scatterlist aead_sgl[2]; + struct scatterlist *orig_out; + int sgs_copied; + + struct scatter_walk in_walk; + struct scatter_walk out_walk; + int dma_in; + struct dma_chan *dma_lch_in; + int dma_out; + struct dma_chan *dma_lch_out; + int in_sg_len; + int out_sg_len; + int pio_only; + const struct omap_aes_pdata *pdata; +}; + +u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset); +void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value); +struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx); +int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen); +int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key, + unsigned int keylen); +int omap_aes_gcm_encrypt(struct aead_request *req); +int omap_aes_gcm_decrypt(struct aead_request *req); +int omap_aes_4106gcm_encrypt(struct aead_request *req); +int omap_aes_4106gcm_decrypt(struct aead_request *req); +int omap_aes_write_ctrl(struct omap_aes_dev *dd); +int omap_aes_check_aligned(struct scatterlist *sg, int total); +int omap_aes_crypt_dma_start(struct omap_aes_dev *dd); +void omap_aes_gcm_dma_out_callback(void *data); +int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd); + +#endif diff -Naur --no-dereference a/drivers/crypto/omap-des.c b/drivers/crypto/omap-des.c --- a/drivers/crypto/omap-des.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/crypto/omap-des.c 2016-05-11 13:31:53.197225234 -0400 @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -158,9 +157,7 @@ struct scatter_walk in_walk; struct scatter_walk out_walk; - int dma_in; struct dma_chan *dma_lch_in; - int dma_out; struct dma_chan *dma_lch_out; int in_sg_len; int out_sg_len; @@ -340,30 +337,21 @@ static int omap_des_dma_init(struct omap_des_dev *dd) { - int err = -ENOMEM; - dma_cap_mask_t mask; + int err; dd->dma_lch_out = NULL; dd->dma_lch_in = NULL; - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); - - dd->dma_lch_in = dma_request_slave_channel_compat(mask, - omap_dma_filter_fn, - &dd->dma_in, - dd->dev, "rx"); - if (!dd->dma_lch_in) { + dd->dma_lch_in = dma_request_chan(dd->dev, "rx"); + if (IS_ERR(dd->dma_lch_in)) { dev_err(dd->dev, "Unable to request in DMA channel\n"); - goto err_dma_in; + return PTR_ERR(dd->dma_lch_in); } - dd->dma_lch_out = dma_request_slave_channel_compat(mask, - omap_dma_filter_fn, - &dd->dma_out, - dd->dev, "tx"); - if (!dd->dma_lch_out) { + dd->dma_lch_out = dma_request_chan(dd->dev, "tx"); + if (IS_ERR(dd->dma_lch_out)) { dev_err(dd->dev, "Unable to request out DMA channel\n"); + err = PTR_ERR(dd->dma_lch_out); goto err_dma_out; } @@ -371,14 +359,15 @@ err_dma_out: dma_release_channel(dd->dma_lch_in); -err_dma_in: - if (err) - pr_err("error: %d\n", err); + return err; } static void omap_des_dma_cleanup(struct omap_des_dev *dd) { + if (dd->pio_only) + return; + dma_release_channel(dd->dma_lch_out); dma_release_channel(dd->dma_lch_in); } @@ -527,8 +516,6 @@ static int omap_des_crypt_dma_stop(struct omap_des_dev *dd) { - int err = 0; - pr_debug("total: %d\n", dd->total); omap_des_dma_stop(dd); @@ -536,32 +523,39 @@ dmaengine_terminate_all(dd->dma_lch_in); dmaengine_terminate_all(dd->dma_lch_out); - return err; + return 0; } -static int omap_des_copy_needed(struct scatterlist *sg) +static int omap_des_copy_needed(struct scatterlist *sg, int total) { + int len = 0; + + if (!IS_ALIGNED(total, DES_BLOCK_SIZE)) + return -1; + while (sg) { if (!IS_ALIGNED(sg->offset, 4)) return -1; if (!IS_ALIGNED(sg->length, DES_BLOCK_SIZE)) return -1; + + len += sg->length; sg = sg_next(sg); } + + if (len != total) + return -1; + return 0; } static int omap_des_copy_sgs(struct omap_des_dev *dd) { void *buf_in, *buf_out; - int pages; + int pages, total; - pages = dd->total >> PAGE_SHIFT; - - if (dd->total & (PAGE_SIZE-1)) - pages++; - - BUG_ON(!pages); + total = ALIGN(dd->total, DES_BLOCK_SIZE); + pages = get_order(total); buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages); buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages); @@ -623,8 +617,8 @@ dd->in_sg = req->src; dd->out_sg = req->dst; - if (omap_des_copy_needed(dd->in_sg) || - omap_des_copy_needed(dd->out_sg)) { + if (omap_des_copy_needed(dd->in_sg, dd->total) || + omap_des_copy_needed(dd->out_sg, dd->total)) { if (omap_des_copy_sgs(dd)) pr_err("Failed to copy SGs for unaligned cases\n"); dd->sgs_copied = 1; @@ -1001,8 +995,6 @@ return -EINVAL; } - dd->dma_out = -1; /* Dummy value that's unused */ - dd->dma_in = -1; /* Dummy value that's unused */ dd->pdata = match->data; return 0; @@ -1018,33 +1010,10 @@ static int omap_des_get_pdev(struct omap_des_dev *dd, struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct resource *r; - int err = 0; - - /* Get the DMA out channel */ - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (!r) { - dev_err(dev, "no DMA out resource info\n"); - err = -ENODEV; - goto err; - } - dd->dma_out = r->start; - - /* Get the DMA in channel */ - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (!r) { - dev_err(dev, "no DMA in resource info\n"); - err = -ENODEV; - goto err; - } - dd->dma_in = r->start; - /* non-DT devices get pdata from pdev */ dd->pdata = pdev->dev.platform_data; -err: - return err; + return 0; } static int omap_des_probe(struct platform_device *pdev) @@ -1086,6 +1055,7 @@ dd->phys_base = res->start; pm_runtime_enable(dev); + pm_runtime_irq_safe(dev); err = pm_runtime_get_sync(dev); if (err < 0) { pm_runtime_put_noidle(dev); @@ -1107,7 +1077,9 @@ tasklet_init(&dd->queue_task, omap_des_queue_task, (unsigned long)dd); err = omap_des_dma_init(dd); - if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { + if (err == -EPROBE_DEFER) { + goto err_irq; + } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) { dd->pio_only = 1; irq = platform_get_irq(pdev, 0); @@ -1151,8 +1123,8 @@ for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) crypto_unregister_alg( &dd->pdata->algs_info[i].algs_list[j]); - if (!dd->pio_only) - omap_des_dma_cleanup(dd); + + omap_des_dma_cleanup(dd); err_irq: tasklet_kill(&dd->done_task); tasklet_kill(&dd->queue_task); diff -Naur --no-dereference a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c --- a/drivers/crypto/omap-sham.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/crypto/omap-sham.c 2016-05-11 13:31:53.197225234 -0400 @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -174,7 +173,7 @@ struct omap_sham_hmac_ctx base[0]; }; -#define OMAP_SHAM_QUEUE_LENGTH 1 +#define OMAP_SHAM_QUEUE_LENGTH 10 struct omap_sham_algs_info { struct ahash_alg *algs_list; @@ -219,7 +218,6 @@ int irq; spinlock_t lock; int err; - unsigned int dma; struct dma_chan *dma_lch; struct tasklet_struct done_task; u8 polling_mode; @@ -242,6 +240,8 @@ .lock = __SPIN_LOCK_UNLOCKED(sham.lock), }; +static void omap_sham_done_task(unsigned long data); + static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) { return __raw_readl(dd->io_base + offset); @@ -362,14 +362,6 @@ static int omap_sham_hw_init(struct omap_sham_dev *dd) { - int err; - - err = pm_runtime_get_sync(dd->dev); - if (err < 0) { - dev_err(dd->dev, "failed to get sync: %d\n", err); - return err; - } - if (!test_bit(FLAGS_INIT, &dd->flags)) { set_bit(FLAGS_INIT, &dd->flags); dd->err = 0; @@ -815,7 +807,6 @@ { struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); - dmaengine_terminate_all(dd->dma_lch); if (ctx->flags & BIT(FLAGS_SG)) { dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); @@ -1001,13 +992,11 @@ dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); - pm_runtime_put(dd->dev); - if (req->base.complete) req->base.complete(&req->base, err); /* handle new request */ - tasklet_schedule(&dd->done_task); + omap_sham_done_task((unsigned long)dd); } static int omap_sham_handle_queue(struct omap_sham_dev *dd, @@ -1095,7 +1084,7 @@ ctx->offset = 0; if (ctx->flags & BIT(FLAGS_FINUP)) { - if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) { + if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) { /* * OMAP HW accel works only with buffers >= 9 * will switch to bypass in final() @@ -1151,9 +1140,13 @@ if (ctx->flags & BIT(FLAGS_ERROR)) return 0; /* uncompleted hash is not needed */ - /* OMAP HW accel works only with buffers >= 9 */ - /* HMAC is always >= 9 because ipad == block size */ - if ((ctx->digcnt + ctx->bufcnt) < 9) + /* + * OMAP HW accel works only with buffers >= 9. + * HMAC is always >= 9 because ipad == block size. + * If buffersize is less than 240, we use fallback SW encoding, + * as using DMA + HW in this case doesn't provide any benefit. + */ + if ((ctx->digcnt + ctx->bufcnt) < 240) return omap_sham_final_shash(req); else if (ctx->bufcnt) return omap_sham_enqueue(req, OP_FINAL); @@ -1241,6 +1234,7 @@ { struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); const char *alg_name = crypto_tfm_alg_name(tfm); + struct omap_sham_dev *dd; /* Allocate a fallback and abort if it failed. */ tctx->fallback = crypto_alloc_shash(alg_name, 0, @@ -1268,6 +1262,13 @@ } + spin_lock_bh(&sham.lock); + list_for_each_entry(dd, &sham.dev_list, list) { + break; + } + spin_unlock_bh(&sham.lock); + + pm_runtime_get_sync(dd->dev); return 0; } @@ -1309,6 +1310,7 @@ static void omap_sham_cra_exit(struct crypto_tfm *tfm) { struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); + struct omap_sham_dev *dd; crypto_free_shash(tctx->fallback); tctx->fallback = NULL; @@ -1317,6 +1319,42 @@ struct omap_sham_hmac_ctx *bctx = tctx->base; crypto_free_shash(bctx->shash); } + + spin_lock_bh(&sham.lock); + list_for_each_entry(dd, &sham.dev_list, list) { + break; + } + spin_unlock_bh(&sham.lock); + + pm_runtime_get_sync(dd->dev); +} + +static int omap_sham_export(struct ahash_request *req, void *out) +{ + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct omap_sham_reqctx *rctx = ahash_request_ctx(req); + struct omap_sham_ctx *ctx = crypto_ahash_ctx(tfm); + struct omap_sham_hmac_ctx *bctx = ctx->base; + + memcpy(out, rctx, sizeof(*rctx)); + memcpy(out + sizeof(*rctx), ctx, sizeof(*ctx)); + memcpy(out + sizeof(*rctx) + sizeof(*ctx), bctx, sizeof(*bctx)); + + return 0; +} + +static int omap_sham_import(struct ahash_request *req, const void *in) +{ + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct omap_sham_reqctx *rctx = ahash_request_ctx(req); + struct omap_sham_ctx *ctx = crypto_ahash_ctx(tfm); + struct omap_sham_hmac_ctx *bctx = ctx->base; + + memcpy(rctx, in, sizeof(*rctx)); + memcpy(ctx, in + sizeof(*rctx), sizeof(*ctx)); + memcpy(bctx, in + sizeof(*rctx) + sizeof(*ctx), sizeof(*bctx)); + + return 0; } static struct ahash_alg algs_sha1_md5[] = { @@ -1842,7 +1880,6 @@ goto err; } - dd->dma = -1; /* Dummy value that's unused */ dd->pdata = match->data; err: @@ -1884,15 +1921,6 @@ goto err; } - /* Get the DMA */ - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (!r) { - dev_err(dev, "no DMA resource info\n"); - err = -ENODEV; - goto err; - } - dd->dma = r->start; - /* Only OMAP2/3 can be non-DT */ dd->pdata = &omap_sham_pdata_omap2; @@ -1946,9 +1974,12 @@ dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); - dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn, - &dd->dma, dev, "rx"); - if (!dd->dma_lch) { + dd->dma_lch = dma_request_chan(dev, "rx"); + if (IS_ERR(dd->dma_lch)) { + err = PTR_ERR(dd->dma_lch); + if (err == -EPROBE_DEFER) + goto data_err; + dd->polling_mode = 1; dev_dbg(dev, "using polling mode instead of dma\n"); } @@ -1977,8 +2008,15 @@ for (i = 0; i < dd->pdata->algs_info_size; i++) { for (j = 0; j < dd->pdata->algs_info[i].size; j++) { - err = crypto_register_ahash( - &dd->pdata->algs_info[i].algs_list[j]); + struct ahash_alg *alg; + + alg = &dd->pdata->algs_info[i].algs_list[j]; + alg->export = omap_sham_export; + alg->import = omap_sham_import; + alg->halg.statesize = sizeof(struct omap_sham_reqctx) + + sizeof(struct omap_sham_ctx) + + sizeof(struct omap_sham_hmac_ctx); + err = crypto_register_ahash(alg); if (err) goto err_algs; @@ -1995,7 +2033,7 @@ &dd->pdata->algs_info[i].algs_list[j]); err_pm: pm_runtime_disable(dev); - if (dd->dma_lch) + if (dd->polling_mode) dma_release_channel(dd->dma_lch); data_err: dev_err(dev, "initialization failed.\n"); @@ -2021,7 +2059,7 @@ tasklet_kill(&dd->done_task); pm_runtime_disable(&pdev->dev); - if (dd->dma_lch) + if (!dd->polling_mode) dma_release_channel(dd->dma_lch); return 0; diff -Naur --no-dereference a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/dmaengine.c 2016-05-11 13:31:53.197225234 -0400 @@ -43,6 +43,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -265,8 +266,11 @@ module_put(dma_chan_to_owner(chan)); /* This channel is not in use anymore, free it */ - if (!chan->client_count && chan->device->device_free_chan_resources) + if (!chan->client_count && chan->device->device_free_chan_resources) { + /* Make sure all operations have completed */ + dmaengine_synchronize(chan); chan->device->device_free_chan_resources(chan); + } /* If the channel is used via a DMA request router, free the mapping */ if (chan->router && chan->router->route_free) { @@ -493,6 +497,7 @@ caps->dst_addr_widths = device->dst_addr_widths; caps->directions = device->directions; caps->residue_granularity = device->residue_granularity; + caps->descriptor_reuse = device->descriptor_reuse; /* * Some devices implement only pause (e.g. to get residuum) but no @@ -511,7 +516,7 @@ { struct dma_chan *chan; - if (!__dma_device_satisfies_mask(dev, mask)) { + if (mask && !__dma_device_satisfies_mask(dev, mask)) { pr_debug("%s: wrong capabilities\n", __func__); return NULL; } @@ -542,6 +547,42 @@ return NULL; } +static struct dma_chan *find_candidate(struct dma_device *device, + const dma_cap_mask_t *mask, + dma_filter_fn fn, void *fn_param) +{ + struct dma_chan *chan = private_candidate(mask, device, fn, fn_param); + int err; + + if (chan) { + /* Found a suitable channel, try to grab, prep, and return it. + * We first set DMA_PRIVATE to disable balance_ref_count as this + * channel will not be published in the general-purpose + * allocator + */ + dma_cap_set(DMA_PRIVATE, device->cap_mask); + device->privatecnt++; + err = dma_chan_get(chan); + + if (err) { + if (err == -ENODEV) { + pr_debug("%s: %s module removed\n", __func__, + dma_chan_name(chan)); + list_del_rcu(&device->global_node); + } else + pr_debug("%s: failed to get %s: (%d)\n", + __func__, dma_chan_name(chan), err); + + if (--device->privatecnt == 0) + dma_cap_clear(DMA_PRIVATE, device->cap_mask); + + chan = ERR_PTR(err); + } + } + + return chan ? chan : ERR_PTR(-EPROBE_DEFER); +} + /** * dma_get_slave_channel - try to get specific channel exclusively * @chan: target channel @@ -580,7 +621,6 @@ { dma_cap_mask_t mask; struct dma_chan *chan; - int err; dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); @@ -588,23 +628,11 @@ /* lock against __dma_request_channel */ mutex_lock(&dma_list_mutex); - chan = private_candidate(&mask, device, NULL, NULL); - if (chan) { - dma_cap_set(DMA_PRIVATE, device->cap_mask); - device->privatecnt++; - err = dma_chan_get(chan); - if (err) { - pr_debug("%s: failed to get %s: (%d)\n", - __func__, dma_chan_name(chan), err); - chan = NULL; - if (--device->privatecnt == 0) - dma_cap_clear(DMA_PRIVATE, device->cap_mask); - } - } + chan = find_candidate(device, &mask, NULL, NULL); mutex_unlock(&dma_list_mutex); - return chan; + return IS_ERR(chan) ? NULL : chan; } EXPORT_SYMBOL_GPL(dma_get_any_slave_channel); @@ -621,35 +649,15 @@ { struct dma_device *device, *_d; struct dma_chan *chan = NULL; - int err; /* Find a channel */ mutex_lock(&dma_list_mutex); list_for_each_entry_safe(device, _d, &dma_device_list, global_node) { - chan = private_candidate(mask, device, fn, fn_param); - if (chan) { - /* Found a suitable channel, try to grab, prep, and - * return it. We first set DMA_PRIVATE to disable - * balance_ref_count as this channel will not be - * published in the general-purpose allocator - */ - dma_cap_set(DMA_PRIVATE, device->cap_mask); - device->privatecnt++; - err = dma_chan_get(chan); + chan = find_candidate(device, mask, fn, fn_param); + if (!IS_ERR(chan)) + break; - if (err == -ENODEV) { - pr_debug("%s: %s module removed\n", - __func__, dma_chan_name(chan)); - list_del_rcu(&device->global_node); - } else if (err) - pr_debug("%s: failed to get %s: (%d)\n", - __func__, dma_chan_name(chan), err); - else - break; - if (--device->privatecnt == 0) - dma_cap_clear(DMA_PRIVATE, device->cap_mask); - chan = NULL; - } + chan = NULL; } mutex_unlock(&dma_list_mutex); @@ -662,27 +670,73 @@ } EXPORT_SYMBOL_GPL(__dma_request_channel); +static const struct dma_slave_map *dma_filter_match(struct dma_device *device, + const char *name, + struct device *dev) +{ + int i; + + if (!device->filter.mapcnt) + return NULL; + + for (i = 0; i < device->filter.mapcnt; i++) { + const struct dma_slave_map *map = &device->filter.map[i]; + + if (!strcmp(map->devname, dev_name(dev)) && + !strcmp(map->slave, name)) + return map; + } + + return NULL; +} + /** - * dma_request_slave_channel_reason - try to allocate an exclusive slave channel + * dma_request_chan - try to allocate an exclusive slave channel * @dev: pointer to client device structure * @name: slave channel name * * Returns pointer to appropriate DMA channel on success or an error pointer. */ -struct dma_chan *dma_request_slave_channel_reason(struct device *dev, - const char *name) +struct dma_chan *dma_request_chan(struct device *dev, const char *name) { + struct dma_device *d, *_d; + struct dma_chan *chan = NULL; + /* If device-tree is present get slave info from here */ if (dev->of_node) - return of_dma_request_slave_channel(dev->of_node, name); + chan = of_dma_request_slave_channel(dev->of_node, name); /* If device was enumerated by ACPI get slave info from here */ - if (ACPI_HANDLE(dev)) - return acpi_dma_request_slave_chan_by_name(dev, name); + if (has_acpi_companion(dev) && !chan) + chan = acpi_dma_request_slave_chan_by_name(dev, name); + + if (chan) { + /* Valid channel found or requester need to be deferred */ + if (!IS_ERR(chan) || PTR_ERR(chan) == -EPROBE_DEFER) + return chan; + } + + /* Try to find the channel via the DMA filter map(s) */ + mutex_lock(&dma_list_mutex); + list_for_each_entry_safe(d, _d, &dma_device_list, global_node) { + dma_cap_mask_t mask; + const struct dma_slave_map *map = dma_filter_match(d, name, dev); + + if (!map) + continue; - return ERR_PTR(-ENODEV); + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + chan = find_candidate(d, &mask, d->filter.fn, map->param); + if (!IS_ERR(chan)) + break; + } + mutex_unlock(&dma_list_mutex); + + return chan ? chan : ERR_PTR(-EPROBE_DEFER); } -EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason); +EXPORT_SYMBOL_GPL(dma_request_chan); /** * dma_request_slave_channel - try to allocate an exclusive slave channel @@ -694,17 +748,35 @@ struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name) { - struct dma_chan *ch = dma_request_slave_channel_reason(dev, name); + struct dma_chan *ch = dma_request_chan(dev, name); if (IS_ERR(ch)) return NULL; - dma_cap_set(DMA_PRIVATE, ch->device->cap_mask); - ch->device->privatecnt++; - return ch; } EXPORT_SYMBOL_GPL(dma_request_slave_channel); +/** + * dma_request_chan_by_mask - allocate a channel satisfying certain capabilities + * @mask: capabilities that the channel must satisfy + * + * Returns pointer to appropriate DMA channel on success or an error pointer. + */ +struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask) +{ + struct dma_chan *chan; + + if (!mask) + return ERR_PTR(-ENODEV); + + chan = __dma_request_channel(mask, NULL, NULL); + if (!chan) + chan = ERR_PTR(-ENODEV); + + return chan; +} +EXPORT_SYMBOL_GPL(dma_request_chan_by_mask); + void dma_release_channel(struct dma_chan *chan) { mutex_lock(&dma_list_mutex); diff -Naur --no-dereference a/drivers/dma/edma.c b/drivers/dma/edma.c --- a/drivers/dma/edma.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/edma.c 2016-05-11 13:31:53.197225234 -0400 @@ -113,6 +113,9 @@ #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */ #define CHMAP_EXIST BIT(24) +/* CCSTAT register */ +#define EDMA_CCSTAT_ACTV BIT(4) + /* * Max of 20 segments per channel to conserve PaRAM slots * Also note that MAX_NR_SG should be atleast the no.of periods @@ -484,7 +487,7 @@ */ static int edma_alloc_slot(struct edma_cc *ecc, int slot) { - if (slot > 0) { + if (slot >= 0) { slot = EDMA_CHAN_SLOT(slot); /* Requesting entry paRAM slot for a HW triggered channel. */ if (ecc->chmap_exist && slot < ecc->num_channels) @@ -866,6 +869,13 @@ return 0; } +static void edma_synchronize(struct dma_chan *chan) +{ + struct edma_chan *echan = to_edma_chan(chan); + + vchan_synchronize(&echan->vchan); +} + static int edma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) { @@ -1228,6 +1238,7 @@ struct edma_desc *edesc; dma_addr_t src_addr, dst_addr; enum dma_slave_buswidth dev_width; + bool use_intermediate = false; u32 burst; int i, ret, nslots; @@ -1269,8 +1280,21 @@ * but the synchronization is difficult to achieve with Cyclic and * cannot be guaranteed, so we error out early. */ - if (nslots > MAX_NR_SG) - return NULL; + if (nslots > MAX_NR_SG) { + /* + * If the burst and period sizes are the same, we can put + * the full buffer into a single period and activate + * intermediate interrupts. This will produce interrupts + * after each burst, which is also after each desired period. + */ + if (burst == period_len) { + period_len = buf_len; + nslots = 2; + use_intermediate = true; + } else { + return NULL; + } + } edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]), GFP_ATOMIC); @@ -1348,8 +1372,13 @@ /* * Enable period interrupt only if it is requested */ - if (tx_flags & DMA_PREP_INTERRUPT) + if (tx_flags & DMA_PREP_INTERRUPT) { edesc->pset[i].param.opt |= TCINTEN; + + /* Also enable intermediate interrupts if necessary */ + if (use_intermediate) + edesc->pset[i].param.opt |= ITCINTEN; + } } /* Place the cyclic channel to highest priority queue */ @@ -1362,36 +1391,36 @@ static void edma_completion_handler(struct edma_chan *echan) { struct device *dev = echan->vchan.chan.device->dev; - struct edma_desc *edesc = echan->edesc; - - if (!edesc) - return; + struct edma_desc *edesc; spin_lock(&echan->vchan.lock); - if (edesc->cyclic) { - vchan_cyclic_callback(&edesc->vdesc); - spin_unlock(&echan->vchan.lock); - return; - } else if (edesc->processed == edesc->pset_nr) { - edesc->residue = 0; - edma_stop(echan); - vchan_cookie_complete(&edesc->vdesc); - echan->edesc = NULL; - - dev_dbg(dev, "Transfer completed on channel %d\n", - echan->ch_num); - } else { - dev_dbg(dev, "Sub transfer completed on channel %d\n", - echan->ch_num); - - edma_pause(echan); - - /* Update statistics for tx_status */ - edesc->residue -= edesc->sg_len; - edesc->residue_stat = edesc->residue; - edesc->processed_stat = edesc->processed; + edesc = echan->edesc; + if (edesc) { + if (edesc->cyclic) { + vchan_cyclic_callback(&edesc->vdesc); + spin_unlock(&echan->vchan.lock); + return; + } else if (edesc->processed == edesc->pset_nr) { + edesc->residue = 0; + edma_stop(echan); + vchan_cookie_complete(&edesc->vdesc); + echan->edesc = NULL; + + dev_dbg(dev, "Transfer completed on channel %d\n", + echan->ch_num); + } else { + dev_dbg(dev, "Sub transfer completed on channel %d\n", + echan->ch_num); + + edma_pause(echan); + + /* Update statistics for tx_status */ + edesc->residue -= edesc->sg_len; + edesc->residue_stat = edesc->residue; + edesc->processed_stat = edesc->processed; + } + edma_execute(echan); } - edma_execute(echan); spin_unlock(&echan->vchan.lock); } @@ -1560,32 +1589,6 @@ return IRQ_HANDLED; } -static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable) -{ - struct platform_device *tc_pdev; - int ret; - - if (!IS_ENABLED(CONFIG_OF) || !tc) - return; - - tc_pdev = of_find_device_by_node(tc->node); - if (!tc_pdev) { - pr_err("%s: TPTC device is not found\n", __func__); - return; - } - if (!pm_runtime_enabled(&tc_pdev->dev)) - pm_runtime_enable(&tc_pdev->dev); - - if (enable) - ret = pm_runtime_get_sync(&tc_pdev->dev); - else - ret = pm_runtime_put_sync(&tc_pdev->dev); - - if (ret < 0) - pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__, - enable ? "get" : "put", dev_name(&tc_pdev->dev)); -} - /* Alloc channel resources */ static int edma_alloc_chan_resources(struct dma_chan *chan) { @@ -1622,8 +1625,6 @@ EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, echan->hw_triggered ? "HW" : "SW"); - edma_tc_set_pm_state(echan->tc, true); - return 0; err_slot: @@ -1660,7 +1661,6 @@ echan->alloced = false; } - edma_tc_set_pm_state(echan->tc, false); echan->tc = NULL; echan->hw_triggered = false; @@ -1680,9 +1680,20 @@ spin_unlock_irqrestore(&echan->vchan.lock, flags); } +/* + * This limit exists to avoid a possible infinite loop when waiting for proof + * that a particular transfer is completed. This limit can be hit if there + * are large bursts to/from slow devices or the CPU is never able to catch + * the DMA hardware idle. On an AM335x transfering 48 bytes from the UART + * RX-FIFO, as many as 55 loops have been seen. + */ +#define EDMA_MAX_TR_WAIT_LOOPS 1000 + static u32 edma_residue(struct edma_desc *edesc) { bool dst = edesc->direction == DMA_DEV_TO_MEM; + int loop_count = EDMA_MAX_TR_WAIT_LOOPS; + struct edma_chan *echan = edesc->echan; struct edma_pset *pset = edesc->pset; dma_addr_t done, pos; int i; @@ -1691,7 +1702,32 @@ * We always read the dst/src position from the first RamPar * pset. That's the one which is active now. */ - pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst); + pos = edma_get_position(echan->ecc, echan->slot[0], dst); + + /* + * "pos" may represent a transfer request that is still being + * processed by the EDMACC or EDMATC. We will busy wait until + * any one of the situations occurs: + * 1. the DMA hardware is idle + * 2. a new transfer request is setup + * 3. we hit the loop limit + */ + while (edma_read(echan->ecc, EDMA_CCSTAT) & EDMA_CCSTAT_ACTV) { + /* check if a new transfer request is setup */ + if (edma_get_position(echan->ecc, + echan->slot[0], dst) != pos) { + break; + } + + if (!--loop_count) { + dev_dbg_ratelimited(echan->vchan.chan.device->dev, + "%s: timeout waiting for PaRAM update\n", + __func__); + break; + } + + cpu_relax(); + } /* * Cyclic is simple. Just subtract pset[0].addr from pos. @@ -1798,6 +1834,7 @@ s_ddev->device_pause = edma_dma_pause; s_ddev->device_resume = edma_dma_resume; s_ddev->device_terminate_all = edma_terminate_all; + s_ddev->device_synchronize = edma_synchronize; s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; @@ -1823,6 +1860,7 @@ m_ddev->device_pause = edma_dma_pause; m_ddev->device_resume = edma_dma_resume; m_ddev->device_terminate_all = edma_terminate_all; + m_ddev->device_synchronize = edma_synchronize; m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; @@ -2314,6 +2352,10 @@ edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); } + ecc->dma_slave.filter.map = info->slave_map; + ecc->dma_slave.filter.mapcnt = info->slavecnt; + ecc->dma_slave.filter.fn = edma_filter_fn; + ret = dma_async_device_register(&ecc->dma_slave); if (ret) { dev_err(dev, "slave ddev registration failed (%d)\n", ret); @@ -2365,10 +2407,8 @@ int i; for (i = 0; i < ecc->num_channels; i++) { - if (echan[i].alloced) { + if (echan[i].alloced) edma_setup_interrupt(&echan[i], false); - edma_tc_set_pm_state(echan[i].tc, false); - } } return 0; @@ -2398,8 +2438,6 @@ /* Set up channel -> slot mapping for the entry slot */ edma_set_chmap(&echan[i], echan[i].slot[0]); - - edma_tc_set_pm_state(echan[i].tc, true); } } @@ -2421,7 +2459,14 @@ }, }; +static int edma_tptc_probe(struct platform_device *pdev) +{ + pm_runtime_enable(&pdev->dev); + return pm_runtime_get_sync(&pdev->dev); +} + static struct platform_driver edma_tptc_driver = { + .probe = edma_tptc_probe, .driver = { .name = "edma3-tptc", .of_match_table = edma_tptc_of_ids, diff -Naur --no-dereference a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c --- a/drivers/dma/omap-dma.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/omap-dma.c 2016-05-11 13:31:53.197225234 -0400 @@ -28,8 +28,6 @@ struct omap_dmadev { struct dma_device ddev; spinlock_t lock; - struct tasklet_struct task; - struct list_head pending; void __iomem *base; const struct omap_dma_reg *reg_map; struct omap_system_dma_plat_info *plat; @@ -42,7 +40,6 @@ struct omap_chan { struct virt_dma_chan vc; - struct list_head node; void __iomem *channel_base; const struct omap_dma_reg *reg_map; uint32_t ccr; @@ -51,6 +48,7 @@ unsigned dma_sig; bool cyclic; bool paused; + bool running; int dma_ch; struct omap_desc *desc; @@ -297,6 +295,8 @@ /* Enable channel */ omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); + + c->running = true; } static void omap_dma_stop(struct omap_chan *c) @@ -358,6 +358,8 @@ omap_dma_chan_write(c, CLNK_CTRL, val); } + + c->running = false; } static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, @@ -454,33 +456,6 @@ spin_unlock_irqrestore(&c->vc.lock, flags); } -/* - * This callback schedules all pending channels. We could be more - * clever here by postponing allocation of the real DMA channels to - * this point, and freeing them when our virtual channel becomes idle. - * - * We would then need to deal with 'all channels in-use' - */ -static void omap_dma_sched(unsigned long data) -{ - struct omap_dmadev *d = (struct omap_dmadev *)data; - LIST_HEAD(head); - - spin_lock_irq(&d->lock); - list_splice_tail_init(&d->pending, &head); - spin_unlock_irq(&d->lock); - - while (!list_empty(&head)) { - struct omap_chan *c = list_first_entry(&head, - struct omap_chan, node); - - spin_lock_irq(&c->vc.lock); - list_del_init(&c->node); - omap_dma_start_desc(c); - spin_unlock_irq(&c->vc.lock); - } -} - static irqreturn_t omap_dma_irq(int irq, void *devid) { struct omap_dmadev *od = devid; @@ -706,6 +681,17 @@ unsigned long flags; ret = dma_cookie_status(chan, cookie, txstate); + + if (!c->paused) { + uint32_t ccr = omap_dma_chan_read(c, CCR); + /* + * The channel is no longer active, set the return value + * accordingly + */ + if (!(ccr & CCR_ENABLE)) + ret = DMA_COMPLETE; + } + if (ret == DMA_COMPLETE || !txstate) return ret; @@ -719,7 +705,7 @@ if (d->dir == DMA_MEM_TO_DEV) pos = omap_dma_get_src_pos(c); - else if (d->dir == DMA_DEV_TO_MEM) + else if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) pos = omap_dma_get_dst_pos(c); else pos = 0; @@ -739,22 +725,8 @@ unsigned long flags; spin_lock_irqsave(&c->vc.lock, flags); - if (vchan_issue_pending(&c->vc) && !c->desc) { - /* - * c->cyclic is used only by audio and in this case the DMA need - * to be started without delay. - */ - if (!c->cyclic) { - struct omap_dmadev *d = to_omap_dma_dev(chan->device); - spin_lock(&d->lock); - if (list_empty(&c->node)) - list_add_tail(&c->node, &d->pending); - spin_unlock(&d->lock); - tasklet_schedule(&d->task); - } else { - omap_dma_start_desc(c); - } - } + if (vchan_issue_pending(&c->vc) && !c->desc) + omap_dma_start_desc(c); spin_unlock_irqrestore(&c->vc.lock, flags); } @@ -768,7 +740,7 @@ struct scatterlist *sgent; struct omap_desc *d; dma_addr_t dev_addr; - unsigned i, j = 0, es, en, frame_bytes; + unsigned i, es, en, frame_bytes; u32 burst; if (dir == DMA_DEV_TO_MEM) { @@ -845,13 +817,12 @@ en = burst; frame_bytes = es_bytes[es] * en; for_each_sg(sgl, sgent, sglen, i) { - d->sg[j].addr = sg_dma_address(sgent); - d->sg[j].en = en; - d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; - j++; + d->sg[i].addr = sg_dma_address(sgent); + d->sg[i].en = en; + d->sg[i].fn = sg_dma_len(sgent) / frame_bytes; } - d->sglen = j; + d->sglen = sglen; return vchan_tx_prep(&c->vc, &d->vd, tx_flags); } @@ -1018,17 +989,11 @@ static int omap_dma_terminate_all(struct dma_chan *chan) { struct omap_chan *c = to_omap_dma_chan(chan); - struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); unsigned long flags; LIST_HEAD(head); spin_lock_irqsave(&c->vc.lock, flags); - /* Prevent this channel being scheduled */ - spin_lock(&d->lock); - list_del_init(&c->node); - spin_unlock(&d->lock); - /* * Stop DMA activity: we assume the callback will not be called * after omap_dma_stop() returns (even if it does, it will see @@ -1054,6 +1019,13 @@ return 0; } +static void omap_dma_synchronize(struct dma_chan *chan) +{ + struct omap_chan *c = to_omap_dma_chan(chan); + + vchan_synchronize(&c->vc); +} + static int omap_dma_pause(struct dma_chan *chan) { struct omap_chan *c = to_omap_dma_chan(chan); @@ -1102,14 +1074,12 @@ c->reg_map = od->reg_map; c->vc.desc_free = omap_dma_desc_free; vchan_init(&c->vc, &od->ddev); - INIT_LIST_HEAD(&c->node); return 0; } static void omap_dma_free(struct omap_dmadev *od) { - tasklet_kill(&od->task); while (!list_empty(&od->ddev.channels)) { struct omap_chan *c = list_first_entry(&od->ddev.channels, struct omap_chan, vc.chan.device_node); @@ -1159,18 +1129,16 @@ od->ddev.device_pause = omap_dma_pause; od->ddev.device_resume = omap_dma_resume; od->ddev.device_terminate_all = omap_dma_terminate_all; + od->ddev.device_synchronize = omap_dma_synchronize; od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS; od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS; od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; od->ddev.dev = &pdev->dev; INIT_LIST_HEAD(&od->ddev.channels); - INIT_LIST_HEAD(&od->pending); spin_lock_init(&od->lock); spin_lock_init(&od->irq_lock); - tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); - od->dma_requests = OMAP_SDMA_REQUESTS; if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, "dma-requests", @@ -1203,6 +1171,10 @@ return rc; } + od->ddev.filter.map = od->plat->slave_map; + od->ddev.filter.mapcnt = od->plat->slavecnt; + od->ddev.filter.fn = omap_dma_filter_fn; + rc = dma_async_device_register(&od->ddev); if (rc) { pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", diff -Naur --no-dereference a/drivers/dma/ti-dma-crossbar.c b/drivers/dma/ti-dma-crossbar.c --- a/drivers/dma/ti-dma-crossbar.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/ti-dma-crossbar.c 2016-05-11 13:31:53.197225234 -0400 @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -198,7 +197,8 @@ void __iomem *iomem; struct dma_router dmarouter; - struct idr map_idr; + struct mutex mutex; + unsigned long *dma_inuse; u16 safe_val; /* Value to rest the crossbar lines */ u32 xbar_requests; /* number of DMA requests connected to XBAR */ @@ -225,7 +225,9 @@ map->xbar_in, map->xbar_out); ti_dra7_xbar_write(xbar->iomem, map->xbar_out, xbar->safe_val); - idr_remove(&xbar->map_idr, map->xbar_out); + mutex_lock(&xbar->mutex); + clear_bit(map->xbar_out, xbar->dma_inuse); + mutex_unlock(&xbar->mutex); kfree(map); } @@ -255,8 +257,17 @@ return ERR_PTR(-ENOMEM); } - map->xbar_out = idr_alloc(&xbar->map_idr, NULL, 0, xbar->dma_requests, - GFP_KERNEL); + mutex_lock(&xbar->mutex); + map->xbar_out = find_first_zero_bit(xbar->dma_inuse, + xbar->dma_requests); + mutex_unlock(&xbar->mutex); + if (map->xbar_out == xbar->dma_requests) { + dev_err(&pdev->dev, "Run out of free DMA requests\n"); + kfree(map); + return ERR_PTR(-ENOMEM); + } + set_bit(map->xbar_out, xbar->dma_inuse); + map->xbar_in = (u16)dma_spec->args[0]; dma_spec->args[0] = map->xbar_out + xbar->dma_offset; @@ -278,17 +289,29 @@ .compatible = "ti,edma3", .data = (void *)TI_XBAR_EDMA_OFFSET, }, + { + .compatible = "ti,edma3-tpcc", + .data = (void *)TI_XBAR_EDMA_OFFSET, + }, {}, }; +static inline void ti_dra7_xbar_reserve(int offset, int len, unsigned long *p) +{ + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); +} + static int ti_dra7_xbar_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; const struct of_device_id *match; struct device_node *dma_node; struct ti_dra7_xbar_data *xbar; + struct property *prop; struct resource *res; u32 safe_val; + size_t sz; void __iomem *iomem; int i, ret; @@ -299,8 +322,6 @@ if (!xbar) return -ENOMEM; - idr_init(&xbar->map_idr); - dma_node = of_parse_phandle(node, "dma-masters", 0); if (!dma_node) { dev_err(&pdev->dev, "Can't get DMA master node\n"); @@ -322,6 +343,12 @@ } of_node_put(dma_node); + xbar->dma_inuse = devm_kcalloc(&pdev->dev, + BITS_TO_LONGS(xbar->dma_requests), + sizeof(unsigned long), GFP_KERNEL); + if (!xbar->dma_inuse) + return -ENOMEM; + if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) { dev_info(&pdev->dev, "Missing XBAR input information, using %u.\n", @@ -332,6 +359,33 @@ if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val)) xbar->safe_val = (u16)safe_val; + + prop = of_find_property(node, "ti,reserved-dma-request-ranges", &sz); + if (prop) { + const char pname[] = "ti,reserved-dma-request-ranges"; + u32 (*rsv_events)[2]; + size_t nelm = sz / sizeof(*rsv_events); + int i; + + if (!nelm) + return -EINVAL; + + rsv_events = kcalloc(nelm, sizeof(*rsv_events), GFP_KERNEL); + if (!rsv_events) + return -ENOMEM; + + ret = of_property_read_u32_array(node, pname, (u32 *)rsv_events, + nelm * 2); + if (ret) + return ret; + + for (i = 0; i < nelm; i++) { + ti_dra7_xbar_reserve(rsv_events[i][0], rsv_events[i][1], + xbar->dma_inuse); + } + kfree(rsv_events); + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); iomem = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(iomem)) @@ -343,18 +397,23 @@ xbar->dmarouter.route_free = ti_dra7_xbar_free; xbar->dma_offset = (u32)match->data; + mutex_init(&xbar->mutex); platform_set_drvdata(pdev, xbar); /* Reset the crossbar */ - for (i = 0; i < xbar->dma_requests; i++) - ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val); + for (i = 0; i < xbar->dma_requests; i++) { + if (!test_bit(i, xbar->dma_inuse)) + ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val); + } ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate, &xbar->dmarouter); if (ret) { /* Restore the defaults for the crossbar */ - for (i = 0; i < xbar->dma_requests; i++) - ti_dra7_xbar_write(xbar->iomem, i, i); + for (i = 0; i < xbar->dma_requests; i++) { + if (!test_bit(i, xbar->dma_inuse)) + ti_dra7_xbar_write(xbar->iomem, i, i); + } } return ret; diff -Naur --no-dereference a/drivers/dma/virt-dma.c b/drivers/dma/virt-dma.c --- a/drivers/dma/virt-dma.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/virt-dma.c 2016-05-11 13:31:53.197225234 -0400 @@ -29,7 +29,7 @@ spin_lock_irqsave(&vc->lock, flags); cookie = dma_cookie_assign(tx); - list_add_tail(&vd->node, &vc->desc_submitted); + list_move_tail(&vd->node, &vc->desc_submitted); spin_unlock_irqrestore(&vc->lock, flags); dev_dbg(vc->chan.device->dev, "vchan %p: txd %p[%x]: submitted\n", @@ -39,6 +39,33 @@ } EXPORT_SYMBOL_GPL(vchan_tx_submit); +/** + * vchan_tx_desc_free - free a reusable descriptor + * @tx: the transfer + * + * This function frees a previously allocated reusable descriptor. The only + * other way is to clear the DMA_CTRL_REUSE flag and submit one last time the + * transfer. + * + * Returns 0 upon success + */ +int vchan_tx_desc_free(struct dma_async_tx_descriptor *tx) +{ + struct virt_dma_chan *vc = to_virt_chan(tx->chan); + struct virt_dma_desc *vd = to_virt_desc(tx); + unsigned long flags; + + spin_lock_irqsave(&vc->lock, flags); + list_del(&vd->node); + spin_unlock_irqrestore(&vc->lock, flags); + + dev_dbg(vc->chan.device->dev, "vchan %p: txd %p[%x]: freeing\n", + vc, vd, vd->tx.cookie); + vc->desc_free(vd); + return 0; +} +EXPORT_SYMBOL_GPL(vchan_tx_desc_free); + struct virt_dma_desc *vchan_find_desc(struct virt_dma_chan *vc, dma_cookie_t cookie) { @@ -83,8 +110,10 @@ cb_data = vd->tx.callback_param; list_del(&vd->node); - - vc->desc_free(vd); + if (dmaengine_desc_test_reuse(&vd->tx)) + list_add(&vd->node, &vc->desc_allocated); + else + vc->desc_free(vd); if (cb) cb(cb_data); @@ -96,9 +125,13 @@ while (!list_empty(head)) { struct virt_dma_desc *vd = list_first_entry(head, struct virt_dma_desc, node); - list_del(&vd->node); - dev_dbg(vc->chan.device->dev, "txd %p: freeing\n", vd); - vc->desc_free(vd); + if (dmaengine_desc_test_reuse(&vd->tx)) { + list_move_tail(&vd->node, &vc->desc_allocated); + } else { + dev_dbg(vc->chan.device->dev, "txd %p: freeing\n", vd); + list_del(&vd->node); + vc->desc_free(vd); + } } } EXPORT_SYMBOL_GPL(vchan_dma_desc_free_list); @@ -108,6 +141,7 @@ dma_cookie_init(&vc->chan); spin_lock_init(&vc->lock); + INIT_LIST_HEAD(&vc->desc_allocated); INIT_LIST_HEAD(&vc->desc_submitted); INIT_LIST_HEAD(&vc->desc_issued); INIT_LIST_HEAD(&vc->desc_completed); diff -Naur --no-dereference a/drivers/dma/virt-dma.h b/drivers/dma/virt-dma.h --- a/drivers/dma/virt-dma.h 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/dma/virt-dma.h 2016-05-11 13:31:53.197225234 -0400 @@ -29,6 +29,7 @@ spinlock_t lock; /* protected by vc.lock */ + struct list_head desc_allocated; struct list_head desc_submitted; struct list_head desc_issued; struct list_head desc_completed; @@ -55,10 +56,17 @@ struct virt_dma_desc *vd, unsigned long tx_flags) { extern dma_cookie_t vchan_tx_submit(struct dma_async_tx_descriptor *); + extern int vchan_tx_desc_free(struct dma_async_tx_descriptor *); + unsigned long flags; dma_async_tx_descriptor_init(&vd->tx, &vc->chan); vd->tx.flags = tx_flags; vd->tx.tx_submit = vchan_tx_submit; + vd->tx.desc_free = vchan_tx_desc_free; + + spin_lock_irqsave(&vc->lock, flags); + list_add_tail(&vd->node, &vc->desc_allocated); + spin_unlock_irqrestore(&vc->lock, flags); return &vd->tx; } @@ -134,6 +142,7 @@ static inline void vchan_get_all_descriptors(struct virt_dma_chan *vc, struct list_head *head) { + list_splice_tail_init(&vc->desc_allocated, head); list_splice_tail_init(&vc->desc_submitted, head); list_splice_tail_init(&vc->desc_issued, head); list_splice_tail_init(&vc->desc_completed, head); @@ -141,14 +150,30 @@ static inline void vchan_free_chan_resources(struct virt_dma_chan *vc) { + struct virt_dma_desc *vd; unsigned long flags; LIST_HEAD(head); spin_lock_irqsave(&vc->lock, flags); vchan_get_all_descriptors(vc, &head); + list_for_each_entry(vd, &head, node) + dmaengine_desc_clear_reuse(&vd->tx); spin_unlock_irqrestore(&vc->lock, flags); vchan_dma_desc_free_list(vc, &head); } +/** + * vchan_synchronize() - synchronize callback execution to the current context + * @vc: virtual channel to synchronize + * + * Makes sure that all scheduled or active callbacks have finished running. For + * proper operation the caller has to ensure that no new callbacks are scheduled + * after the invocation of this function started. + */ +static inline void vchan_synchronize(struct virt_dma_chan *vc) +{ + tasklet_kill(&vc->task); +} + #endif diff -Naur --no-dereference a/drivers/edac/Kconfig b/drivers/edac/Kconfig --- a/drivers/edac/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/edac/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -390,4 +390,12 @@ Support for error detection and correction on the APM X-Gene family of SOCs. +config EDAC_KEYSTONE_MC + bool "Keystone DDR3 MC ECC handler" + depends on ARCH_KEYSTONE + help + Support for double bit error detection by DDR3 Memory + controller. This is a simple handler that can panic on double + bit error. + endif # EDAC diff -Naur --no-dereference a/drivers/edac/keystone_mc_edac.c b/drivers/edac/keystone_mc_edac.c --- a/drivers/edac/keystone_mc_edac.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/edac/keystone_mc_edac.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Keystone DDR3 MC ECC error detection driver + * + * TODO: Need to investgiate how to hook this to the edac core driver. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include + +/* DDR3 controller registers */ +#define DDR3_EOI 0x0A0 +#define DDR3_IRQ_STATUS_RAW_SYS 0x0A4 +#define DDR3_IRQ_STATUS_SYS 0x0AC +#define DDR3_IRQ_ENABLE_SET_SYS 0x0B4 +#define DDR3_IRQ_ENABLE_CLR_SYS 0x0BC +#define DDR3_ECC_CTRL 0x110 +#define DDR3_ONE_BIT_ECC_ERR_CNT 0x130 +#define TWO_BIT_ECC_ERR_ADDR_LOG 0x140 + +#define DDR3_1B_ECC_ERR BIT(5) +#define DDR3_2B_ECC_ERR BIT(4) +#define DDR3_WR_ECC_ERR BIT(3) +#define DDR3_SYS_ERR BIT(0) +/* Bit 31 enables ECC and 28 enables RMW */ +#define ECC_ENABLED (BIT(31) | BIT(28)) + +static void ks2_mc_ddr3_ecc_check(void __iomem *reg) +{ + u32 irq_status; + + irq_status = readl(reg + DDR3_IRQ_STATUS_SYS); + if ((irq_status & DDR3_2B_ECC_ERR) || + (irq_status & DDR3_WR_ECC_ERR)) { + /* + * Do a kernel panic as this is double bit ECC error + * or ECC write that are fatal + */ + if (irq_status & DDR3_2B_ECC_ERR) + panic("UC DDR3 ECC err, irq stats 0x%x, addr 0x%x..\n", + irq_status, + readl(reg + TWO_BIT_ECC_ERR_ADDR_LOG)); + else + panic("UC DDR3 ECC err, irq stats 0x%x..\n", + irq_status); + } +} + +static irqreturn_t ks2_mc_ddr3_ecc_isr(int irq, void *reg_virt) +{ + void __iomem *reg = (void __iomem *)reg_virt; + + ks2_mc_ddr3_ecc_check(reg); + + /* + * Other errors should be handled by hardware + * So, nothing to do here. For now it never reaches here + * as panic will be triggerred for ECC errors + */ + return IRQ_HANDLED; +} + +static const struct of_device_id ks2_mc_ddr3_ecc_of_match[] = { + {.compatible = "ti,keystone-ddr3-mc-edac", }, + {}, +}; + +static int ks2_mc_ddr3_ecc_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int error_irq = 0, ret = -ENODEV; + struct device *dev = &pdev->dev; + struct resource res; + void __iomem *reg; + u32 val; + + if (of_address_to_resource(np, 0, &res) < 0) { + dev_err(dev, "no edac resource address\n"); + return ret; + } + + reg = devm_ioremap_resource(dev, &res); + if (IS_ERR(reg)) { + dev_err(dev, + "DDR3 controller regs not defined\n"); + return PTR_ERR(reg); + } + + /* Check if ECC is enabled. If not, just return */ + val = readl(reg + DDR3_ECC_CTRL); + if (!(val & ECC_ENABLED)) { + dev_info(&pdev->dev, "ECC is not enabled, disable edac\n"); + return ret; + } + + /* disable and clear unused ECC interrupts */ + writel(DDR3_1B_ECC_ERR | DDR3_SYS_ERR, reg + DDR3_IRQ_ENABLE_CLR_SYS); + writel(DDR3_1B_ECC_ERR | DDR3_SYS_ERR, reg + DDR3_IRQ_STATUS_SYS); + + /* check if we already have unrecoverable errors */ + ks2_mc_ddr3_ecc_check(reg); + + writel(DDR3_2B_ECC_ERR | DDR3_WR_ECC_ERR, + reg + DDR3_IRQ_ENABLE_CLR_SYS); + + /* add DDR3 ECC error handler */ + error_irq = platform_get_irq(pdev, 0); + if (!error_irq) { + dev_err(&pdev->dev, + "DDR3 ECC irq number not defined\n"); + return ret; + } + + ret = devm_request_irq(dev, error_irq, ks2_mc_ddr3_ecc_isr, 0, + "ddr3-ecc-err-irq", (void *)reg); + if (ret) { + dev_err(&pdev->dev, + "request_irq fail for DDR3 ECC error irq\n"); + return ret; + } + + writel(DDR3_2B_ECC_ERR | DDR3_WR_ECC_ERR, + reg + DDR3_IRQ_ENABLE_SET_SYS); + + return ret; +} + +static struct platform_driver ks2_mc_ddr3_ecc_driver = { + .probe = ks2_mc_ddr3_ecc_probe, + .driver = { + .name = "ks2_mc_ddr3_ecc", + .of_match_table = ks2_mc_ddr3_ecc_of_match, + }, +}; + +static int __init ks2_mc_ddr3_ecc_init(void) +{ + int ret = 0; + + ret = platform_driver_register(&ks2_mc_ddr3_ecc_driver); + if (ret) + pr_warn("keystone DDR3 DDR3 ecc_init failed\n"); + + return ret; +} +subsys_initcall(ks2_mc_ddr3_ecc_init); + +MODULE_AUTHOR("Texas Instruments Inc."); +MODULE_DESCRIPTION("EDAC Driver for Keystone DDR3 MC"); +MODULE_LICENSE("GPL v2"); diff -Naur --no-dereference a/drivers/edac/Makefile b/drivers/edac/Makefile --- a/drivers/edac/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/edac/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -70,3 +70,4 @@ obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o +obj-$(CONFIG_EDAC_KEYSTONE_MC) += keystone_mc_edac.o diff -Naur --no-dereference a/drivers/extcon/extcon-palmas.c b/drivers/extcon/extcon-palmas.c --- a/drivers/extcon/extcon-palmas.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/extcon/extcon-palmas.c 2016-05-11 13:31:53.197225234 -0400 @@ -216,11 +216,23 @@ return PTR_ERR(palmas_usb->id_gpiod); } + palmas_usb->vbus_gpiod = devm_gpiod_get_optional(&pdev->dev, "vbus", + GPIOD_IN); + if (IS_ERR(palmas_usb->vbus_gpiod)) { + dev_err(&pdev->dev, "failed to get vbus gpio\n"); + return PTR_ERR(palmas_usb->vbus_gpiod); + } + if (palmas_usb->enable_id_detection && palmas_usb->id_gpiod) { palmas_usb->enable_id_detection = false; palmas_usb->enable_gpio_id_detection = true; } + if (palmas_usb->enable_vbus_detection && palmas_usb->vbus_gpiod) { + palmas_usb->enable_vbus_detection = false; + palmas_usb->enable_gpio_vbus_detection = true; + } + if (palmas_usb->enable_gpio_id_detection) { u32 debounce; @@ -266,7 +278,7 @@ palmas_usb->id_irq, NULL, palmas_id_irq_handler, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | - IRQF_ONESHOT | IRQF_EARLY_RESUME, + IRQF_ONESHOT, "palmas_usb_id", palmas_usb); if (status < 0) { dev_err(&pdev->dev, "can't get IRQ %d, err %d\n", @@ -304,13 +316,46 @@ palmas_usb->vbus_irq, NULL, palmas_vbus_irq_handler, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | - IRQF_ONESHOT | IRQF_EARLY_RESUME, + IRQF_ONESHOT, "palmas_usb_vbus", palmas_usb); if (status < 0) { dev_err(&pdev->dev, "can't get IRQ %d, err %d\n", palmas_usb->vbus_irq, status); return status; } + } else if (palmas_usb->enable_gpio_vbus_detection) { + /* remux GPIO_1 as VBUSDET */ + status = palmas_update_bits(palmas, + PALMAS_PU_PD_OD_BASE, + PALMAS_PRIMARY_SECONDARY_PAD1, + PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK, + (1 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT)); + if (status < 0) { + dev_err(&pdev->dev, "can't remux GPIO1\n"); + return status; + } + + palmas_usb->vbus_otg_irq = regmap_irq_get_virq(palmas->irq_data, + PALMAS_VBUS_OTG_IRQ); + palmas_usb->gpio_vbus_irq = gpiod_to_irq(palmas_usb->vbus_gpiod); + if (palmas_usb->gpio_vbus_irq < 0) { + dev_err(&pdev->dev, "failed to get vbus irq\n"); + return palmas_usb->gpio_vbus_irq; + } + status = devm_request_threaded_irq(&pdev->dev, + palmas_usb->gpio_vbus_irq, + NULL, + palmas_vbus_irq_handler, + IRQF_TRIGGER_FALLING | + IRQF_TRIGGER_RISING | + IRQF_ONESHOT, + "palmas_usb_vbus", + palmas_usb); + if (status < 0) { + dev_err(&pdev->dev, + "failed to request handler for vbus irq\n"); + return status; + } } palmas_enable_irq(palmas_usb); @@ -337,6 +382,8 @@ if (device_may_wakeup(dev)) { if (palmas_usb->enable_vbus_detection) enable_irq_wake(palmas_usb->vbus_irq); + if (palmas_usb->enable_gpio_vbus_detection) + enable_irq_wake(palmas_usb->gpio_vbus_irq); if (palmas_usb->enable_id_detection) enable_irq_wake(palmas_usb->id_irq); if (palmas_usb->enable_gpio_id_detection) @@ -352,6 +399,8 @@ if (device_may_wakeup(dev)) { if (palmas_usb->enable_vbus_detection) disable_irq_wake(palmas_usb->vbus_irq); + if (palmas_usb->enable_gpio_vbus_detection) + disable_irq_wake(palmas_usb->gpio_vbus_irq); if (palmas_usb->enable_id_detection) disable_irq_wake(palmas_usb->id_irq); if (palmas_usb->enable_gpio_id_detection) diff -Naur --no-dereference a/drivers/extcon/extcon-usb-gpio.c b/drivers/extcon/extcon-usb-gpio.c --- a/drivers/extcon/extcon-usb-gpio.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/extcon/extcon-usb-gpio.c 2016-05-11 13:31:53.197225234 -0400 @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -141,7 +142,8 @@ } platform_set_drvdata(pdev, info); - device_init_wakeup(dev, 1); + device_init_wakeup(dev, true); + dev_pm_set_wake_irq(dev, info->id_irq); /* Perform initial detection */ usb_extcon_detect_cable(&info->wq_detcable.work); @@ -155,6 +157,9 @@ cancel_delayed_work_sync(&info->wq_detcable); + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); + return 0; } @@ -164,12 +169,6 @@ struct usb_extcon_info *info = dev_get_drvdata(dev); int ret = 0; - if (device_may_wakeup(dev)) { - ret = enable_irq_wake(info->id_irq); - if (ret) - return ret; - } - /* * We don't want to process any IRQs after this point * as GPIOs used behind I2C subsystem might not be @@ -185,13 +184,8 @@ struct usb_extcon_info *info = dev_get_drvdata(dev); int ret = 0; - if (device_may_wakeup(dev)) { - ret = disable_irq_wake(info->id_irq); - if (ret) - return ret; - } - enable_irq(info->id_irq); + usb_extcon_detect_cable(&info->wq_detcable.work); return ret; } diff -Naur --no-dereference a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig --- a/drivers/firmware/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/firmware/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -173,6 +173,21 @@ def_bool y depends on QCOM_SCM && ARM64 +config TI_SCI_PROTOCOL + tristate "TI System Control Interface (TISCI) Message Protocol" + depends on TI_MESSAGE_MANAGER + help + TI System Control Interface(TISCI) Message Protocol is used to manage + compute systems such as ARM, DSP etc with the system controller in + complex System on Chip(SoC) such as those found on certain keystone + generation SoC from TI. + + System controller provides various facilities including power + management function support. + + This protocol library is used by client drivers to use the features + provided by the system controller. + source "drivers/firmware/broadcom/Kconfig" source "drivers/firmware/google/Kconfig" source "drivers/firmware/efi/Kconfig" diff -Naur --no-dereference a/drivers/firmware/Makefile b/drivers/firmware/Makefile --- a/drivers/firmware/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/firmware/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a +obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-y += broadcom/ obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ diff -Naur --no-dereference a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c --- a/drivers/firmware/ti_sci.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/firmware/ti_sci.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,1908 @@ +/* + * Texas Instruments System Control Interface Protocol Driver + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * Nishanth Menon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ti_sci.h" + +/* List of all TI SCI devices active in system */ +static LIST_HEAD(ti_sci_list); +/* Protection for the entire list */ +static DEFINE_MUTEX(ti_sci_list_mutex); + +/** + * struct ti_sci_xfer - Structure representing a message flow + * @tx_message: Transmit message + * @rx_len: Receive message length + * @xfer_buf: Preallocated buffer to store receive message + * Since we work with request-ACK protocol, we can + * reuse the same buffer for the rx path as we + * use for the tx path. + * @done: completion event + */ +struct ti_sci_xfer { + struct ti_msgmgr_message tx_message; + u8 rx_len; + u8 *xfer_buf; + struct completion done; +}; + +/** + * struct ti_sci_xfers_info - Structure to manage transfer information + * @sem_xfer_count: Counting Semaphore for managing max simultaneous + * Messages. + * @xfer_block: Preallocated Message array + * @xfer_alloc_table: Bitmap table for allocated messages. + * Index of this bitmap table is also used for message + * sequence identifier. + * @xfer_lock: Protection for message allocation + */ +struct ti_sci_xfers_info { + struct semaphore sem_xfer_count; + struct ti_sci_xfer *xfer_block; + unsigned long *xfer_alloc_table; + /* protect transfer allocation */ + spinlock_t xfer_lock; +}; + +/** + * struct ti_sci_desc - Description of SoC integration + * @host_id: Host identifier representing the compute entity + * @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds) + * @max_msgs: Maximum number of messages that can be pending + * simultaneously in the system + * @max_msg_size: Maximum size of data per message that can be handled. + */ +struct ti_sci_desc { + u8 host_id; + int max_rx_timeout_ms; + int max_msgs; + int max_msg_size; +}; + +/** + * struct ti_sci_info - Structure representing a TI SCI instance + * @dev: Device pointer + * @desc: SoC description for this instance + * @d: Debugfs file entry + * @debug_region: Memory region where the debug message are available + * @debug_region_size: Debug region size + * @debug_buffer: Buffer allocated to copy debug messages. + * @handle: Instance of TI SCI handle to send to clients. + * @cl: Mailbox Client + * @chan_tx: Transmit mailbox channel + * @chan_rx: Receive mailbox channel + * @minfo: Message info + * @node: list head + * @users: Number of users of this instance + */ +struct ti_sci_info { + struct device *dev; + const struct ti_sci_desc *desc; + struct dentry *d; + void __iomem *debug_region; + char *debug_buffer; + size_t debug_region_size; + struct ti_sci_handle handle; + struct mbox_client cl; + struct mbox_chan *chan_tx; + struct mbox_chan *chan_rx; + struct ti_sci_xfers_info minfo; + struct list_head node; + /* protected by ti_sci_list_mutex */ + int users; +}; + +#define cl_to_ti_sci_info(cl) container_of(cl, struct ti_sci_info, cl) +#define handle_to_ti_sci_info(handle) container_of(handle, struct ti_sci_info,\ + handle) +#ifdef CONFIG_DEBUG_FS + +/** + * ti_sci_debug_show() - Helper to dump the debug log + * @s: sequence file pointer + * @unused: unused. + * + * Return: 0 + */ +static int ti_sci_debug_show(struct seq_file *s, void *unused) +{ + struct ti_sci_info *info = s->private; + + memcpy_fromio(info->debug_buffer, info->debug_region, + info->debug_region_size); + /* + * XXX: + * 1. Can we trust firmware to leave NULL terminated last byte?? + * 2. What do we do when log rolls over - how do we detect that and + * provide messages in the right order?? + * TOBEFIXED: rewrite code as per final debug strategy. + */ + seq_puts(s, info->debug_buffer); + return 0; +} + +/** + * ti_sci_debug_open() - debug file open + * @inode: inode pointer + * @file: file pointer + * + * Return: result of single_open + */ +static int ti_sci_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, ti_sci_debug_show, inode->i_private); +} + +/* log file operations */ +static const struct file_operations ti_sci_debug_fops = { + .open = ti_sci_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +/** + * ti_sci_debugfs_create() - Create log debug file + * @pdev: platform device pointer + * @info: Pointer to SCI entity information + * + * Return: 0 if all went fine, else corresponding error. + */ +static int ti_sci_debugfs_create(struct platform_device *pdev, + struct ti_sci_info *info) +{ + struct device *dev = &pdev->dev; + struct resource *res; + char debug_name[50] = "ti_sci_debug@"; + + /* Debug region is optional */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "debug_messages"); + info->debug_region = devm_ioremap_resource(dev, res); + if (IS_ERR(info->debug_region)) + return 0; + info->debug_region_size = resource_size(res); + + info->debug_buffer = devm_kcalloc(dev, info->debug_region_size + 1, + sizeof(char), GFP_KERNEL); + if (!info->debug_buffer) + return -ENOMEM; + /* Setup NULL termination */ + info->debug_buffer[info->debug_region_size] = 0; + + info->d = debugfs_create_file(strncat(debug_name, dev_name(dev), + sizeof(debug_name)), + S_IRUGO, NULL, info, &ti_sci_debug_fops); + if (IS_ERR(info->d)) + return PTR_ERR(info->d); + + dev_dbg(dev, "Debug region => %p, size = %zu bytes, resource: %pr\n", + info->debug_region, info->debug_region_size, res); + return 0; +} + +/** + * ti_sci_debugfs_destroy() - clean up log debug file + * @pdev: platform device pointer + * @info: Pointer to SCI entity information + */ +static void ti_sci_debugfs_destroy(struct platform_device *pdev, + struct ti_sci_info *info) +{ + if (IS_ERR(info->debug_region)) + return; + + debugfs_remove(info->d); +} +#else /* CONFIG_DEBUG_FS */ +static inline int ti_sci_debugfs_create(struct platform_device *dev, + struct ti_sci_info *info) +{ + return 0; +} + +static inline void ti_sci_debugfs_destroy(struct platform_device *dev, + struct ti_sci_info *info) +{ +} +#endif /* CONFIG_DEBUG_FS */ + +/** + * ti_sci_dump_header_dbg() - Helper to dump a message header. + * @dev: Device pointer corresponding to the SCI entity + * @hdr: pointer to header. + */ +static inline void ti_sci_dump_header_dbg(struct device *dev, + struct ti_sci_msg_hdr *hdr) +{ + dev_dbg(dev, "MSGHDR:type=0x%04x host=0x%02x seq=0x%02x flags=0x%08x\n", + hdr->type, hdr->host, hdr->seq, hdr->flags); +} + +/** + * ti_sci_rx_callback() - mailbox client callback for receive messages + * @cl: client pointer + * @m: mailbox message + * + * Processes one received message to appropriate transfer information and + * signals completion of the transfer. + * + * NOTE: This function will be invoked in IRQ context, hence should be + * as optimal as possible. + */ +static void ti_sci_rx_callback(struct mbox_client *cl, void *m) +{ + struct ti_sci_info *info = cl_to_ti_sci_info(cl); + struct device *dev = info->dev; + struct ti_sci_xfers_info *minfo = &info->minfo; + struct ti_msgmgr_message *mbox_msg = m; + struct ti_sci_msg_hdr *hdr = (struct ti_sci_msg_hdr *)mbox_msg->buf; + struct ti_sci_xfer *xfer; + u8 xfer_id; + + xfer_id = hdr->seq; + + /* + * Are we even expecting this? + * NOTE: barriers were implicit in locks used for modifying the bitmap + */ + if (!test_bit(xfer_id, minfo->xfer_alloc_table)) { + dev_err(dev, "Message for %d is not expected!\n", xfer_id); + return; + } + + xfer = &minfo->xfer_block[xfer_id]; + + /* Is the message of valid length? */ + if (mbox_msg->len > info->desc->max_msg_size) { + dev_err(dev, "Unable to handle %d xfer(max %d)\n", + mbox_msg->len, info->desc->max_msg_size); + ti_sci_dump_header_dbg(dev, hdr); + return; + } + if (mbox_msg->len < xfer->rx_len) { + dev_err(dev, "Recv xfer %d < expected %d length\n", + mbox_msg->len, xfer->rx_len); + ti_sci_dump_header_dbg(dev, hdr); + return; + } + + ti_sci_dump_header_dbg(dev, hdr); + /* Take a copy to the rx buffer.. */ + memcpy(xfer->xfer_buf, mbox_msg->buf, xfer->rx_len); + complete(&xfer->done); +} + +/** + * ti_sci_get_one_xfer() - Allocate one message + * @info: Pointer to SCI entity information + * @msg_type: Message type + * @msg_flags: Flag to set for the message + * @tx_message_size: transmit message size + * @rx_message_size: receive message size + * + * Helper function which is used by various command functions that are + * exposed to clients of this driver for allocating a message traffic event. + * + * This function can sleep depending on pending requests already in the system + * for the SCI entity. Further, this also holds a spinlock to maintain integrity + * of internal data structures. + * + * Return: 0 if all went fine, else corresponding error. + */ +static struct ti_sci_xfer *ti_sci_get_one_xfer(struct ti_sci_info *info, + u16 msg_type, u32 msg_flags, + size_t tx_message_size, + size_t rx_message_size) +{ + struct ti_sci_xfers_info *minfo = &info->minfo; + struct ti_sci_xfer *xfer; + struct ti_sci_msg_hdr *hdr; + unsigned long flags; + unsigned long bit_pos; + u8 xfer_id; + int ret; + int timeout; + + /* Ensure we have sane transfer sizes */ + if (rx_message_size > info->desc->max_msg_size || + tx_message_size > info->desc->max_msg_size || + rx_message_size < sizeof(*hdr) || tx_message_size < sizeof(*hdr)) + return ERR_PTR(-ERANGE); + + /* + * Ensure we have only controlled number of pending messages. + * Ideally, we might just have to wait a single message, be + * conservative and wait 5 times that.. + */ + timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms) * 5; + ret = down_timeout(&minfo->sem_xfer_count, timeout); + if (ret < 0) + return ERR_PTR(ret); + + /* Keep the locked section as small as possible */ + spin_lock_irqsave(&minfo->xfer_lock, flags); + bit_pos = find_first_zero_bit(minfo->xfer_alloc_table, + info->desc->max_msgs); + set_bit(bit_pos, minfo->xfer_alloc_table); + spin_unlock_irqrestore(&minfo->xfer_lock, flags); + + /* + * We already ensured in probe that we can have max messages that can + * fit in hdr.seq - NOTE: this improves access latencies + * to predictable O(1) access, BUT, it opens us to risk if + * remote misbehaves with corrupted message sequence responses. + * If that happens, we are going to be messed up anyways.. + */ + xfer_id = (u8)bit_pos; + + xfer = &minfo->xfer_block[xfer_id]; + + hdr = (struct ti_sci_msg_hdr *)xfer->tx_message.buf; + xfer->tx_message.len = tx_message_size; + xfer->rx_len = (u8)rx_message_size; + + reinit_completion(&xfer->done); + + hdr->seq = xfer_id; + hdr->type = msg_type; + hdr->host = info->desc->host_id; + hdr->flags = msg_flags; + + return xfer; +} + +/** + * ti_sci_put_one_xfer() - Release a message + * @minfo: transfer info pointer + * @xfer: message that was reserved by ti_sci_get_one_xfer + * + * This holds a spinlock to maintain integrity of internal data structures. + */ +static void ti_sci_put_one_xfer(struct ti_sci_xfers_info *minfo, + struct ti_sci_xfer *xfer) +{ + unsigned long flags; + struct ti_sci_msg_hdr *hdr; + u8 xfer_id; + + hdr = (struct ti_sci_msg_hdr *)xfer->tx_message.buf; + xfer_id = hdr->seq; + + /* + * Keep the locked section as small as possible + * NOTE: we might escape with smp_mb and no lock here.. + * but just be conservative and symmetric. + */ + spin_lock_irqsave(&minfo->xfer_lock, flags); + clear_bit(xfer_id, minfo->xfer_alloc_table); + spin_unlock_irqrestore(&minfo->xfer_lock, flags); + + /* Increment the count for the next user to get through */ + up(&minfo->sem_xfer_count); +} + +/** + * ti_sci_do_xfer() - Do one transfer + * @info: Pointer to SCI entity information + * @xfer: Transfer to initiate and wait for response + * + * Return: -ETIMEDOUT in case of no response, if transmit error, + * return corresponding error, else if all goes well, + * return 0. + */ +static inline int ti_sci_do_xfer(struct ti_sci_info *info, + struct ti_sci_xfer *xfer) +{ + int ret; + int timeout; + struct device *dev = info->dev; + + ret = mbox_send_message(info->chan_tx, &xfer->tx_message); + if (ret < 0) + return ret; + + ret = 0; + + /* And we wait for the response. */ + timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); + if (!wait_for_completion_timeout(&xfer->done, timeout)) { + dev_err(dev, "Mbox timedout in resp(caller: %pF)\n", + (void *)_RET_IP_); + ret = -ETIMEDOUT; + } + /* + * NOTE: we might prefer not to need the mailbox ticker to manage the + * transfer queueing since the protocol layer queues things by itself. + * Unfortunately, we have to kick the mailbox framework after we have + * received our message. + */ + mbox_client_txdone(info->chan_tx, ret); + + return ret; +} + +/** + * ti_sci_cmd_get_revision() - command to get the revision of the SCI entity + * @info: Pointer to SCI entity information + * + * Updates the SCI information in the internal data structure. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_get_revision(struct ti_sci_info *info) +{ + struct device *dev = info->dev; + struct ti_sci_handle *handle = &info->handle; + struct ti_sci_version_info *ver = &handle->version; + struct ti_sci_msg_resp_version *rev_info; + struct ti_sci_xfer *xfer; + int ret; + + /* No need to setup flags since it is expected to respond */ + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_VERSION, + 0x0, sizeof(struct ti_sci_msg_hdr), + sizeof(*rev_info)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + + rev_info = (struct ti_sci_msg_resp_version *)xfer->xfer_buf; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + ver->abi_major = rev_info->abi_major; + ver->abi_minor = rev_info->abi_minor; + ver->firmware_revision = rev_info->firmware_revision; + strncpy(ver->firmware_description, rev_info->firmware_description, + sizeof(ver->firmware_description)); + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + return ret; +} + +/** + * tis_sci_is_response_ack() - Generic ACK/NACK message checkup + * @r: pointer to response buffer + * + * Return: true if the response was an ACK, else returns false. + */ +static inline bool tis_sci_is_response_ack(void *r) +{ + struct ti_sci_msg_hdr *hdr = r; + + return hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK ? true : false; +} + +/** + * ti_sci_set_device_state() - Set device state helper + * @handle: pointer to TI SCI handle + * @id: Device identifier + * @flags: flags to setup for the device + * @state: State to move the device to + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_set_device_state(const struct ti_sci_handle *handle, + u32 id, u32 flags, u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_device_state *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_DEVICE_STATE, + flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_device_state *)xfer->xfer_buf; + req->id = id; + req->state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = tis_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_get_device_state() - Get device state helper + * @handle: Handle to the device + * @id: Device Identifier + * @clcnt: Pointer to Context Loss Count + * @resets: pointer to resets + * @p_state: pointer to p_state + * @c_state: pointer to c_state + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_get_device_state(const struct ti_sci_handle *handle, + u32 id, u32 *clcnt, u32 *resets, + u8 *p_state, u8 *c_state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_get_device_state *req; + struct ti_sci_msg_resp_get_device_state *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + if (!clcnt && !resets && !p_state && !c_state) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + /* Response is expected, so need of any flags */ + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, + 0, sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_get_device_state *)xfer->xfer_buf; + req->id = id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_get_device_state *)xfer->xfer_buf; + if (!tis_sci_is_response_ack(resp)) { + ret = -ENODEV; + goto fail; + } + + if (clcnt) + *clcnt = resp->context_loss_count; + if (resets) + *resets = resp->resets; + if (p_state) + *p_state = resp->programmed_state; + if (c_state) + *c_state = resp->current_state; +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_get_device() - command to request for device managed by TISCI + * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * @id: Device Identifier + * + * Request for the device - NOTE: the client MUST maintain integrity of + * usage count by balancing get_device with put_device. No refcounting is + * managed by driver for that purpose. + * + * NOTE: The request is for exclusive access for the processor. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id) +{ + return ti_sci_set_device_state(handle, id, + MSG_FLAG_DEVICE_EXCLUSIVE, + MSG_DEVICE_SW_STATE_ON); +} + +/** + * ti_sci_cmd_idle_device() - Command to idle a device managed by TISCI + * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * @id: Device Identifier + * + * Request for the device - NOTE: the client MUST maintain integrity of + * usage count by balancing get_device with put_device. No refcounting is + * managed by driver for that purpose. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id) +{ + return ti_sci_set_device_state(handle, id, + MSG_FLAG_DEVICE_EXCLUSIVE, + MSG_DEVICE_SW_STATE_RETENTION); +} + +/** + * ti_sci_cmd_put_device() - command to release a device managed by TISCI + * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * @id: Device Identifier + * + * Request for the device - NOTE: the client MUST maintain integrity of + * usage count by balancing get_device with put_device. No refcounting is + * managed by driver for that purpose. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_put_device(const struct ti_sci_handle *handle, u32 id) +{ + return ti_sci_set_device_state(handle, id, + 0, MSG_DEVICE_SW_STATE_AUTO_OFF); +} + +/** + * ti_sci_cmd_dev_is_valid() - Is the device valid + * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * @id: Device Identifier + * + * Return: 0 if all went fine and the device ID is valid, else return + * appropriate error. + */ +static int ti_sci_cmd_dev_is_valid(const struct ti_sci_handle *handle, u32 id) +{ + u8 unused; + + /* check the device state which will also tell us if the ID is valid */ + return ti_sci_get_device_state(handle, id, NULL, NULL, NULL, &unused); +} + +/** + * ti_sci_cmd_dev_get_clcnt() - Get context loss counter + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @count: Pointer to Context Loss counter to populate + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_dev_get_clcnt(const struct ti_sci_handle *handle, u32 id, + u32 *count) +{ + return ti_sci_get_device_state(handle, id, count, NULL, NULL, NULL); +} + +/** + * ti_sci_cmd_dev_is_idle() - Check if the device is requested to be idle + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @r_state: true if requested to be idle + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_dev_is_idle(const struct ti_sci_handle *handle, u32 id, + bool *r_state) +{ + int ret; + u8 state; + + if (!r_state) + return -EINVAL; + + ret = ti_sci_get_device_state(handle, id, NULL, NULL, &state, NULL); + if (ret) + return ret; + + *r_state = (state == MSG_DEVICE_SW_STATE_RETENTION); + + return 0; +} + +/** + * ti_sci_cmd_dev_is_stop() - Check if the device is requested to be stopped + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @r_state: true if requested to be stopped + * @curr_state: true if currently stopped. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_dev_is_stop(const struct ti_sci_handle *handle, u32 id, + bool *r_state, bool *curr_state) +{ + int ret; + u8 p_state, c_state; + + if (!r_state && !curr_state) + return -EINVAL; + + ret = + ti_sci_get_device_state(handle, id, NULL, NULL, &p_state, &c_state); + if (ret) + return ret; + + if (r_state) + *r_state = (p_state == MSG_DEVICE_SW_STATE_AUTO_OFF); + if (curr_state) + *curr_state = (c_state == MSG_DEVICE_HW_STATE_OFF); + + return 0; +} + +/** + * ti_sci_cmd_dev_is_on() - Check if the device is requested to be ON + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @r_state: true if requested to be ON + * @curr_state: true if currently ON and active + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_dev_is_on(const struct ti_sci_handle *handle, u32 id, + bool *r_state, bool *curr_state) +{ + int ret; + u8 p_state, c_state; + + if (!r_state && !curr_state) + return -EINVAL; + + ret = + ti_sci_get_device_state(handle, id, NULL, NULL, &p_state, &c_state); + if (ret) + return ret; + + if (r_state) + *r_state = (p_state == MSG_DEVICE_SW_STATE_ON); + if (curr_state) + *curr_state = (c_state == MSG_DEVICE_HW_STATE_ON); + + return 0; +} + +/** + * ti_sci_cmd_dev_is_trans() - Check if the device is currently transitioning + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @curr_state: true if currently transitioning. + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_dev_is_trans(const struct ti_sci_handle *handle, u32 id, + bool *curr_state) +{ + int ret; + u8 state; + + if (!curr_state) + return -EINVAL; + + ret = ti_sci_get_device_state(handle, id, NULL, NULL, NULL, &state); + if (ret) + return ret; + + *curr_state = (state == MSG_DEVICE_HW_STATE_TRANS); + + return 0; +} + +/** + * ti_sci_cmd_set_device_resets() - command to set resets for device managed + * by TISCI + * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle + * @id: Device Identifier + * @reset_state: Device specific reset bit field + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_set_device_resets(const struct ti_sci_handle *handle, + u32 id, u32 reset_state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_device_resets *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_DEVICE_RESETS, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_device_resets *)xfer->xfer_buf; + req->id = id; + req->resets = reset_state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = tis_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_get_device_resets() - Get reset state for device managed + * by TISCI + * @handle: Pointer to TISCI handle + * @id: Device Identifier + * @reset_state: Pointer to reset state to populate + * + * Return: 0 if all went fine, else return appropriate error. + */ +static int ti_sci_cmd_get_device_resets(const struct ti_sci_handle *handle, + u32 id, u32 *reset_state) +{ + return ti_sci_get_device_state(handle, id, NULL, reset_state, NULL, + NULL); +} + +/** + * ti_sci_set_clock_state() - Set clock state helper + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @flags: Header flags as needed + * @state: State to request for the clock. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_set_clock_state(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, + u32 flags, u8 state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_clock_state *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_CLOCK_STATE, + flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_clock_state *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + req->request_state = state; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = tis_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_get_clock_state() - Get clock state helper + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @programmed_state: State requested for clock to move to + * @current_state: State that the clock is currently in + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_get_clock_state(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, + u8 *programmed_state, u8 *current_state) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_get_clock_state *req; + struct ti_sci_msg_resp_get_clock_state *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + if (!programmed_state && !current_state) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_GET_CLOCK_STATE, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_get_clock_state *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_get_clock_state *)xfer->xfer_buf; + + if (!tis_sci_is_response_ack(resp)) { + ret = -ENODEV; + goto fail; + } + + if (programmed_state) + *programmed_state = resp->programmed_state; + if (current_state) + *current_state = resp->current_state; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_get_clock() - Get control of a clock from TI SCI + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @needs_ssc: 'true' if Spread Spectrum clock is desired, else 'false' + * @can_change_freq: 'true' if frequency change is desired, else 'false' + * @enable_input_term: 'true' if input termination is desired, else 'false' + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_get_clock(const struct ti_sci_handle *handle, u32 dev_id, + u8 clk_id, bool needs_ssc, bool can_change_freq, + bool enable_input_term) +{ + u32 flags = 0; + + flags |= needs_ssc ? MSG_FLAG_CLOCK_ALLOW_SSC : 0; + flags |= can_change_freq ? MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE : 0; + flags |= enable_input_term ? MSG_FLAG_CLOCK_INPUT_TERM : 0; + + return ti_sci_set_clock_state(handle, dev_id, clk_id, flags, + MSG_CLOCK_SW_STATE_REQ); +} + +/** + * ti_sci_cmd_idle_clock() - Idle a clock which is in our control + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * + * NOTE: This clock must have been requested by get_clock previously. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_idle_clock(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id) +{ + return ti_sci_set_clock_state(handle, dev_id, clk_id, 0, + MSG_CLOCK_SW_STATE_UNREQ); +} + +/** + * ti_sci_cmd_put_clock() - Release a clock from our control back to TISCI + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * + * NOTE: This clock must have been requested by get_clock previously. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_put_clock(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id) +{ + return ti_sci_set_clock_state(handle, dev_id, clk_id, 0, + MSG_CLOCK_SW_STATE_AUTO); +} + +/** + * ti_sci_cmd_clk_is_auto() - Is the clock being auto managed + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @req_state: state indicating if the clock is auto managed + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_is_auto(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, bool *req_state) +{ + u8 state = 0; + int ret; + + if (!req_state) + return -EINVAL; + + ret = ti_sci_cmd_get_clock_state(handle, dev_id, clk_id, &state, NULL); + if (ret) + return ret; + + *req_state = (state == MSG_CLOCK_SW_STATE_AUTO); + return 0; +} + +/** + * ti_sci_cmd_clk_is_on() - Is the clock ON + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @req_state: state indicating if the clock is managed by us and enabled + * @curr_state: state indicating if the clock is ready for operation + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_is_on(const struct ti_sci_handle *handle, u32 dev_id, + u8 clk_id, bool *req_state, bool *curr_state) +{ + u8 c_state = 0, r_state = 0; + int ret; + + if (!req_state && !curr_state) + return -EINVAL; + + ret = ti_sci_cmd_get_clock_state(handle, dev_id, clk_id, + &r_state, &c_state); + if (ret) + return ret; + + if (req_state) + *req_state = (r_state == MSG_CLOCK_SW_STATE_REQ); + if (curr_state) + *curr_state = (c_state == MSG_CLOCK_HW_STATE_READY); + return 0; +} + +/** + * ti_sci_cmd_clk_is_off() - Is the clock OFF + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @req_state: state indicating if the clock is managed by us and disabled + * @curr_state: state indicating if the clock is NOT ready for operation + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_is_off(const struct ti_sci_handle *handle, u32 dev_id, + u8 clk_id, bool *req_state, bool *curr_state) +{ + u8 c_state = 0, r_state = 0; + int ret; + + if (!req_state && !curr_state) + return -EINVAL; + + ret = ti_sci_cmd_get_clock_state(handle, dev_id, clk_id, + &r_state, &c_state); + if (ret) + return ret; + + if (req_state) + *req_state = (r_state == MSG_CLOCK_SW_STATE_UNREQ); + if (curr_state) + *curr_state = (c_state == MSG_CLOCK_HW_STATE_NOT_READY); + return 0; +} + +/** + * ti_sci_cmd_clk_set_parent() - Set the clock source of a specific device clock + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @parent_id: Parent clock identifier to set + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_set_parent(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, u8 parent_id) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_clock_parent *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_CLOCK_PARENT, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_clock_parent *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + req->parent_id = parent_id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = tis_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_clk_get_parent() - Get current parent clock source + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @parent_id: Current clock parent + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_get_parent(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, u8 *parent_id) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_get_clock_parent *req; + struct ti_sci_msg_resp_get_clock_parent *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle || !parent_id) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_GET_CLOCK_PARENT, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_get_clock_parent *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_get_clock_parent *)xfer->xfer_buf; + + if (!tis_sci_is_response_ack(resp)) + ret = -ENODEV; + else + *parent_id = resp->parent_id; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_clk_get_num_parents() - Get num parents of the current clk source + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @num_parents: Returns he number of parents to the current clock. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_get_num_parents(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, + u8 *num_parents) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_get_clock_num_parents *req; + struct ti_sci_msg_resp_get_clock_num_parents *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle || !num_parents) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_get_clock_num_parents *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_get_clock_num_parents *)xfer->xfer_buf; + + if (!tis_sci_is_response_ack(resp)) + ret = -ENODEV; + else + *num_parents = resp->num_parents; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_clk_get_match_freq() - Find a good match for frequency + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @min_freq: The minimum allowable frequency in Hz. This is the minimum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @target_freq: The target clock frequency in Hz. A frequency will be + * processed as close to this target frequency as possible. + * @max_freq: The maximum allowable frequency in Hz. This is the maximum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @match_freq: Frequency match in Hz response. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_get_match_freq(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, u64 min_freq, + u64 target_freq, u64 max_freq, + u64 *match_freq) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_query_clock_freq *req; + struct ti_sci_msg_resp_query_clock_freq *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle || !match_freq) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_QUERY_CLOCK_FREQ, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_query_clock_freq *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + req->min_freq_hz = min_freq; + req->target_freq_hz = target_freq; + req->max_freq_hz = max_freq; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_query_clock_freq *)xfer->xfer_buf; + + if (!tis_sci_is_response_ack(resp)) + ret = -ENODEV; + else + *match_freq = resp->freq_hz; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_clk_set_freq() - Set a frequency for clock + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @min_freq: The minimum allowable frequency in Hz. This is the minimum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @target_freq: The target clock frequency in Hz. A frequency will be + * processed as close to this target frequency as possible. + * @max_freq: The maximum allowable frequency in Hz. This is the maximum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_set_freq(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, u64 min_freq, + u64 target_freq, u64 max_freq) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_set_clock_freq *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_SET_CLOCK_FREQ, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_set_clock_freq *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + req->min_freq_hz = min_freq; + req->target_freq_hz = target_freq; + req->max_freq_hz = max_freq; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + + ret = tis_sci_is_response_ack(resp) ? 0 : -ENODEV; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/** + * ti_sci_cmd_clk_get_freq() - Get current frequency + * @handle: pointer to TI SCI handle + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @freq: Currently frequency in Hz + * + * Return: 0 if all went well, else returns appropriate error value. + */ +static int ti_sci_cmd_clk_get_freq(const struct ti_sci_handle *handle, + u32 dev_id, u8 clk_id, u64 *freq) +{ + struct ti_sci_info *info; + struct ti_sci_msg_req_get_clock_freq *req; + struct ti_sci_msg_resp_get_clock_freq *resp; + struct ti_sci_xfer *xfer; + struct device *dev; + int ret = 0; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle || !freq) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_GET_CLOCK_FREQ, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "Message alloc failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_req_get_clock_freq *)xfer->xfer_buf; + req->dev_id = dev_id; + req->clk_id = clk_id; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "Mbox send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_resp_get_clock_freq *)xfer->xfer_buf; + + if (!tis_sci_is_response_ack(resp)) + ret = -ENODEV; + else + *freq = resp->freq_hz; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + + return ret; +} + +/* + * ti_sci_setup_ops() - Setup the operations structures + * @info: pointer to TISCI pointer + */ +static void ti_sci_setup_ops(struct ti_sci_info *info) +{ + struct ti_sci_ops *ops = &info->handle.ops; + struct ti_sci_dev_ops *dops = &ops->dev_ops; + struct ti_sci_clk_ops *cops = &ops->clk_ops; + + dops->get_device = ti_sci_cmd_get_device; + dops->idle_device = ti_sci_cmd_idle_device; + dops->put_device = ti_sci_cmd_put_device; + + dops->is_valid = ti_sci_cmd_dev_is_valid; + dops->get_context_loss_count = ti_sci_cmd_dev_get_clcnt; + dops->is_idle = ti_sci_cmd_dev_is_idle; + dops->is_stop = ti_sci_cmd_dev_is_stop; + dops->is_on = ti_sci_cmd_dev_is_on; + dops->is_transitioning = ti_sci_cmd_dev_is_trans; + dops->set_device_resets = ti_sci_cmd_set_device_resets; + dops->get_device_resets = ti_sci_cmd_get_device_resets; + + cops->get_clock = ti_sci_cmd_get_clock; + cops->idle_clock = ti_sci_cmd_idle_clock; + cops->put_clock = ti_sci_cmd_put_clock; + cops->is_auto = ti_sci_cmd_clk_is_auto; + cops->is_on = ti_sci_cmd_clk_is_on; + cops->is_off = ti_sci_cmd_clk_is_off; + + cops->set_parent = ti_sci_cmd_clk_set_parent; + cops->get_parent = ti_sci_cmd_clk_get_parent; + cops->get_num_parents = ti_sci_cmd_clk_get_num_parents; + + cops->get_best_match_freq = ti_sci_cmd_clk_get_match_freq; + cops->set_freq = ti_sci_cmd_clk_set_freq; + cops->get_freq = ti_sci_cmd_clk_get_freq; +} + +/** + * ti_sci_get_handle() - Get the TI SCI handle for a device + * @dev: Pointer to device for which we want SCI handle + * + * NOTE: The function does not track individual clients of the framework + * and is expected to be maintained by caller of TI SCI protocol library. + * ti_sci_put_handle must be balanced with successful ti_sci_get_handle + * Return: pointer to handle if successful, else: + * -EPROBE_DEFER if the instance is not ready + * -ENODEV if the required node handler is missing + * -EINVAL if invalid conditions are encountered. + */ +const struct ti_sci_handle *ti_sci_get_handle(struct device *dev) +{ + struct device_node *np; + struct device_node *ti_sci_np; + struct list_head *p; + struct ti_sci_handle *handle = NULL; + struct ti_sci_info *info; + + if (!dev) { + pr_err("I need a device pointer\n"); + return ERR_PTR(-EINVAL); + } + np = dev->of_node; + if (!np) { + dev_err(dev, "No OF information\n"); + return ERR_PTR(-EINVAL); + } + + ti_sci_np = of_parse_phandle(np, "ti,sci", 0); + if (!ti_sci_np) { + dev_err(dev, "Needs a 'ti,sci' phandle\n"); + return ERR_PTR(-ENODEV); + } + + mutex_lock(&ti_sci_list_mutex); + list_for_each(p, &ti_sci_list) { + info = list_entry(p, struct ti_sci_info, node); + if (ti_sci_np == info->dev->of_node) { + handle = &info->handle; + info->users++; + break; + } + } + mutex_unlock(&ti_sci_list_mutex); + of_node_put(ti_sci_np); + + if (!handle) + return ERR_PTR(-EPROBE_DEFER); + + return handle; +} +EXPORT_SYMBOL_GPL(ti_sci_get_handle); + +/** + * ti_sci_put_handle() - Release the handle acquired by ti_sci_get_handle + * @handle: Handle acquired by ti_sci_get_handle + * + * NOTE: The function does not track individual clients of the framework + * and is expected to be maintained by caller of TI SCI protocol library. + * ti_sci_put_handle must be balanced with successful ti_sci_get_handle + * + * Return: 0 is successfully released + * if an error pointer was passed, it returns the error value back, + * if null was passed, it returns -EINVAL; + */ +int ti_sci_put_handle(const struct ti_sci_handle *handle) +{ + struct ti_sci_info *info; + + if (IS_ERR(handle)) + return PTR_ERR(handle); + if (!handle) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + mutex_lock(&ti_sci_list_mutex); + if (!WARN_ON(!info->users)) + info->users--; + mutex_unlock(&ti_sci_list_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(ti_sci_put_handle); + +static void devm_ti_sci_release(struct device *dev, void *res) +{ + const struct ti_sci_handle **ptr = res; + const struct ti_sci_handle *handle = *ptr; + int ret; + + ret = ti_sci_put_handle(handle); + if (ret) + dev_err(dev, "failed to put handle %d\n", ret); +} + +/** + * devm_ti_sci_get_handle() - Managed get handle + * @dev: device for which we want SCI handle for. + * + * NOTE: This releases the handle once the device resources are + * no longer needed. MUST NOT BE released with ti_sci_put_handle. + * The function does not track individual clients of the framework + * and is expected to be maintained by caller of TI SCI protocol library. + * + * Return: 0 if all went fine, else corresponding error. + */ +const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev) +{ + const struct ti_sci_handle **ptr; + const struct ti_sci_handle *handle; + + ptr = devres_alloc(devm_ti_sci_release, sizeof(*ptr), GFP_KERNEL); + if (!ptr) + return ERR_PTR(-ENOMEM); + handle = ti_sci_get_handle(dev); + + if (!IS_ERR(handle)) { + *ptr = handle; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + + return handle; +} +EXPORT_SYMBOL_GPL(devm_ti_sci_get_handle); + +/* Description for K2G */ +static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = { + .host_id = 2, + /* Conservative duration */ + .max_rx_timeout_ms = 1000, + /* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */ + .max_msgs = 20, + .max_msg_size = 64, +}; + +static const struct of_device_id ti_sci_of_match[] = { + {.compatible = "ti,k2g-sci", .data = &ti_sci_pmmc_k2g_desc}, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ti_sci_of_match); + +static int ti_sci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id; + const struct ti_sci_desc *desc; + struct ti_sci_xfer *xfer; + struct ti_sci_info *info = NULL; + struct ti_sci_xfers_info *minfo; + struct mbox_client *cl; + int ret = -EINVAL; + int i; + + of_id = of_match_device(ti_sci_of_match, dev); + if (!of_id) { + dev_err(dev, "OF data missing\n"); + return -EINVAL; + } + desc = of_id->data; + + info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->dev = dev; + info->desc = desc; + INIT_LIST_HEAD(&info->node); + minfo = &info->minfo; + + /* + * Pre-allocate messages + * NEVER allocate more than what we can indicate in hdr.seq + * if we have data description bug, force a fix.. + */ + if (WARN_ON(desc->max_msgs >= + 1 << 8 * sizeof(((struct ti_sci_msg_hdr *)0)->seq))) + return -EINVAL; + + minfo->xfer_block = devm_kcalloc(dev, + desc->max_msgs, + sizeof(*minfo->xfer_block), + GFP_KERNEL); + if (!minfo->xfer_block) + return -ENOMEM; + + minfo->xfer_alloc_table = devm_kzalloc(dev, + BITS_TO_LONGS(desc->max_msgs) + * sizeof(unsigned long), + GFP_KERNEL); + if (!minfo->xfer_alloc_table) + return -ENOMEM; + bitmap_zero(minfo->xfer_alloc_table, desc->max_msgs); + + /* Pre-initialize the buffer pointer to pre-allocated buffers */ + for (i = 0, xfer = minfo->xfer_block; i < desc->max_msgs; i++, xfer++) { + xfer->xfer_buf = devm_kcalloc(dev, 1, desc->max_msg_size, + GFP_KERNEL); + if (!xfer->xfer_buf) + return -ENOMEM; + + xfer->tx_message.buf = xfer->xfer_buf; + init_completion(&xfer->done); + } + + ret = ti_sci_debugfs_create(pdev, info); + if (ret) + dev_warn(dev, "Failed to create debug file\n"); + + platform_set_drvdata(pdev, info); + + cl = &info->cl; + cl->dev = dev; + cl->tx_block = false; + cl->rx_callback = ti_sci_rx_callback; + cl->knows_txdone = true; + + spin_lock_init(&minfo->xfer_lock); + sema_init(&minfo->sem_xfer_count, desc->max_msgs); + + info->chan_rx = mbox_request_channel_byname(cl, "rx"); + if (IS_ERR(info->chan_rx)) { + ret = PTR_ERR(info->chan_rx); + goto out; + } + + info->chan_tx = mbox_request_channel_byname(cl, "tx"); + if (IS_ERR(info->chan_tx)) { + ret = PTR_ERR(info->chan_tx); + goto out; + } + ret = ti_sci_cmd_get_revision(info); + if (ret) { + dev_err(dev, "Unable to communicate with TISCI(%d)\n", ret); + goto out; + } + + ti_sci_setup_ops(info); + + dev_info(dev, "ABI: %d.%d (firmware rev 0x%04x '%s')\n", + info->handle.version.abi_major, info->handle.version.abi_minor, + info->handle.version.firmware_revision, + info->handle.version.firmware_description); + + mutex_lock(&ti_sci_list_mutex); + list_add_tail(&info->node, &ti_sci_list); + mutex_unlock(&ti_sci_list_mutex); + + return 0; +out: + if (!IS_ERR(info->chan_tx)) + mbox_free_channel(info->chan_tx); + if (!IS_ERR(info->chan_rx)) + mbox_free_channel(info->chan_rx); + debugfs_remove(info->d); + return ret; +} + +static int ti_sci_remove(struct platform_device *pdev) +{ + struct ti_sci_info *info; + int ret = 0; + + info = platform_get_drvdata(pdev); + + mutex_lock(&ti_sci_list_mutex); + if (info->users) + ret = -EBUSY; + else + list_del(&info->node); + mutex_unlock(&ti_sci_list_mutex); + + if (!ret) + ti_sci_debugfs_destroy(pdev, info); + + return ret; +} + +static struct platform_driver ti_sci_driver = { + .probe = ti_sci_probe, + .remove = ti_sci_remove, + .driver = { + .name = "ti-sci", + .of_match_table = of_match_ptr(ti_sci_of_match), + }, +}; +module_platform_driver(ti_sci_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("TI System Control Interface(SCI) driver"); +MODULE_AUTHOR("Nishanth Menon"); +MODULE_ALIAS("platform:ti-sci"); diff -Naur --no-dereference a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h --- a/drivers/firmware/ti_sci.h 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/firmware/ti_sci.h 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,480 @@ +/* + * Texas Instruments System Control Interface (TISCI) Protocol + * + * Communication protocol with TI SCI hardware + * The system works in a message response protocol + * See: https://...blablablah.com/asdasdasa.pdf for details + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __TI_SCI_H +#define __TI_SCI_H + +/* Generic Messages */ +#define TI_SCI_MSG_ENABLE_WDT 0x0000 +#define TI_SCI_MSG_WAKE_RESET 0x0001 +#define TI_SCI_MSG_VERSION 0x0002 +#define TI_SCI_MSG_WAKE_REASON 0x0003 +#define TI_SCI_MSG_GOODBYE 0x0004 + +/* Device requests */ +#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 +#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 +#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 + +/* Clock requests */ +#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 +#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 +#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 +#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 +#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 +#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c +#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d +#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e + +/** + * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses + * @type: Type of messages: One of TI_SCI_MSG* values + * @host: Host of the message + * @seq: Message identifier indicating a transfer sequence + * @flags: Flag for the message + */ +struct ti_sci_msg_hdr { + u16 type; + u8 host; + u8 seq; +#define TI_SCI_MSG_FLAG(val) (1 << (val)) +#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 +#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) +#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) +#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 +#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) + /* Additional Flags */ + u32 flags; +} __packed; + +/** + * struct ti_sci_msg_resp_version - Response for a message + * @hdr: Generic header + * @firmware_description: String describing the firmware + * @firmware_revision: Firmware revision + * @abi_major: Major version of the ABI that firmware supports + * @abi_minor: Minor version of the ABI that firmware supports + * + * In general, ABI version changes follow the rule that minor version increments + * are backward compatible. Major revision changes in ABI may not be + * backward compatible. + * + * Response to a generic message with message type TI_SCI_MSG_VERSION + */ +struct ti_sci_msg_resp_version { + struct ti_sci_msg_hdr hdr; + char firmware_description[32]; + u16 firmware_revision; + u8 abi_major; + u8 abi_minor; +} __packed; + +/** + * struct ti_sci_msg_req_set_device_state - Set the desired state of the device + * @hdr: Generic header + * @id: Indicates which device to modify + * @reserved: Reserved space in message, must be 0 for backward compatibility + * @state: The desired state of the device. + * + * Certain flags can also be set to alter the device state: + * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. + * The meaning of this flag will vary slightly from device to device and from + * SoC to SoC but it generally allows the device to wake the SoC out of deep + * suspend states. + * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. + * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed + * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. + * If another host already has this device set to STATE_RETENTION or STATE_ON, + * the message will fail. Once successful, other hosts attempting to set + * STATE_RETENTION or STATE_ON will fail. + * + * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic + * ACK/NACK message. + */ +struct ti_sci_msg_req_set_device_state { + /* Additional hdr->flags options */ +#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) +#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) +#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) + struct ti_sci_msg_hdr hdr; + u32 id; + u32 reserved; + +#define MSG_DEVICE_SW_STATE_AUTO_OFF 0 +#define MSG_DEVICE_SW_STATE_RETENTION 1 +#define MSG_DEVICE_SW_STATE_ON 2 + u8 state; +} __packed; + +/** + * struct ti_sci_msg_req_get_device_state - Request to get device. + * @hdr: Generic header + * @id: Device Identifier + * + * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state + * information + */ +struct ti_sci_msg_req_get_device_state { + struct ti_sci_msg_hdr hdr; + u32 id; +} __packed; + +/** + * struct ti_sci_msg_resp_get_device_state - Response to get device request. + * @hdr: Generic header + * @context_loss_count: Indicates how many times the device has lost context. A + * driver can use this monotonic counter to determine if the device has + * lost context since the last time this message was exchanged. + * @resets: Programmed state of the reset lines. + * @programmed_state: The state as programmed by set_device. + * - Uses the MSG_DEVICE_SW_* macros + * @current_state: The actual state of the hardware. + * + * Response to request TI_SCI_MSG_GET_DEVICE_STATE. + */ +struct ti_sci_msg_resp_get_device_state { + struct ti_sci_msg_hdr hdr; + u32 context_loss_count; + u32 resets; + u8 programmed_state; +#define MSG_DEVICE_HW_STATE_OFF 0 +#define MSG_DEVICE_HW_STATE_ON 1 +#define MSG_DEVICE_HW_STATE_TRANS 2 + u8 current_state; +} __packed; + +/** + * struct ti_sci_msg_req_set_device_resets - Set the desired resets + * configuration of the device + * @hdr: Generic header + * @id: Indicates which device to modify + * @resets: A bit field of resets for the device. The meaning, behavior, + * and usage of the reset flags are device specific. 0 for a bit + * indicates releasing the reset represented by that bit while 1 + * indicates keeping it held. + * + * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic + * ACK/NACK message. + */ +struct ti_sci_msg_req_set_device_resets { + struct ti_sci_msg_hdr hdr; + u32 id; + u32 resets; +} __packed; + +/** + * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state + * @hdr: Generic Header, Certain flags can be set specific to the clocks: + * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified + * via spread spectrum clocking. + * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's + * frequency to be changed while it is running so long as it + * is within the min/max limits. + * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this + * is only applicable to clock inputs on the SoC pseudo-device. + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @request_state: Request the state for the clock to be set to. + * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, + * it can be disabled, regardless of the state of the device + * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to + * automatically manage the state of this clock. If the device + * is enabled, then the clock is enabled. If the device is set + * to off or retention, then the clock is internally set as not + * being required by the device.(default) + * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, + * regardless of the state of the device. + * + * Normally, all required clocks are managed by TISCI entity, this is used + * only for specific control *IF* required. Auto managed state is + * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote + * will explicitly control. + * + * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic + * ACK or NACK message. + */ +struct ti_sci_msg_req_set_clock_state { + /* Additional hdr->flags options */ +#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) +#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) +#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; +#define MSG_CLOCK_SW_STATE_UNREQ 0 +#define MSG_CLOCK_SW_STATE_AUTO 1 +#define MSG_CLOCK_SW_STATE_REQ 2 + u8 request_state; +} __packed; + +/** + * struct ti_sci_msg_req_get_clock_state - Request for clock state + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to get state of. + * + * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state + * of the clock + */ +struct ti_sci_msg_req_get_clock_state { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_resp_get_clock_state - Response to get clock state + * @hdr: Generic Header + * @programmed_state: Any programmed state of the clock. This is one of + * MSG_CLOCK_SW_STATE* values. + * @current_state: Current state of the clock. This is one of: + * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready + * MSG_CLOCK_HW_STATE_READY: Clock is ready + * + * Response to TI_SCI_MSG_GET_CLOCK_STATE. + */ +struct ti_sci_msg_resp_get_clock_state { + struct ti_sci_msg_hdr hdr; + u8 programmed_state; +#define MSG_CLOCK_HW_STATE_NOT_READY 0 +#define MSG_CLOCK_HW_STATE_READY 1 + u8 current_state; +} __packed; + +/** + * struct ti_sci_msg_req_set_clock_parent - Set the clock parent + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to modify. + * @parent_id: The new clock parent is selectable by an index via this + * parameter. + * + * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic + * ACK / NACK message. + */ +struct ti_sci_msg_req_set_clock_parent { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; + u8 parent_id; +} __packed; + +/** + * struct ti_sci_msg_req_get_clock_parent - Get the clock parent + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * Each device has it's own set of clock inputs. This indexes + * which clock input to get the parent for. + * + * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information + */ +struct ti_sci_msg_req_get_clock_parent { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent + * @hdr: Generic Header + * @parent_id: The current clock parent + * + * Response to TI_SCI_MSG_GET_CLOCK_PARENT. + */ +struct ti_sci_msg_resp_get_clock_parent { + struct ti_sci_msg_hdr hdr; + u8 parent_id; +} __packed; + +/** + * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents + * @hdr: Generic header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * + * This request provides information about how many clock parent options + * are available for a given clock to a device. This is typically used + * for input clocks. + * + * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate + * message, or NACK in case of inability to satisfy request. + */ +struct ti_sci_msg_req_get_clock_num_parents { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents + * @hdr: Generic header + * @num_parents: Number of clock parents + * + * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS + */ +struct ti_sci_msg_resp_get_clock_num_parents { + struct ti_sci_msg_hdr hdr; + u8 num_parents; +} __packed; + +/** + * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @target_freq_hz: The target clock frequency. A frequency will be found + * as close to this target frequency as possible. + * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @clk_id: Clock identifier for the device for this request. + * + * NOTE: Normally clock frequency management is automatically done by TISCI + * entity. In case of specific requests, TISCI evaluates capability to achieve + * requested frequency within provided range and responds with + * result message. + * + * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, + * or NACK in case of inability to satisfy request. + */ +struct ti_sci_msg_req_query_clock_freq { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u64 min_freq_hz; + u64 target_freq_hz; + u64 max_freq_hz; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query + * @hdr: Generic Header + * @freq_hz: Frequency that is the best match in Hz. + * + * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request + * cannot be satisfied, the message will be of type NACK. + */ +struct ti_sci_msg_resp_query_clock_freq { + struct ti_sci_msg_hdr hdr; + u64 freq_hz; +} __packed; + +/** + * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @target_freq_hz: The target clock frequency. The clock will be programmed + * at a rate as close to this target frequency as possible. + * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum + * allowable programmed frequency and does not account for clock + * tolerances and jitter. + * @clk_id: Clock identifier for the device for this request. + * + * NOTE: Normally clock frequency management is automatically done by TISCI + * entity. In case of specific requests, TISCI evaluates capability to achieve + * requested range and responds with success/failure message. + * + * This sets the desired frequency for a clock within an allowable + * range. This message will fail on an enabled clock unless + * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, + * if other clocks have their frequency modified due to this message, + * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. + * + * Calling set frequency on a clock input to the SoC pseudo-device will + * inform the PMMC of that clock's frequency. Setting a frequency of + * zero will indicate the clock is disabled. + * + * Calling set frequency on clock outputs from the SoC pseudo-device will + * function similarly to setting the clock frequency on a device. + * + * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK + * message. + */ +struct ti_sci_msg_req_set_clock_freq { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u64 min_freq_hz; + u64 target_freq_hz; + u64 max_freq_hz; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency + * @hdr: Generic Header + * @dev_id: Device identifier this request is for + * @clk_id: Clock identifier for the device for this request. + * + * NOTE: Normally clock frequency management is automatically done by TISCI + * entity. In some cases, clock frequencies are configured by host. + * + * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency + * that the clock is currently at. + */ +struct ti_sci_msg_req_get_clock_freq { + struct ti_sci_msg_hdr hdr; + u32 dev_id; + u8 clk_id; +} __packed; + +/** + * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request + * @hdr: Generic Header + * @freq_hz: Frequency that the clock is currently on, in Hz. + * + * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. + */ +struct ti_sci_msg_resp_get_clock_freq { + struct ti_sci_msg_hdr hdr; + u64 freq_hz; +} __packed; + +#endif /* __TI_SCI_H */ diff -Naur --no-dereference a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c --- a/drivers/gpio/gpio-davinci.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpio/gpio-davinci.c 2016-05-11 13:31:53.197225234 -0400 @@ -45,25 +45,7 @@ container_of(chip, struct davinci_gpio_controller, chip) static void __iomem *gpio_base; - -static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio) -{ - void __iomem *ptr; - - if (gpio < 32 * 1) - ptr = gpio_base + 0x10; - else if (gpio < 32 * 2) - ptr = gpio_base + 0x38; - else if (gpio < 32 * 3) - ptr = gpio_base + 0x60; - else if (gpio < 32 * 4) - ptr = gpio_base + 0x88; - else if (gpio < 32 * 5) - ptr = gpio_base + 0xb0; - else - ptr = NULL; - return ptr; -} +static unsigned offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) { @@ -197,13 +179,14 @@ static int davinci_gpio_probe(struct platform_device *pdev) { - int i, base; - unsigned ngpio; + int i, base, temp_ctrl_base; + unsigned ngpio, nbank; struct davinci_gpio_controller *chips; struct davinci_gpio_platform_data *pdata; struct davinci_gpio_regs __iomem *regs; struct device *dev = &pdev->dev; struct resource *res; + static int bank_base; pdata = davinci_gpio_get_pdata(pdev); if (!pdata) { @@ -227,8 +210,9 @@ if (WARN_ON(ARCH_NR_GPIOS < ngpio)) ngpio = ARCH_NR_GPIOS; + nbank = DIV_ROUND_UP(ngpio, 32); chips = devm_kzalloc(dev, - ngpio * sizeof(struct davinci_gpio_controller), + nbank * sizeof(struct davinci_gpio_controller), GFP_KERNEL); if (!chips) return -ENOMEM; @@ -238,6 +222,8 @@ if (IS_ERR(gpio_base)) return PTR_ERR(gpio_base); + temp_ctrl_base = bank_base; + for (i = 0, base = 0; base < ngpio; i++, base += 32) { chips[i].chip.label = "DaVinci"; @@ -246,10 +232,14 @@ chips[i].chip.direction_output = davinci_direction_out; chips[i].chip.set = davinci_gpio_set; - chips[i].chip.base = base; + chips[i].chip.base = bank_base; + chips[i].ctrl_base = temp_ctrl_base; + bank_base += 32; chips[i].chip.ngpio = ngpio - base; if (chips[i].chip.ngpio > 32) chips[i].chip.ngpio = 32; + else + bank_base = ngpio; #ifdef CONFIG_OF_GPIO chips[i].chip.of_gpio_n_cells = 2; @@ -259,7 +249,7 @@ #endif spin_lock_init(&chips[i].lock); - regs = gpio2regs(base); + regs = gpio_base + offset_array[i]; chips[i].regs = regs; chips[i].set_data = ®s->set_data; chips[i].clr_data = ®s->clr_data; @@ -337,7 +327,7 @@ g = (struct davinci_gpio_regs __iomem *)d->regs; /* we only care about one bank */ - if (irq & 1) + if (irq == d->birq2) mask <<= 16; /* temporarily mask (level sensitive) parent IRQ */ @@ -345,6 +335,7 @@ while (1) { u32 status; int bit; + irq_hw_number_t hw_irq; /* ack any irqs */ status = readl_relaxed(&g->intstat) & mask; @@ -357,9 +348,13 @@ while (status) { bit = __ffs(status); status &= ~BIT(bit); + /* Max number of gpios per controller is 144 so + * hw_irq will be in [0..143] + */ + hw_irq = (d->chip.base - d->ctrl_base) + bit; + generic_handle_irq( - irq_find_mapping(d->irq_domain, - d->chip.base + bit)); + irq_find_mapping(d->irq_domain, hw_irq)); } } chained_irq_exit(irq_desc_get_chip(desc), desc); @@ -369,11 +364,17 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) { struct davinci_gpio_controller *d = chip2controller(chip); + irq_hw_number_t hw_irq; - if (d->irq_domain) - return irq_create_mapping(d->irq_domain, d->chip.base + offset); - else + if (d->irq_domain) { + /* Max number of gpios per controller is 144 so + * hw_irq will be in [0..143] + */ + hw_irq = (d->chip.base - d->ctrl_base) + offset; + return irq_create_mapping(d->irq_domain, hw_irq); + } else { return -ENXIO; + } } static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) @@ -415,7 +416,9 @@ davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - struct davinci_gpio_regs __iomem *g = gpio2regs(hw); + struct davinci_gpio_controller *chips = + (struct davinci_gpio_controller *)d->host_data; + struct davinci_gpio_regs __iomem *g = chips[hw / 32].regs; irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, "davinci_gpio"); @@ -451,6 +454,26 @@ static const struct of_device_id davinci_gpio_ids[]; +struct gpio_driver_data { + gpio_get_irq_chip_cb_t gpio_get_irq_chip; + bool clk_optional; +}; + +static struct gpio_driver_data davinci_data = { + .gpio_get_irq_chip = davinci_gpio_get_irq_chip, + .clk_optional = false, +}; + +static struct gpio_driver_data keystone_data = { + .gpio_get_irq_chip = keystone_gpio_get_irq_chip, + .clk_optional = false, +}; + +static struct gpio_driver_data k2g_data = { + .gpio_get_irq_chip = keystone_gpio_get_irq_chip, + .clk_optional = true, +}; + /* * NOTE: for suspend/resume, probably best to make a platform_device with * suspend_late/resume_resume calls hooking into results of the set_wake() @@ -474,6 +497,7 @@ struct irq_domain *irq_domain = NULL; const struct of_device_id *match; struct irq_chip *irq_chip; + struct gpio_driver_data *driver_data = NULL; gpio_get_irq_chip_cb_t gpio_get_irq_chip; /* @@ -482,8 +506,10 @@ gpio_get_irq_chip = davinci_gpio_get_irq_chip; match = of_match_device(of_match_ptr(davinci_gpio_ids), dev); - if (match) - gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; + if (match) { + driver_data = (struct gpio_driver_data *)match->data; + gpio_get_irq_chip = driver_data->gpio_get_irq_chip; + } ngpio = pdata->ngpio; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); @@ -499,6 +525,9 @@ return -ENODEV; } + if (driver_data && driver_data->clk_optional) + goto skip_clk_handling; + clk = devm_clk_get(dev, "gpio"); if (IS_ERR(clk)) { printk(KERN_ERR "Error %ld getting gpio clock?\n", @@ -507,6 +536,7 @@ } clk_prepare_enable(clk); +skip_clk_handling: if (!pdata->gpio_unbanked) { irq = irq_alloc_descs(-1, 0, ngpio, 0); if (irq < 0) { @@ -514,7 +544,7 @@ return irq; } - irq_domain = irq_domain_add_legacy(NULL, ngpio, irq, 0, + irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, &davinci_gpio_irq_ops, chips); if (!irq_domain) { @@ -553,7 +583,7 @@ irq_chip->irq_set_type = gpio_irq_type_unbanked; /* default trigger: both edges */ - g = gpio2regs(0); + g = chips[0].regs; writel_relaxed(~0, &g->set_falling); writel_relaxed(~0, &g->set_rising); @@ -573,10 +603,16 @@ */ for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) { /* disabled by default, enabled only as needed */ - g = gpio2regs(gpio); + g = chips[bank / 2].regs; writel_relaxed(~0, &g->clr_falling); writel_relaxed(~0, &g->clr_rising); + bank_irq = platform_get_irq(pdev, bank); + if (bank % 1) + chips[bank / 2].birq2 = bank_irq; + else + chips[bank / 2].birq1 = bank_irq; + /* * Each chip handles 32 gpios, and each irq bank consists of 16 * gpio irqs. Pass the irq bank's corresponding controller to @@ -600,8 +636,18 @@ #if IS_ENABLED(CONFIG_OF) static const struct of_device_id davinci_gpio_ids[] = { - { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, - { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, + { + .compatible = "ti,keystone-gpio", + .data = &keystone_data, + }, + { + .compatible = "ti,dm6441-gpio", + .data = &davinci_data, + }, + { + .compatible = "ti,k2g-gpio", + .data = &k2g_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, davinci_gpio_ids); diff -Naur --no-dereference a/drivers/gpio/gpio-of-helper.c b/drivers/gpio/gpio-of-helper.c --- a/drivers/gpio/gpio-of-helper.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpio/gpio-of-helper.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,429 @@ +/* + * GPIO OF based helper + * + * A simple DT based driver to provide access to GPIO functionality + * to user-space via sysfs. + * + * Copyright (C) 2013 Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* fwd decl. */ +struct gpio_of_helper_info; + +enum gpio_type { + GPIO_TYPE_INPUT = 0, + GPIO_TYPE_OUTPUT = 1, +}; + +struct gpio_of_entry { + int id; + struct gpio_of_helper_info *info; + struct device_node *node; + enum gpio_type type; + int gpio; + enum of_gpio_flags gpio_flags; + int irq; + const char *name; + atomic64_t counter; + unsigned int count_flags; +#define COUNT_RISING_EDGE (1 << 0) +#define COUNT_FALLING_EDGE (1 << 1) +}; + +struct gpio_of_helper_info { + struct platform_device *pdev; + struct idr idr; +}; + +static const struct of_device_id gpio_of_helper_of_match[] = { + { + .compatible = "gpio-of-helper", + }, + { }, +}; +MODULE_DEVICE_TABLE(of, gpio_of_helper_of_match); + +static ssize_t gpio_of_helper_show_status(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gpio_of_helper_info *info = platform_get_drvdata(pdev); + struct gpio_of_entry *entry; + char *p, *e; + int id, n; + + p = buf; + e = p + PAGE_SIZE; + n = 0; + idr_for_each_entry(&info->idr, entry, id) { + switch (entry->type) { + case GPIO_TYPE_INPUT: + n = snprintf(p, e - p, "%2d %-24s %3d %-3s %llu\n", + entry->id, entry->name, entry->gpio, "IN", + (unsigned long long) + atomic64_read(&entry->counter)); + break; + case GPIO_TYPE_OUTPUT: + n = snprintf(p, e - p, "%2d %-24s %3d %-3s\n", + entry->id, entry->name, entry->gpio, "OUT"); + break; + } + p += n; + } + + return p - buf; +} + +static DEVICE_ATTR(status, S_IRUGO, + gpio_of_helper_show_status, NULL); + +static irqreturn_t gpio_of_helper_handler(int irq, void *ptr) +{ + struct gpio_of_entry *entry = ptr; + + /* caution - low speed interfaces only! */ + atomic64_inc(&entry->counter); + + return IRQ_HANDLED; +} + +static struct gpio_of_entry * +gpio_of_entry_create(struct gpio_of_helper_info *info, + struct device_node *node) +{ + struct platform_device *pdev = info->pdev; + struct device *dev = &pdev->dev; + struct gpio_of_entry *entry; + int err, gpio, irq; + unsigned int req_flags, count_flags, irq_flags; + enum gpio_type type; + enum of_gpio_flags gpio_flags; + const char *name; + + /* get the type of the node first */ + if (of_property_read_bool(node, "input")) + type = GPIO_TYPE_INPUT; + else if (of_property_read_bool(node, "output")) + type = GPIO_TYPE_OUTPUT; + else { + dev_err(dev, "Not valid gpio node type\n"); + err = -EINVAL; + goto err_bad_node; + } + + /* get the name */ + err = of_property_read_string(node, "gpio-name", &name); + if (err != 0) { + dev_err(dev, "Failed to get name property\n"); + goto err_bad_node; + } + + err = of_get_named_gpio_flags(node, "gpio", 0, &gpio_flags); + if (IS_ERR_VALUE(err)) { + dev_err(dev, "Failed to get gpio property of '%s'\n", name); + goto err_bad_node; + } + gpio = err; + + req_flags = 0; + count_flags = 0; + + /* set the request flags */ + switch (type) { + case GPIO_TYPE_INPUT: + req_flags = GPIOF_DIR_IN | GPIOF_EXPORT; + if (of_property_read_bool(node, "count-falling-edge")) + count_flags |= COUNT_FALLING_EDGE; + if (of_property_read_bool(node, "count-rising-edge")) + count_flags |= COUNT_RISING_EDGE; + break; + case GPIO_TYPE_OUTPUT: + req_flags = GPIOF_DIR_OUT | GPIOF_EXPORT; + if (of_property_read_bool(node, "init-high")) + req_flags |= GPIOF_OUT_INIT_HIGH; + else if (of_property_read_bool(node, "init-low")) + req_flags |= GPIOF_OUT_INIT_LOW; + break; + } + if (of_property_read_bool(node, "dir-changeable")) + req_flags |= GPIOF_EXPORT_CHANGEABLE; + + /* request the gpio */ + err = devm_gpio_request_one(dev, gpio, req_flags, name); + if (err != 0) { + dev_err(dev, "Failed to request gpio '%s'\n", name); + goto err_bad_node; + } + + irq = -1; + irq_flags = 0; + + /* counter mode requested - need an interrupt */ + if (count_flags != 0) { + irq = gpio_to_irq(gpio); + if (IS_ERR_VALUE(irq)) { + dev_err(dev, "Failed to request gpio '%s'\n", name); + goto err_bad_node; + } + + if (count_flags & COUNT_RISING_EDGE) + irq_flags |= IRQF_TRIGGER_RISING; + if (count_flags & COUNT_FALLING_EDGE) + irq_flags |= IRQF_TRIGGER_FALLING; + } + +// if (!idr_pre_get(&info->idr, GFP_KERNEL)) { +// dev_err(dev, "Failed on idr_pre_get of '%s'\n", name); +// err = -ENOMEM; +// goto err_no_mem; +// } + + idr_preload(GFP_KERNEL); + + entry = devm_kzalloc(dev, sizeof(*entry), GFP_KERNEL); + if (entry == NULL) { + dev_err(dev, "Failed to allocate gpio entry of '%s'\n", name); + err = -ENOMEM; + goto err_no_mem; + } + + entry->id = -1; + entry->info = info; + entry->node = of_node_get(node); /* get node reference */ + entry->type = type; + entry->gpio = gpio; + entry->gpio_flags = gpio_flags; + entry->irq = irq; + entry->name = name; + + /* interrupt enable is last thing done */ + if (irq >= 0) { + atomic64_set(&entry->counter, 0); + entry->count_flags = count_flags; + err = devm_request_irq(dev, irq, gpio_of_helper_handler, + irq_flags, name, entry); + if (err != 0) { + dev_err(dev, "Failed to request irq of '%s'\n", name); + goto err_no_irq; + } + } + + /* all done; insert */ +// err = idr_get_new(&info->idr, entry, &entry->id); +// if (IS_ERR_VALUE(err)) { +// dev_err(dev, "Failed to idr_get_new of '%s'\n", name); +// goto err_fail_idr; +// } + + err = idr_alloc(&info->idr, entry, 0, 0, GFP_NOWAIT); + if (err >= 0) + entry->id = err; + + idr_preload_end(); + + if (err < 0) { + dev_err(dev, "Failed to idr_get_new of '%s'\n", name); + goto err_fail_idr; + } + + dev_info(dev, "Allocated GPIO id=%d\n", entry->id); + + return entry; + +err_fail_idr: + /* nothing to do */ +err_no_irq: + /* release node ref */ + of_node_put(node); + /* nothing else needs to be done, devres handles it */ +err_no_mem: +err_bad_node: + return ERR_PTR(err); +} + +static int gpio_of_entry_destroy(struct gpio_of_entry *entry) +{ + struct gpio_of_helper_info *info = entry->info; + struct platform_device *pdev = info->pdev; + struct device *dev = &pdev->dev; + + dev_info(dev, "Destroying GPIO id=%d\n", entry->id); + + /* remove from the IDR */ + idr_remove(&info->idr, entry->id); + + /* remove node ref */ + of_node_put(entry->node); + + /* free gpio */ + devm_gpio_free(dev, entry->gpio); + + /* gree irq */ + if (entry->irq >= 0) + devm_free_irq(dev, entry->irq, entry); + + /* and free */ + devm_kfree(dev, entry); + + return 0; +} + +static int gpio_of_helper_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gpio_of_helper_info *info; + struct gpio_of_entry *entry; + struct device_node *pnode = pdev->dev.of_node; + struct device_node *cnode; + struct pinctrl *pinctrl; + int err; + + /* we only support OF */ + if (pnode == NULL) { + dev_err(&pdev->dev, "No platform of_node!\n"); + return -ENODEV; + } + + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + if (IS_ERR(pinctrl)) { + /* special handling for probe defer */ + if (PTR_ERR(pinctrl) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + dev_warn(&pdev->dev, + "pins are not configured from the driver\n"); + } + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (info == NULL) { + dev_err(&pdev->dev, "Failed to allocate info\n"); + err = -ENOMEM; + goto err_no_mem; + } + platform_set_drvdata(pdev, info); + info->pdev = pdev; + + idr_init(&info->idr); + + err = device_create_file(dev, &dev_attr_status); + if (err != 0) { + dev_err(dev, "Failed to create status sysfs attribute\n"); + goto err_no_sysfs; + } + + for_each_child_of_node(pnode, cnode) { + + entry = gpio_of_entry_create(info, cnode); + if (IS_ERR_OR_NULL(entry)) { + dev_err(dev, "Failed to create gpio entry\n"); + err = PTR_ERR(entry); + goto err_fail_entry; + } + } + + dev_info(&pdev->dev, "ready\n"); + + return 0; +err_fail_entry: + device_remove_file(&pdev->dev, &dev_attr_status); +err_no_sysfs: +err_no_mem: + return err; +} + +static int gpio_of_helper_remove(struct platform_device *pdev) +{ + struct gpio_of_helper_info *info = platform_get_drvdata(pdev); + struct gpio_of_entry *entry; + int id; + + dev_info(&pdev->dev, "removing\n"); + + device_remove_file(&pdev->dev, &dev_attr_status); + + id = 0; + idr_for_each_entry(&info->idr, entry, id) { + /* destroy each and every one */ + gpio_of_entry_destroy(entry); + } + + return 0; +} + +#ifdef CONFIG_PM +//#ifdef CONFIG_PM_RUNTIME +static int gpio_of_helper_runtime_suspend(struct device *dev) +{ + /* place holder */ + return 0; +} + +static int gpio_of_helper_runtime_resume(struct device *dev) +{ + /* place holder */ + return 0; +} +//#endif /* CONFIG_PM_RUNTIME */ + +static struct dev_pm_ops gpio_of_helper_pm_ops = { + SET_RUNTIME_PM_OPS(gpio_of_helper_runtime_suspend, + gpio_of_helper_runtime_resume, NULL) +}; +#define GPIO_OF_HELPER_PM_OPS (&gpio_of_helper_pm_ops) +#else +#define GPIO_OF_HELPER_PM_OPS NULL +#endif /* CONFIG_PM */ + +struct platform_driver gpio_of_helper_driver = { + .probe = gpio_of_helper_probe, + .remove = gpio_of_helper_remove, + .driver = { + .name = "gpio-of-helper", + .owner = THIS_MODULE, + .pm = GPIO_OF_HELPER_PM_OPS, + .of_match_table = gpio_of_helper_of_match, + }, +}; + +module_platform_driver(gpio_of_helper_driver); + +MODULE_AUTHOR("Pantelis Antoniou "); +MODULE_DESCRIPTION("GPIO OF Helper driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:gpio-of-helper"); diff -Naur --no-dereference a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c --- a/drivers/gpio/gpio-omap.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpio/gpio-omap.c 2016-05-11 13:31:53.197225234 -0400 @@ -69,7 +69,7 @@ struct device *dev; bool is_mpuio; bool dbck_flag; - bool loses_context; + bool context_valid; int stride; u32 width; @@ -612,51 +612,12 @@ omap_disable_gpio_irqbank(bank, BIT(offset)); } -/* - * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. - * 1510 does not seem to have a wake-up register. If JTAG is connected - * to the target, system will wake up always on GPIO events. While - * system is running all registered GPIO interrupts need to have wake-up - * enabled. When system is suspended, only selected GPIO interrupts need - * to have wake-up enabled. - */ -static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, - int enable) -{ - u32 gpio_bit = BIT(offset); - unsigned long flags; - - if (bank->non_wakeup_gpios & gpio_bit) { - dev_err(bank->dev, - "Unable to modify wakeup on non-wakeup GPIO%d\n", - offset); - return -EINVAL; - } - - raw_spin_lock_irqsave(&bank->lock, flags); - if (enable) - bank->context.wake_en |= gpio_bit; - else - bank->context.wake_en &= ~gpio_bit; - - writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); - raw_spin_unlock_irqrestore(&bank->lock, flags); - - return 0; -} - /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) { struct gpio_bank *bank = omap_irq_data_get_bank(d); - unsigned offset = d->hwirq; - int ret; - ret = omap_set_gpio_wakeup(bank, offset, enable); - if (!ret) - ret = irq_set_irq_wake(bank->irq, enable); - - return ret; + return irq_set_irq_wake(bank->irq, enable); } static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) @@ -1185,6 +1146,7 @@ irqc->irq_bus_lock = omap_gpio_irq_bus_lock, irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, irqc->name = dev_name(&pdev->dev); + irqc->flags = IRQCHIP_MASK_ON_SUSPEND; bank->irq = platform_get_irq(pdev, 0); if (bank->irq <= 0) { @@ -1208,15 +1170,9 @@ #ifdef CONFIG_OF_GPIO bank->chip.of_node = of_node_get(node); #endif - if (node) { - if (!of_property_read_bool(node, "ti,gpio-always-on")) - bank->loses_context = true; - } else { - bank->loses_context = pdata->loses_context; - - if (bank->loses_context) - bank->get_context_loss_count = - pdata->get_context_loss_count; + if (!node) { + bank->get_context_loss_count = + pdata->get_context_loss_count; } if (bank->regs->set_dataout && bank->regs->clr_dataout) @@ -1373,7 +1329,7 @@ * been initialised and so initialise it now. Also initialise * the context loss count. */ - if (bank->loses_context && !bank->context_valid) { + if (!bank->context_valid) { omap_gpio_init_context(bank); if (bank->get_context_loss_count) @@ -1394,17 +1350,13 @@ writel_relaxed(bank->context.risingdetect, bank->base + bank->regs->risingdetect); - if (bank->loses_context) { - if (!bank->get_context_loss_count) { - omap_gpio_restore_context(bank); - } else { - c = bank->get_context_loss_count(bank->dev); - if (c != bank->context_loss_count) { - omap_gpio_restore_context(bank); - } else { - raw_spin_unlock_irqrestore(&bank->lock, flags); - return 0; - } + if (!bank->get_context_loss_count) { + omap_gpio_restore_context(bank); + } else { + c = bank->get_context_loss_count(bank->dev); + if (c != bank->context_loss_count) { + raw_spin_unlock_irqrestore(&bank->lock, flags); + return 0; } } @@ -1476,7 +1428,7 @@ struct gpio_bank *bank; list_for_each_entry(bank, &omap_gpio_list, node) { - if (!BANK_USED(bank) || !bank->loses_context) + if (!BANK_USED(bank)) continue; bank->power_mode = pwr_mode; @@ -1490,7 +1442,7 @@ struct gpio_bank *bank; list_for_each_entry(bank, &omap_gpio_list, node) { - if (!BANK_USED(bank) || !bank->loses_context) + if (!BANK_USED(bank)) continue; pm_runtime_get_sync(bank->dev); diff -Naur --no-dereference a/drivers/gpio/gpio-pisosr.c b/drivers/gpio/gpio-pisosr.c --- a/drivers/gpio/gpio-pisosr.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpio/gpio-pisosr.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + */ + +#include +#include +#include +#include +#include +#include + +#define DEFAULT_NGPIO 8 + +/** + * struct pisosr_gpio - GPIO driver data + * @chip: GPIO controller chip + * @spi: SPI device pointer + * @buffer: Buffer for device reads + * @buffer_size: Size of buffer + * @load_gpio: GPIO pin used to load input into device + * @lock: Protects read sequences + */ +struct pisosr_gpio { + struct gpio_chip chip; + struct spi_device *spi; + u8 *buffer; + size_t buffer_size; + struct gpio_desc *load_gpio; + struct mutex lock; +}; + +static inline struct pisosr_gpio *to_pisosr_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct pisosr_gpio, chip); +} + +static int pisosr_gpio_refresh(struct pisosr_gpio *gpio) +{ + int ret; + + mutex_lock(&gpio->lock); + + if (gpio->load_gpio) { + gpiod_set_value_cansleep(gpio->load_gpio, 1); + udelay(1); /* registers load time (~10ns) */ + gpiod_set_value_cansleep(gpio->load_gpio, 0); + udelay(1); /* registers recovery time (~5ns) */ + } + + ret = spi_read(gpio->spi, gpio->buffer, gpio->buffer_size); + + mutex_unlock(&gpio->lock); + + return ret; +} + +static int pisosr_gpio_get_direction(struct gpio_chip *chip, + unsigned offset) +{ + /* This device always input */ + return 1; +} + +static int pisosr_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + /* This device always input */ + return 0; +} + +static int pisosr_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + /* This device is input only */ + return -EINVAL; +} + +static int pisosr_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct pisosr_gpio *gpio = to_pisosr_gpio(chip); + + /* Refresh may not always be needed */ + pisosr_gpio_refresh(gpio); + + return (gpio->buffer[offset / 8] >> (offset % 8)) & 0x1; +} + +static struct gpio_chip template_chip = { + .label = "pisosr-gpio", + .owner = THIS_MODULE, + .get_direction = pisosr_gpio_get_direction, + .direction_input = pisosr_gpio_direction_input, + .direction_output = pisosr_gpio_direction_output, + .get = pisosr_gpio_get, + .base = -1, + .ngpio = DEFAULT_NGPIO, + .can_sleep = true, +}; + +static int pisosr_gpio_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct pisosr_gpio *gpio; + int ret; + + gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + spi_set_drvdata(spi, gpio); + + gpio->chip = template_chip; + gpio->chip.dev = dev; + of_property_read_u16(dev->of_node, "ngpios", &gpio->chip.ngpio); + + gpio->spi = spi; + + gpio->buffer_size = DIV_ROUND_UP(gpio->chip.ngpio, 8); + gpio->buffer = devm_kzalloc(dev, gpio->buffer_size, GFP_KERNEL); + if (!gpio->buffer) + return -ENOMEM; + + gpio->load_gpio = devm_gpiod_get_optional(dev, "load", GPIOD_OUT_LOW); + if (IS_ERR(gpio->load_gpio)) { + ret = PTR_ERR(gpio->load_gpio); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Unable to allocate load GPIO\n"); + return ret; + } + + mutex_init(&gpio->lock); + + ret = gpiochip_add(&gpio->chip); + if (ret < 0) { + dev_err(dev, "Unable to register gpiochip\n"); + return ret; + } + + return 0; +} + +static int pisosr_gpio_remove(struct spi_device *spi) +{ + struct pisosr_gpio *gpio = spi_get_drvdata(spi); + + gpiochip_remove(&gpio->chip); + + mutex_destroy(&gpio->lock); + + return 0; +} + +static const struct spi_device_id pisosr_gpio_id_table[] = { + { "pisosr-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, pisosr_gpio_id_table); + +static const struct of_device_id pisosr_gpio_of_match_table[] = { + { .compatible = "pisosr-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pisosr_gpio_of_match_table); + +static struct spi_driver pisosr_gpio_driver = { + .driver = { + .name = "pisosr-gpio", + .of_match_table = pisosr_gpio_of_match_table, + }, + .probe = pisosr_gpio_probe, + .remove = pisosr_gpio_remove, + .id_table = pisosr_gpio_id_table, +}; +module_spi_driver(pisosr_gpio_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_DESCRIPTION("SPI Compatible PISO Shift Register GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Naur --no-dereference a/drivers/gpio/gpio-tpic2810.c b/drivers/gpio/gpio-tpic2810.c --- a/drivers/gpio/gpio-tpic2810.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpio/gpio-tpic2810.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + */ + +#include +#include +#include +#include + +#define TPIC2810_WS_COMMAND 0x44 + +/** + * struct tpic2810 - GPIO driver data + * @chip: GPIO controller chip + * @client: I2C device pointer + * @buffer: Buffer for device register + * @lock: Protects write sequences + */ +struct tpic2810 { + struct gpio_chip chip; + struct i2c_client *client; + u8 buffer; + struct mutex lock; +}; + +static inline struct tpic2810 *to_tpic2810(struct gpio_chip *chip) +{ + return container_of(chip, struct tpic2810, chip); +} + +static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value); + +static int tpic2810_get_direction(struct gpio_chip *chip, + unsigned offset) +{ + /* This device always output */ + return 0; +} + +static int tpic2810_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + /* This device is output only */ + return -EINVAL; +} + +static int tpic2810_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + /* This device always output */ + tpic2810_set(chip, offset, value); + return 0; +} + +static void tpic2810_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct tpic2810 *gpio = to_tpic2810(chip); + + mutex_lock(&gpio->lock); + + if (value) + gpio->buffer |= BIT(offset); + else + gpio->buffer &= ~BIT(offset); + + i2c_smbus_write_byte_data(gpio->client, TPIC2810_WS_COMMAND, + gpio->buffer); + + mutex_unlock(&gpio->lock); +} + +static void tpic2810_set_multiple(struct gpio_chip *chip, unsigned long *mask, + unsigned long *bits) +{ + struct tpic2810 *gpio = to_tpic2810(chip); + + mutex_lock(&gpio->lock); + + /* clear bits under mask */ + gpio->buffer &= ~(*mask); + /* set bits under mask */ + gpio->buffer |= ((*mask) & (*bits)); + + i2c_smbus_write_byte_data(gpio->client, TPIC2810_WS_COMMAND, + gpio->buffer); + + mutex_unlock(&gpio->lock); +} + +static struct gpio_chip template_chip = { + .label = "tpic2810", + .owner = THIS_MODULE, + .get_direction = tpic2810_get_direction, + .direction_input = tpic2810_direction_input, + .direction_output = tpic2810_direction_output, + .set = tpic2810_set, + .set_multiple = tpic2810_set_multiple, + .base = -1, + .ngpio = 8, + .can_sleep = true, +}; + +static const struct of_device_id tpic2810_of_match_table[] = { + { .compatible = "ti,tpic2810" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tpic2810_of_match_table); + +static int tpic2810_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct tpic2810 *gpio; + int ret; + + gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + i2c_set_clientdata(client, gpio); + + gpio->chip = template_chip; + gpio->chip.dev = &client->dev; + + gpio->client = client; + + mutex_init(&gpio->lock); + + ret = gpiochip_add(&gpio->chip); + if (ret < 0) { + dev_err(&client->dev, "Unable to register gpiochip\n"); + return ret; + } + + return 0; +} + +static int tpic2810_remove(struct i2c_client *client) +{ + struct tpic2810 *gpio = i2c_get_clientdata(client); + + gpiochip_remove(&gpio->chip); + + return 0; +} + +static const struct i2c_device_id tpic2810_id_table[] = { + { "tpic2810", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, tpic2810_id_table); + +static struct i2c_driver tpic2810_driver = { + .driver = { + .name = "tpic2810", + .of_match_table = tpic2810_of_match_table, + }, + .probe = tpic2810_probe, + .remove = tpic2810_remove, + .id_table = tpic2810_id_table, +}; +module_i2c_driver(tpic2810_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_DESCRIPTION("TPIC2810 8-Bit LED Driver GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Naur --no-dereference a/drivers/gpio/gpio-tps65086.c b/drivers/gpio/gpio-tps65086.c --- a/drivers/gpio/gpio-tps65086.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpio/gpio-tps65086.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * Based on the TPS65912 driver + */ + +#include +#include +#include + +#include + +struct tps65086_gpio { + struct gpio_chip chip; + struct tps65086 *tps; +}; + +static inline struct tps65086_gpio *to_tps65086_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct tps65086_gpio, chip); +} + +static int tps65086_gpio_get_direction(struct gpio_chip *chip, + unsigned offset) +{ + /* This device is output only */ + return 0; +} + +static int tps65086_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + /* This device is output only */ + return -EINVAL; +} + +static int tps65086_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct tps65086_gpio *gpio = to_tps65086_gpio(chip); + + /* Set the initial value */ + regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL, + BIT(4 + offset), value ? BIT(4 + offset) : 0); + + return 0; +} + +static int tps65086_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct tps65086_gpio *gpio = to_tps65086_gpio(chip); + int ret, val; + + ret = regmap_read(gpio->tps->regmap, TPS65086_GPOCTRL, &val); + if (ret < 0) + return ret; + + return val & BIT(4 + offset); +} + +static void tps65086_gpio_set(struct gpio_chip *chip, unsigned offset, + int value) +{ + struct tps65086_gpio *gpio = to_tps65086_gpio(chip); + + regmap_update_bits(gpio->tps->regmap, TPS65086_GPOCTRL, + BIT(4 + offset), value ? BIT(4 + offset) : 0); +} + +static struct gpio_chip template_chip = { + .label = "tps65086-gpio", + .owner = THIS_MODULE, + .get_direction = tps65086_gpio_get_direction, + .direction_input = tps65086_gpio_direction_input, + .direction_output = tps65086_gpio_direction_output, + .get = tps65086_gpio_get, + .set = tps65086_gpio_set, + .base = -1, + .ngpio = 4, + .can_sleep = true, +}; + +static int tps65086_gpio_probe(struct platform_device *pdev) +{ + struct tps65086_gpio *gpio; + int ret; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) + return -ENOMEM; + + platform_set_drvdata(pdev, gpio); + + gpio->tps = dev_get_drvdata(pdev->dev.parent); + gpio->chip = template_chip; + gpio->chip.dev = gpio->tps->dev; + + ret = gpiochip_add(&gpio->chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); + return ret; + } + + return 0; +} + +static int tps65086_gpio_remove(struct platform_device *pdev) +{ + struct tps65086_gpio *gpio = platform_get_drvdata(pdev); + + gpiochip_remove(&gpio->chip); + + return 0; +} + +static const struct platform_device_id tps65086_gpio_id_table[] = { + { "tps65086-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, tps65086_gpio_id_table); + +static struct platform_driver tps65086_gpio_driver = { + .driver = { + .name = "tps65086-gpio", + }, + .probe = tps65086_gpio_probe, + .remove = tps65086_gpio_remove, + .id_table = tps65086_gpio_id_table, +}; +module_platform_driver(tps65086_gpio_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_DESCRIPTION("TPS65086 GPIO driver"); +MODULE_LICENSE("GPL v2"); diff -Naur --no-dereference a/drivers/gpio/gpio-tps65912.c b/drivers/gpio/gpio-tps65912.c --- a/drivers/gpio/gpio-tps65912.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpio/gpio-tps65912.c 2016-05-11 13:31:53.197225234 -0400 @@ -1,153 +1,163 @@ /* - * Copyright 2011 Texas Instruments Inc. + * GPIO driver for TI TPS65912x PMICs * - * Author: Margarita Olaya + * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. * - * This driver is based on wm8350 implementation. + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether expressed or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License version 2 for more details. + * + * Based on the Arizona GPIO driver and the previous TPS65912 driver by + * Margarita Olaya Cabrera */ -#include -#include -#include #include -#include +#include #include -#include -#include + #include -struct tps65912_gpio_data { - struct tps65912 *tps65912; +struct tps65912_gpio { struct gpio_chip gpio_chip; + struct tps65912 *tps; }; -#define to_tgd(gc) container_of(gc, struct tps65912_gpio_data, gpio_chip) +static inline struct tps65912_gpio *to_tps65912_gpio(struct gpio_chip *chip) +{ + return container_of(chip, struct tps65912_gpio, gpio_chip); +} -static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset) +static int tps65912_gpio_get_direction(struct gpio_chip *gc, + unsigned offset) { - struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc); - struct tps65912 *tps65912 = tps65912_gpio->tps65912; - int val; + struct tps65912_gpio *gpio = to_tps65912_gpio(gc); - val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset); + int ret, val; - if (val & GPIO_STS_MASK) - return 1; + ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val); + if (ret) + return ret; - return 0; + if (val & GPIO_CFG_MASK) + return GPIOF_DIR_OUT; + else + return GPIOF_DIR_IN; } -static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset, - int value) +static int tps65912_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { - struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc); - struct tps65912 *tps65912 = tps65912_gpio->tps65912; + struct tps65912_gpio *gpio = to_tps65912_gpio(gc); - if (value) - tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset, - GPIO_SET_MASK); - else - tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset, - GPIO_SET_MASK); + return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset, + GPIO_CFG_MASK, 0); } -static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset, - int value) +static int tps65912_gpio_direction_output(struct gpio_chip *gc, + unsigned offset, int value) { - struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc); - struct tps65912 *tps65912 = tps65912_gpio->tps65912; + struct tps65912_gpio *gpio = to_tps65912_gpio(gc); /* Set the initial value */ - tps65912_gpio_set(gc, offset, value); + regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset, + GPIO_SET_MASK, value ? GPIO_SET_MASK : 0); + + return regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset, + GPIO_CFG_MASK, GPIO_CFG_MASK); +} + +static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset) +{ + struct tps65912_gpio *gpio = to_tps65912_gpio(gc); + int ret, val; + + ret = regmap_read(gpio->tps->regmap, TPS65912_GPIO1 + offset, &val); + if (ret) + return ret; + + if (val & GPIO_STS_MASK) + return 1; - return tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset, - GPIO_CFG_MASK); + return 0; } -static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset) +static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset, + int value) { - struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc); - struct tps65912 *tps65912 = tps65912_gpio->tps65912; + struct tps65912_gpio *gpio = to_tps65912_gpio(gc); - return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset, - GPIO_CFG_MASK); + regmap_update_bits(gpio->tps->regmap, TPS65912_GPIO1 + offset, + GPIO_SET_MASK, value ? GPIO_SET_MASK : 0); } static struct gpio_chip template_chip = { - .label = "tps65912", + .label = "tps65912-gpio", .owner = THIS_MODULE, - .direction_input = tps65912_gpio_input, - .direction_output = tps65912_gpio_output, + .get_direction = tps65912_gpio_get_direction, + .direction_input = tps65912_gpio_direction_input, + .direction_output = tps65912_gpio_direction_output, .get = tps65912_gpio_get, .set = tps65912_gpio_set, - .can_sleep = true, - .ngpio = 5, .base = -1, + .ngpio = 5, + .can_sleep = true, }; static int tps65912_gpio_probe(struct platform_device *pdev) { - struct tps65912 *tps65912 = dev_get_drvdata(pdev->dev.parent); - struct tps65912_board *pdata = dev_get_platdata(tps65912->dev); - struct tps65912_gpio_data *tps65912_gpio; + struct tps65912 *tps = dev_get_drvdata(pdev->dev.parent); + struct tps65912_gpio *gpio; int ret; - tps65912_gpio = devm_kzalloc(&pdev->dev, sizeof(*tps65912_gpio), - GFP_KERNEL); - if (tps65912_gpio == NULL) + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) return -ENOMEM; - tps65912_gpio->tps65912 = tps65912; - tps65912_gpio->gpio_chip = template_chip; - tps65912_gpio->gpio_chip.dev = &pdev->dev; - if (pdata && pdata->gpio_base) - tps65912_gpio->gpio_chip.base = pdata->gpio_base; + gpio->tps = dev_get_drvdata(pdev->dev.parent); + gpio->gpio_chip = template_chip; + gpio->gpio_chip.dev = tps->dev; - ret = gpiochip_add(&tps65912_gpio->gpio_chip); + ret = gpiochip_add(&gpio->gpio_chip); if (ret < 0) { - dev_err(&pdev->dev, "Failed to register gpiochip, %d\n", ret); + dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); return ret; } - platform_set_drvdata(pdev, tps65912_gpio); + platform_set_drvdata(pdev, gpio); - return ret; + return 0; } static int tps65912_gpio_remove(struct platform_device *pdev) { - struct tps65912_gpio_data *tps65912_gpio = platform_get_drvdata(pdev); + struct tps65912_gpio *gpio = platform_get_drvdata(pdev); + + gpiochip_remove(&gpio->gpio_chip); - gpiochip_remove(&tps65912_gpio->gpio_chip); return 0; } +static const struct platform_device_id tps65912_gpio_id_table[] = { + { "tps65912-gpio", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(platform, tps65912_gpio_id_table); + static struct platform_driver tps65912_gpio_driver = { .driver = { .name = "tps65912-gpio", }, .probe = tps65912_gpio_probe, .remove = tps65912_gpio_remove, + .id_table = tps65912_gpio_id_table, }; +module_platform_driver(tps65912_gpio_driver); -static int __init tps65912_gpio_init(void) -{ - return platform_driver_register(&tps65912_gpio_driver); -} -subsys_initcall(tps65912_gpio_init); - -static void __exit tps65912_gpio_exit(void) -{ - platform_driver_unregister(&tps65912_gpio_driver); -} -module_exit(tps65912_gpio_exit); - -MODULE_AUTHOR("Margarita Olaya Cabrera "); -MODULE_DESCRIPTION("GPIO interface for TPS65912 PMICs"); +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_DESCRIPTION("TPS65912 GPIO driver"); MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:tps65912-gpio"); diff -Naur --no-dereference a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig --- a/drivers/gpio/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpio/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -85,6 +85,20 @@ Kernel drivers may also request that a particular GPIO be exported to userspace; this can be useful when debugging. +config GPIO_OF_HELPER + bool "GPIO OF helper device (EXPERIMENTAL)" + depends on OF_GPIO + help + Say Y here to add an GPIO OF helper driver + + Allows you specify a GPIO helper based on OF + which allows simple export of GPIO functionality + in user-space. + + Features include, value set/get, direction control, + interrupt/value change poll support, event counting + and others. + config GPIO_GENERIC tristate @@ -696,6 +710,14 @@ 8 bits: sx1508q 16 bits: sx1509q +config GPIO_TPIC2810 + tristate "TPIC2810 8-Bit I2C GPO expander" + help + Say yes here to enable the GPO driver for the TI TPIC2810 chip. + + To compile this driver as a module, choose M here: the module will + be called gpio-tpic2810. + endmenu menu "MFD GPIO expanders" @@ -838,6 +860,12 @@ ---help--- Add support for the GPIO IP in the timberdale FPGA. +config GPIO_TPS65086 + tristate "TI TPS65086 GPO" + depends on MFD_TPS65086 + help + This driver supports the GPO on TI TPS65086x PMICs. + config GPIO_TPS6586X bool "TPS6586X GPIO" depends on MFD_TPS6586X @@ -854,7 +882,7 @@ config GPIO_TPS65912 tristate "TI TPS65912 GPIO" - depends on (MFD_TPS65912_I2C || MFD_TPS65912_SPI) + depends on MFD_TPS65912 help This driver supports TPS65912 gpio chip @@ -1008,6 +1036,12 @@ SPI driver for Freescale MC33880 high-side/low-side switch. This provides GPIO interface supporting inputs and outputs. +config GPIO_PISOSR + tristate "Generic parallel-in/serial-out shift register" + help + GPIO driver for SPI compatible parallel-in/serial-out shift + registers. These are input only devices. + endmenu menu "SPI or I2C GPIO expanders" diff -Naur --no-dereference a/drivers/gpio/Makefile b/drivers/gpio/Makefile --- a/drivers/gpio/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpio/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -8,6 +8,7 @@ obj-$(CONFIG_OF_GPIO) += gpiolib-of.o obj-$(CONFIG_GPIO_SYSFS) += gpiolib-sysfs.o obj-$(CONFIG_GPIO_ACPI) += gpiolib-acpi.o +obj-$(CONFIG_GPIO_OF_HELPER) += gpio-of-helper.o # Device drivers. Generally keep list sorted alphabetically obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o @@ -74,6 +75,7 @@ obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o obj-$(CONFIG_GPIO_PCH) += gpio-pch.o +obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o @@ -95,6 +97,8 @@ obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o obj-$(CONFIG_GPIO_PALMAS) += gpio-palmas.o +obj-$(CONFIG_GPIO_TPS65086) += gpio-tps65086.o +obj-$(CONFIG_GPIO_TPIC2810) += gpio-tpic2810.o obj-$(CONFIG_GPIO_TPS6586X) += gpio-tps6586x.o obj-$(CONFIG_GPIO_TPS65910) += gpio-tps65910.o obj-$(CONFIG_GPIO_TPS65912) += gpio-tps65912.o diff -Naur --no-dereference a/drivers/gpu/drm/i2c/adihdmi_drv.c b/drivers/gpu/drm/i2c/adihdmi_drv.c --- a/drivers/gpu/drm/i2c/adihdmi_drv.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpu/drm/i2c/adihdmi_drv.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,1282 @@ +/* + * Analog Devices ADIHDMI HDMI transmitter driver + * + * Copyright 2012 Analog Devices Inc. + * Copyright 2015 Konsulko Group + * + * Licensed under the GPL-2. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "adihdmi.h" + +#define ADIHDMI_INFOFRAME_PACKETS (0x7900) + +struct adihdmi { + struct i2c_client *i2c_main; + struct i2c_client *i2c_edid; + + struct regmap *regmap; + struct regmap *packet_memory_regmap; + enum drm_connector_status status; + bool powered; + + unsigned int f_tmds; + + unsigned int current_edid_segment; + uint8_t edid_buf[256]; + bool edid_read; + + wait_queue_head_t wq; + struct drm_encoder *encoder; + + bool embedded_sync; + enum adihdmi_sync_polarity vsync_polarity; + enum adihdmi_sync_polarity hsync_polarity; + bool rgb; + + struct edid *edid; + + struct gpio_desc *gpio_pd; +}; + +struct adihdmi2 { + struct adihdmi base; + struct drm_encoder encoder; + struct drm_connector connector; +}; + +/* ADI recommended values for proper operation. */ +static const struct reg_sequence adihdmi_fixed_registers[] = { + { 0x98, 0x03 }, + { 0x9a, 0xe0 }, + { 0x9c, 0x30 }, + { 0x9d, 0x61 }, + { 0xa2, 0xa4 }, + { 0xa3, 0xa4 }, + { 0xe0, 0xd0 }, + { 0xf9, 0x00 }, + { 0x55, 0x02 }, +}; + +/* ----------------------------------------------------------------------------- + * Register access + */ + +static const uint8_t adihdmi_register_defaults[] = { + 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 */ + 0x00, 0x00, 0x01, 0x0e, 0xbc, 0x18, 0x01, 0x13, + 0x25, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 10 */ + 0x46, 0x62, 0x04, 0xa8, 0x00, 0x00, 0x1c, 0x84, + 0x1c, 0xbf, 0x04, 0xa8, 0x1e, 0x70, 0x02, 0x1e, /* 20 */ + 0x00, 0x00, 0x04, 0xa8, 0x08, 0x12, 0x1b, 0xac, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 */ + 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xb0, + 0x00, 0x50, 0x90, 0x7e, 0x79, 0x70, 0x00, 0x00, /* 40 */ + 0x00, 0xa8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x0d, 0x00, 0x00, 0x00, 0x00, /* 50 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 60 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 70 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 80 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, /* 90 */ + 0x0b, 0x02, 0x00, 0x18, 0x5a, 0x60, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x80, 0x08, 0x04, 0x00, 0x00, /* a0 */ + 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c0 */ + 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x01, 0x04, + 0x30, 0xff, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, /* d0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, + 0x80, 0x75, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, /* e0 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x11, 0x00, /* f0 */ + 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static bool adihdmi_register_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ADIHDMI_REG_CHIP_REVISION: + case ADIHDMI_REG_SPDIF_FREQ: + case ADIHDMI_REG_CTS_AUTOMATIC1: + case ADIHDMI_REG_CTS_AUTOMATIC2: + case ADIHDMI_REG_VIC_DETECTED: + case ADIHDMI_REG_VIC_SEND: + case ADIHDMI_REG_AUX_VIC_DETECTED: + case ADIHDMI_REG_STATUS: + case ADIHDMI_REG_GC(1): + case ADIHDMI_REG_INT(0): + case ADIHDMI_REG_INT(1): + case ADIHDMI_REG_PLL_STATUS: + case ADIHDMI_REG_AN(0): + case ADIHDMI_REG_AN(1): + case ADIHDMI_REG_AN(2): + case ADIHDMI_REG_AN(3): + case ADIHDMI_REG_AN(4): + case ADIHDMI_REG_AN(5): + case ADIHDMI_REG_AN(6): + case ADIHDMI_REG_AN(7): + case ADIHDMI_REG_HDCP_STATUS: + case ADIHDMI_REG_BCAPS: + case ADIHDMI_REG_BKSV(0): + case ADIHDMI_REG_BKSV(1): + case ADIHDMI_REG_BKSV(2): + case ADIHDMI_REG_BKSV(3): + case ADIHDMI_REG_BKSV(4): + case ADIHDMI_REG_DDC_STATUS: + case ADIHDMI_REG_BSTATUS(0): + case ADIHDMI_REG_BSTATUS(1): + case ADIHDMI_REG_CHIP_ID_HIGH: + case ADIHDMI_REG_CHIP_ID_LOW: + return true; + } + + return false; +} + +static const struct regmap_config adihdmi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + + .max_register = 0xff, + .cache_type = REGCACHE_RBTREE, + .reg_defaults_raw = adihdmi_register_defaults, + .num_reg_defaults_raw = ARRAY_SIZE(adihdmi_register_defaults), + + .volatile_reg = adihdmi_register_volatile, +}; + +/* ----------------------------------------------------------------------------- + * Hardware configuration + */ + + static void adihdmi_audio_setup(struct adihdmi * adihdmi) +{ + /* Select I2S. */ + regmap_write(adihdmi->regmap, ADIHDMI_REG_AUDIO_SOURCE, 0x01); + regmap_write(adihdmi->regmap, ADIHDMI_REG_I2S_CONFIG, 0x84); + + /* Setup clocks for 48KHz. */ + regmap_write(adihdmi->regmap, ADIHDMI_REG_N0, 0x00); + regmap_write(adihdmi->regmap, ADIHDMI_REG_N1, 0x18); + regmap_write(adihdmi->regmap, ADIHDMI_REG_N2, 0x00); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_I2C_FREQ_ID_CFG, 0xF0, 0x20); + + /* Set audio word length to 24 bits. */ + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_AUDIO_CFG3, 0x0F, 0x0B); + + /* Update audio infoframe. */ + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_INFOFRAME_UPDATE, 0x20, 0x20); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_AUDIO_INFOFRAME(0), 0x07, 0x01); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_AUDIO_INFOFRAME(3), 0x1F, 0x00); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_INFOFRAME_UPDATE, 0x20, 0x00); +} + +static void adihdmi_set_colormap(struct adihdmi *adihdmi, bool enable, + const uint16_t *coeff, + unsigned int scaling_factor) +{ + unsigned int i; + + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_CSC_UPPER(1), + ADIHDMI_CSC_UPDATE_MODE, ADIHDMI_CSC_UPDATE_MODE); + + if (enable) { + for (i = 0; i < 12; ++i) { + regmap_update_bits(adihdmi->regmap, + ADIHDMI_REG_CSC_UPPER(i), + 0x1f, coeff[i] >> 8); + regmap_write(adihdmi->regmap, + ADIHDMI_REG_CSC_LOWER(i), + coeff[i] & 0xff); + } + } + + if (enable) + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_CSC_UPPER(0), + 0xe0, 0x80 | (scaling_factor << 5)); + else + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_CSC_UPPER(0), + 0x80, 0x00); + + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_CSC_UPPER(1), + ADIHDMI_CSC_UPDATE_MODE, 0); +} + +static int adihdmi_packet_enable(struct adihdmi *adihdmi, unsigned int packet) +{ + if (packet & 0xff) + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_PACKET_ENABLE0, + packet, 0xff); + + if (packet & 0xff00) { + packet >>= 8; + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_PACKET_ENABLE1, + packet, 0xff); + } + + return 0; +} + +static int adihdmi_packet_disable(struct adihdmi *adihdmi, unsigned int packet) +{ + if (packet & 0xff) + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_PACKET_ENABLE0, + packet, 0x00); + + if (packet & 0xff00) { + packet >>= 8; + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_PACKET_ENABLE1, + packet, 0x00); + } + + return 0; +} + +/* Coefficients for adihdmi color space conversion */ +static const uint16_t adihdmi_csc_ycbcr_to_rgb[] = { + 0x0734, 0x04ad, 0x0000, 0x1c1b, + 0x1ddc, 0x04ad, 0x1f24, 0x0135, + 0x0000, 0x04ad, 0x087c, 0x1b77, +}; + +static void adihdmi_set_config_csc(struct adihdmi *adihdmi, + struct drm_connector *connector, + bool rgb) +{ + struct adihdmi_video_config config; + bool output_format_422, output_format_ycbcr; + unsigned int mode; + uint8_t infoframe[17]; + + if (adihdmi->edid) + config.hdmi_mode = drm_detect_hdmi_monitor(adihdmi->edid); + else + config.hdmi_mode = false; + + hdmi_avi_infoframe_init(&config.avi_infoframe); + + config.avi_infoframe.scan_mode = HDMI_SCAN_MODE_UNDERSCAN; + + if (rgb) { + config.csc_enable = false; + config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB; + } else { + config.csc_scaling_factor = ADIHDMI_CSC_SCALING_4; + config.csc_coefficents = adihdmi_csc_ycbcr_to_rgb; + + if ((connector->display_info.color_formats & + DRM_COLOR_FORMAT_YCRCB422) && + config.hdmi_mode) { + config.csc_enable = false; + config.avi_infoframe.colorspace = + HDMI_COLORSPACE_YUV422; + } else { + config.csc_enable = true; + config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB; + } + } + + if (config.hdmi_mode) { + mode = ADIHDMI_HDMI_CFG_MODE_HDMI; + + switch (config.avi_infoframe.colorspace) { + case HDMI_COLORSPACE_YUV444: + output_format_422 = false; + output_format_ycbcr = true; + break; + case HDMI_COLORSPACE_YUV422: + output_format_422 = true; + output_format_ycbcr = true; + break; + default: + output_format_422 = false; + output_format_ycbcr = false; + break; + } + } else { + mode = ADIHDMI_HDMI_CFG_MODE_DVI; + output_format_422 = false; + output_format_ycbcr = false; + } + + adihdmi_packet_disable(adihdmi, ADIHDMI_INFOFRAME_PACKETS); + + adihdmi_set_colormap(adihdmi, config.csc_enable, + config.csc_coefficents, + config.csc_scaling_factor); + + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_VIDEO_INPUT_CFG1, 0x81, + (output_format_422 << 7) | output_format_ycbcr); + + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_HDCP_HDMI_CFG, + ADIHDMI_HDMI_CFG_MODE_MASK, mode); + + hdmi_avi_infoframe_pack(&config.avi_infoframe, infoframe, + sizeof(infoframe)); + + /* The AVI infoframe id is not configurable */ + regmap_bulk_write(adihdmi->regmap, ADIHDMI_REG_AVI_INFOFRAME_VERSION, + infoframe + 1, sizeof(infoframe) - 1); + + adihdmi_packet_enable(adihdmi, ADIHDMI_INFOFRAME_PACKETS); +} + +static void adihdmi_set_link_config(struct adihdmi *adihdmi, + const struct adihdmi_link_config *config) +{ + /* + * The input style values documented in the datasheet don't match the + * hardware register field values :-( + */ + static const unsigned int input_styles[4] = { 0, 2, 1, 3 }; + + unsigned int clock_delay; + unsigned int color_depth; + unsigned int input_id; + + clock_delay = (config->clock_delay + 1200) / 400; + color_depth = config->input_color_depth == 8 ? 3 + : (config->input_color_depth == 10 ? 1 : 2); + + /* TODO Support input ID 6 */ + if (config->input_colorspace != HDMI_COLORSPACE_YUV422) + input_id = config->input_clock == ADIHDMI_INPUT_CLOCK_DDR + ? 5 : 0; + else if (config->input_clock == ADIHDMI_INPUT_CLOCK_DDR) + input_id = config->embedded_sync ? 8 : 7; + else if (config->input_clock == ADIHDMI_INPUT_CLOCK_2X) + input_id = config->embedded_sync ? 4 : 3; + else + input_id = config->embedded_sync ? 2 : 1; + + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_I2C_FREQ_ID_CFG, 0xf, + input_id); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_VIDEO_INPUT_CFG1, 0x7e, + (color_depth << 4) | + (input_styles[config->input_style] << 2)); + regmap_write(adihdmi->regmap, ADIHDMI_REG_VIDEO_INPUT_CFG2, + config->input_justification << 3); + regmap_write(adihdmi->regmap, ADIHDMI_REG_TIMING_GEN_SEQ, + config->sync_pulse << 2); + + regmap_write(adihdmi->regmap, 0xba, clock_delay << 5); + + adihdmi->embedded_sync = config->embedded_sync; + adihdmi->hsync_polarity = config->hsync_polarity; + adihdmi->vsync_polarity = config->vsync_polarity; + adihdmi->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB; +} + +static void adihdmi_power_on(struct adihdmi *adihdmi) +{ + adihdmi->current_edid_segment = -1; + + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(0), + ADIHDMI_INT0_EDID_READY); + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(1), + ADIHDMI_INT1_DDC_ERROR); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER, + ADIHDMI_POWER_POWER_DOWN, 0); + + /* + * Per spec it is allowed to pulse the HDP signal to indicate that the + * EDID information has changed. Some monitors do this when they wakeup + * from standby or are enabled. When the HDP goes low the adihdmi is + * reset and the outputs are disabled which might cause the monitor to + * go to standby again. To avoid this we ignore the HDP pin for the + * first few seconds after enabling the output. + */ + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER2, + ADIHDMI_REG_POWER2_HDP_SRC_MASK, + ADIHDMI_REG_POWER2_HDP_SRC_NONE); + + /* + * Most of the registers are reset during power down or when HPD is low. + */ + regcache_sync(adihdmi->regmap); + + adihdmi->powered = true; +} + +static void adihdmi_power_off(struct adihdmi *adihdmi) +{ + /* TODO: setup additional power down modes */ + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER, + ADIHDMI_POWER_POWER_DOWN, + ADIHDMI_POWER_POWER_DOWN); + regcache_mark_dirty(adihdmi->regmap); + + adihdmi->powered = false; +} + +/* ----------------------------------------------------------------------------- + * Interrupt and hotplug detection + */ + +static bool adihdmi_hpd(struct adihdmi *adihdmi) +{ + unsigned int irq0; + int ret; + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_INT(0), &irq0); + if (ret < 0) + return false; + + if (irq0 & ADIHDMI_INT0_HDP) { + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(0), + ADIHDMI_INT0_HDP); + return true; + } + + return false; +} + +static int adihdmi_irq_process(struct adihdmi *adihdmi) +{ + unsigned int irq0, irq1; + int ret; + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_INT(0), &irq0); + if (ret < 0) + return ret; + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_INT(1), &irq1); + if (ret < 0) + return ret; + + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(0), irq0); + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(1), irq1); + + if (irq0 & ADIHDMI_INT0_HDP) + drm_helper_hpd_irq_event(adihdmi->encoder->dev); + + if (irq0 & ADIHDMI_INT0_EDID_READY || irq1 & ADIHDMI_INT1_DDC_ERROR) { + adihdmi->edid_read = true; + + if (adihdmi->i2c_main->irq) + wake_up_all(&adihdmi->wq); + } + + return 0; +} + +static irqreturn_t adihdmi_irq_handler(int irq, void *devid) +{ + struct adihdmi *adihdmi = devid; + int ret; + + ret = adihdmi_irq_process(adihdmi); + return ret < 0 ? IRQ_NONE : IRQ_HANDLED; +} + +/* ----------------------------------------------------------------------------- + * EDID retrieval + */ + +static int adihdmi_wait_for_edid(struct adihdmi *adihdmi, int timeout) +{ + int ret; + + if (adihdmi->i2c_main->irq) { + ret = wait_event_interruptible_timeout(adihdmi->wq, + adihdmi->edid_read, msecs_to_jiffies(timeout)); + } else { + for (; timeout > 0; timeout -= 25) { + ret = adihdmi_irq_process(adihdmi); + if (ret < 0) + break; + + if (adihdmi->edid_read) + break; + + msleep(25); + } + } + + return adihdmi->edid_read ? 0 : -EIO; +} + +static int adihdmi_get_edid_block(void *data, u8 *buf, unsigned int block, + size_t len) +{ + struct adihdmi *adihdmi = data; + struct i2c_msg xfer[2]; + uint8_t offset; + unsigned int i; + int ret; + + if (len > 128) + return -EINVAL; + + if (adihdmi->current_edid_segment != block / 2) { + unsigned int status; + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_DDC_STATUS, + &status); + if (ret < 0) + return ret; + + if (status != 2) { + adihdmi->edid_read = false; + regmap_write(adihdmi->regmap, ADIHDMI_REG_EDID_SEGMENT, + block); + ret = adihdmi_wait_for_edid(adihdmi, 200); + if (ret < 0) + return ret; + } + + /* Break this apart, hopefully more I2C controllers will + * support 64 byte transfers than 256 byte transfers + */ + + xfer[0].addr = adihdmi->i2c_edid->addr; + xfer[0].flags = 0; + xfer[0].len = 1; + xfer[0].buf = &offset; + xfer[1].addr = adihdmi->i2c_edid->addr; + xfer[1].flags = I2C_M_RD; + xfer[1].len = 64; + xfer[1].buf = adihdmi->edid_buf; + + offset = 0; + + for (i = 0; i < 4; ++i) { + ret = i2c_transfer(adihdmi->i2c_edid->adapter, xfer, + ARRAY_SIZE(xfer)); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + + xfer[1].buf += 64; + offset += 64; + } + + adihdmi->current_edid_segment = block / 2; + } + + if (block % 2 == 0) + memcpy(buf, adihdmi->edid_buf, len); + else + memcpy(buf, adihdmi->edid_buf + 128, len); + + return 0; +} + +static int adihdmi_mode_valid(struct drm_display_mode *mode) +{ + if (mode->clock > 165000) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +/* ----------------------------------------------------------------------------- + * DT and private structure operations + */ + +#define conn_to_adihdmi2(x) \ + container_of(x, struct adihdmi2, connector); + +#define enc_to_adihdmi2(x) \ + container_of(x, struct adihdmi2, encoder); + +#define enc_to_adihdmi(x) \ + (&(container_of(x, struct adihdmi2, encoder)->base)) + +static int adihdmi_parse_dt(struct device_node *np, + struct adihdmi_link_config *config) +{ + memset(config, 0, sizeof(*config)); + + config->input_color_depth = 8; + + config->input_colorspace = HDMI_COLORSPACE_RGB; + //config->input_colorspace = HDMI_COLORSPACE_YUV422; + //config->input_colorspace = HDMI_COLORSPACE_YUV444; + + config->input_clock = ADIHDMI_INPUT_CLOCK_1X; + //config->input_clock = ADIHDMI_INPUT_CLOCK_2X; + //config->input_clock = ADIHDMI_INPUT_CLOCK_DDR; + + if (config->input_colorspace == HDMI_COLORSPACE_YUV422 || + config->input_clock != ADIHDMI_INPUT_CLOCK_1X) { + + config->input_style = 1; + //config->input_justification = ADIHDMI_INPUT_JUSTIFICATION_LEFT; + config->input_justification = ADIHDMI_INPUT_JUSTIFICATION_EVENLY; + //config->input_justification = ADIHDMI_INPUT_JUSTIFICATION_RIGHT; + + } else { + config->input_style = 1; + config->input_justification = ADIHDMI_INPUT_JUSTIFICATION_LEFT; + } + + config->clock_delay = 0; + config->embedded_sync = 0; + + /* Hardcode the sync pulse configurations for now. */ + config->sync_pulse = ADIHDMI_INPUT_SYNC_PULSE_NONE; + config->vsync_polarity = ADIHDMI_SYNC_POLARITY_PASSTHROUGH; + config->hsync_polarity = ADIHDMI_SYNC_POLARITY_PASSTHROUGH; + + return 0; +} + +static const int edid_i2c_addr = 0x7e; +static const int packet_i2c_addr = 0x70; +static const int cec_i2c_addr = 0x78; + +static int adihdmi_create(struct i2c_client *i2c, struct adihdmi *adihdmi) +{ + struct adihdmi_link_config link_config; + struct device *dev = &i2c->dev; + unsigned int val; + int ret; + + adihdmi->powered = false; + adihdmi->status = connector_status_disconnected; + + ret = adihdmi_parse_dt(NULL, &link_config); + if (ret) + { + pr_err("%s - %d - Bad parse\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + /* + * The power down GPIO is optional. If present, toggle it from active to + * inactive to wake up the encoder. + */ + adihdmi->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH); + if (IS_ERR(adihdmi->gpio_pd)) + { + pr_err("%s - %d - Bad PD GPIO\n", __FUNCTION__, __LINE__); + return PTR_ERR(adihdmi->gpio_pd); + } + + if (adihdmi->gpio_pd) { + mdelay(5); + gpiod_set_value_cansleep(adihdmi->gpio_pd, 0); + } + + adihdmi->regmap = devm_regmap_init_i2c(i2c, &adihdmi_regmap_config); + if (IS_ERR(adihdmi->regmap)) + { + pr_err("%s - %d - Bad reg map init\n", __FUNCTION__, __LINE__); + return PTR_ERR(adihdmi->regmap); + } + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_CHIP_REVISION, &val); + if (ret) + { + pr_err("%s - %d - Bad reg map read\n", __FUNCTION__, __LINE__); + return ret; + } + dev_dbg(dev, "Rev. %d\n", val); + + ret = regmap_register_patch(adihdmi->regmap, adihdmi_fixed_registers, + ARRAY_SIZE(adihdmi_fixed_registers)); + if (ret) + { + pr_err("%s - %d - Bad reg map patch\n", __FUNCTION__, __LINE__); + return ret; + } + + regmap_write(adihdmi->regmap, ADIHDMI_REG_EDID_I2C_ADDR, edid_i2c_addr); + regmap_write(adihdmi->regmap, ADIHDMI_REG_PACKET_I2C_ADDR, + packet_i2c_addr); + regmap_write(adihdmi->regmap, ADIHDMI_REG_CEC_I2C_ADDR, cec_i2c_addr); + adihdmi_packet_disable(adihdmi, 0xffff); + + adihdmi->i2c_main = i2c; + adihdmi->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1); + if (!adihdmi->i2c_edid) + { + pr_err("%s - %d - No mem for EDID\n", __FUNCTION__, __LINE__); + return -ENOMEM; + } + + if (i2c->irq) { + init_waitqueue_head(&adihdmi->wq); + + ret = devm_request_threaded_irq(dev, i2c->irq, NULL, + adihdmi_irq_handler, + IRQF_ONESHOT, dev_name(dev), + adihdmi); + if (ret) + { + pr_err("%s - %d - Bad IRQ thread request\n", __FUNCTION__, __LINE__); + goto err_i2c_unregister_device; + } + } + + /* CEC is unused for now */ + regmap_write(adihdmi->regmap, ADIHDMI_REG_CEC_CTRL, + ADIHDMI_CEC_CTRL_POWER_DOWN); + + adihdmi_power_off(adihdmi); + + adihdmi_set_link_config(adihdmi, &link_config); + + adihdmi_audio_setup(adihdmi); + + return 0; + +err_i2c_unregister_device: + i2c_unregister_device(adihdmi->i2c_edid); + + return ret; +} + +static void adihdmi_destroy(struct adihdmi *priv) +{ + i2c_unregister_device(priv->i2c_edid); +} + +/* ----------------------------------------------------------------------------- + * Encoder operations + */ + +static int adihdmi_encoder_get_modes(struct adihdmi *adihdmi, + struct drm_connector *connector) +{ + struct edid *edid; + unsigned int count; + + /* Reading the EDID only works if the device is powered */ + if (!adihdmi->powered) { + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(0), + ADIHDMI_INT0_EDID_READY); + regmap_write(adihdmi->regmap, ADIHDMI_REG_INT(1), + ADIHDMI_INT1_DDC_ERROR); + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER, + ADIHDMI_POWER_POWER_DOWN, 0); + adihdmi->current_edid_segment = -1; + } + + edid = drm_do_get_edid(connector, adihdmi_get_edid_block, adihdmi); + + if (!adihdmi->powered) + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER, + ADIHDMI_POWER_POWER_DOWN, + ADIHDMI_POWER_POWER_DOWN); + + kfree(adihdmi->edid); + adihdmi->edid = edid; + if (!edid) + { + pr_err("%s - %d - No EDID\n", __FUNCTION__, __LINE__); + return 0; + } + + drm_mode_connector_update_edid_property(connector, edid); + count = drm_add_edid_modes(connector, edid); + + adihdmi_set_config_csc(adihdmi, connector, adihdmi->rgb); + + return count; +} + +static void adihdmi_encoder_dpms(struct drm_encoder *encoder, int mode) +{ + struct adihdmi2 *priv2 = enc_to_adihdmi2(encoder); + + if (mode == DRM_MODE_DPMS_ON) + adihdmi_power_on(&priv2->base); + else + adihdmi_power_off(&priv2->base); +} + + static enum drm_connector_status +adihdmi_encoder_detect(struct adihdmi *adihdmi, + struct drm_connector *connector) +{ + enum drm_connector_status status; + unsigned int val; + bool hpd; + int ret; + + ret = regmap_read(adihdmi->regmap, ADIHDMI_REG_STATUS, &val); + if (ret < 0) + { + pr_err("%s - %d - Disconnected\n", __FUNCTION__, __LINE__); + return connector_status_disconnected; + } + + if (val & ADIHDMI_STATUS_HPD) + status = connector_status_connected; + else + status = connector_status_disconnected; + + hpd = adihdmi_hpd(adihdmi); + + /* The chip resets itself when the cable is disconnected, so in case + * there is a pending HPD interrupt and the cable is connected there was + * at least one transition from disconnected to connected and the chip + * has to be reinitialized. */ + if (status == connector_status_connected && hpd && adihdmi->powered) { + regcache_mark_dirty(adihdmi->regmap); + adihdmi_power_on(adihdmi); + adihdmi_encoder_get_modes(adihdmi, connector); + if (adihdmi->status == connector_status_connected) + status = connector_status_disconnected; + } else { + /* Renable HDP sensing */ + regmap_update_bits(adihdmi->regmap, ADIHDMI_REG_POWER2, + ADIHDMI_REG_POWER2_HDP_SRC_MASK, + ADIHDMI_REG_POWER2_HDP_SRC_BOTH); + } + + adihdmi->status = status; + return status; +} + +static bool adihdmi_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static int adihdmi_encoder_mode_valid(struct drm_encoder *encoder, struct drm_display_mode *mode) +{ + return adihdmi_mode_valid(mode); +} + +static void adihdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + unsigned int low_refresh_rate; + unsigned int hsync_polarity = 0; + unsigned int vsync_polarity = 0; + struct adihdmi *adihdmi = enc_to_adihdmi(encoder); + + if (adihdmi->embedded_sync) { + unsigned int hsync_offset, hsync_len; + unsigned int vsync_offset, vsync_len; + + hsync_offset = adj_mode->crtc_hsync_start - + adj_mode->crtc_hdisplay; + vsync_offset = adj_mode->crtc_vsync_start - + adj_mode->crtc_vdisplay; + hsync_len = adj_mode->crtc_hsync_end - + adj_mode->crtc_hsync_start; + vsync_len = adj_mode->crtc_vsync_end - + adj_mode->crtc_vsync_start; + + /* The hardware vsync generator has a off-by-one bug */ + vsync_offset += 1; + + regmap_write(adihdmi->regmap, ADIHDMI_REG_HSYNC_PLACEMENT_MSB, + ((hsync_offset >> 10) & 0x7) << 5); + regmap_write(adihdmi->regmap, ADIHDMI_REG_SYNC_DECODER(0), + (hsync_offset >> 2) & 0xff); + regmap_write(adihdmi->regmap, ADIHDMI_REG_SYNC_DECODER(1), + ((hsync_offset & 0x3) << 6) | + ((hsync_len >> 4) & 0x3f)); + regmap_write(adihdmi->regmap, ADIHDMI_REG_SYNC_DECODER(2), + ((hsync_len & 0xf) << 4) | + ((vsync_offset >> 6) & 0xf)); + regmap_write(adihdmi->regmap, ADIHDMI_REG_SYNC_DECODER(3), + ((vsync_offset & 0x3f) << 2) | + ((vsync_len >> 8) & 0x3)); + regmap_write(adihdmi->regmap, ADIHDMI_REG_SYNC_DECODER(4), + vsync_len & 0xff); + + hsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PHSYNC); + vsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PVSYNC); + } else { + enum adihdmi_sync_polarity mode_hsync_polarity; + enum adihdmi_sync_polarity mode_vsync_polarity; + + /** + * If the input signal is always low or always high we want to + * invert or let it passthrough depending on the polarity of the + * current mode. + **/ + if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC) + mode_hsync_polarity = ADIHDMI_SYNC_POLARITY_LOW; + else + mode_hsync_polarity = ADIHDMI_SYNC_POLARITY_HIGH; + + if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC) + mode_vsync_polarity = ADIHDMI_SYNC_POLARITY_LOW; + else + mode_vsync_polarity = ADIHDMI_SYNC_POLARITY_HIGH; + + if (adihdmi->hsync_polarity != mode_hsync_polarity && + adihdmi->hsync_polarity != + ADIHDMI_SYNC_POLARITY_PASSTHROUGH) + hsync_polarity = 1; + + if (adihdmi->vsync_polarity != mode_vsync_polarity && + adihdmi->vsync_polarity != + ADIHDMI_SYNC_POLARITY_PASSTHROUGH) + vsync_polarity = 1; + } + + if (mode->vrefresh <= 24000) + low_refresh_rate = ADIHDMI_LOW_REFRESH_RATE_24HZ; + else if (mode->vrefresh <= 25000) + low_refresh_rate = ADIHDMI_LOW_REFRESH_RATE_25HZ; + else if (mode->vrefresh <= 30000) + low_refresh_rate = ADIHDMI_LOW_REFRESH_RATE_30HZ; + else + low_refresh_rate = ADIHDMI_LOW_REFRESH_RATE_NONE; + + regmap_update_bits(adihdmi->regmap, 0xfb, + 0x6, low_refresh_rate << 1); + regmap_update_bits(adihdmi->regmap, 0x17, + 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); + + /* + * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is + * supposed to give better results. + */ + + adihdmi->f_tmds = mode->clock; +} + +static void adihdmi_encoder_restore(struct drm_encoder *encoder) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); +} + +static void adihdmi_encoder_save(struct drm_encoder *encoder) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); +} + +static void adihdmi_encoder_prepare(struct drm_encoder *encoder) +{ + adihdmi_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); +} + +static void adihdmi_encoder_commit(struct drm_encoder *encoder) +{ + adihdmi_encoder_dpms(encoder, DRM_MODE_DPMS_ON); +} + +static struct drm_encoder_helper_funcs adihdmi_encoder_helper_funcs = { + .dpms = adihdmi_encoder_dpms, + .save = adihdmi_encoder_save, + .restore = adihdmi_encoder_restore, + .mode_fixup = adihdmi_encoder_mode_fixup, + .prepare = adihdmi_encoder_prepare, + .commit = adihdmi_encoder_commit, + .mode_set = adihdmi_encoder_mode_set, +}; + +static void adihdmi_encoder_destroy(struct drm_encoder *encoder) +{ + struct adihdmi2 *priv = enc_to_adihdmi2(encoder); + + adihdmi_destroy(&priv->base); + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs adihdmi_encoder_funcs = { + .destroy = adihdmi_encoder_destroy, +}; + +/* ----------------------------------------------------------------------------- + * Slave operations + */ + +static int adihdmi_encoder_slave_create_resources(struct drm_encoder *encoder, struct drm_connector *connector) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); + return 0; +} + +static void adihdmi_encoder_slave_destroy(struct drm_encoder *encoder) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); +} + + static enum drm_connector_status +adihdmi_encoder_slave_detect(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + return adihdmi_encoder_detect(enc_to_adihdmi(encoder), + connector); +} + +static int adihdmi_encoder_slave_get_modes(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + return adihdmi_encoder_get_modes(enc_to_adihdmi(encoder), + connector); +} + + +static void adihdmi_encoder_slave_set_config(struct drm_encoder *encoder, void *params) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); +} + +static int adihdmi_encoder_set_property(struct drm_encoder *encoder, struct drm_connector *connector, struct drm_property *property, uint64_t val) +{ + pr_debug("%s - %d\n", __FUNCTION__, __LINE__); + return 0; +} + +static struct drm_encoder_slave_funcs adihdmi_encoder_slave_funcs = { + .create_resources = adihdmi_encoder_slave_create_resources, + .destroy = adihdmi_encoder_slave_destroy, + .detect = adihdmi_encoder_slave_detect, + .dpms = adihdmi_encoder_dpms, + .get_modes = adihdmi_encoder_slave_get_modes, + .mode_fixup = adihdmi_encoder_mode_fixup, + .mode_set = adihdmi_encoder_mode_set, + .mode_valid = adihdmi_encoder_mode_valid, + .restore = adihdmi_encoder_restore, + .save = adihdmi_encoder_save, + .set_config = adihdmi_encoder_slave_set_config, + .set_property = adihdmi_encoder_set_property, +}; + +/* ----------------------------------------------------------------------------- + * Connector operations + */ + +static int adihdmi_connector_get_modes(struct drm_connector *connector) +{ + struct adihdmi2 *priv = conn_to_adihdmi2(connector); + + return adihdmi_encoder_get_modes(&priv->base, connector); +} + +static int adihdmi_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + return adihdmi_mode_valid(mode); +} + + static struct drm_encoder * +adihdmi_connector_best_encoder(struct drm_connector *connector) +{ + struct adihdmi2 *priv = conn_to_adihdmi2(connector); + + return &priv->encoder; +} + +static struct drm_connector_helper_funcs adihdmi_connector_helper_funcs = { + .get_modes = adihdmi_connector_get_modes, + .mode_valid = adihdmi_connector_mode_valid, + .best_encoder = adihdmi_connector_best_encoder, +}; + + static enum drm_connector_status +adihdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct adihdmi2 *priv = conn_to_adihdmi2(connector); + + return adihdmi_encoder_detect(&priv->base, connector); +} + +static void adihdmi_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static struct drm_connector_funcs adihdmi_connector_funcs = { + .dpms = drm_helper_connector_dpms, + .fill_modes = drm_helper_probe_single_connector_modes, + .detect = adihdmi_connector_detect, + .destroy = adihdmi_connector_destroy, +}; + +/* ----------------------------------------------------------------------------- + * Component operations + */ + +static int adihdmi_bind(struct device *dev, struct device *master, void *data) +{ + struct i2c_client *client = to_i2c_client(dev); + struct drm_device *drm = data; + struct adihdmi2 *priv; + uint32_t crtcs = 0; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + { + pr_err("%s - %d - No memory for ADIHDMI\n", __FUNCTION__, __LINE__); + return -ENOMEM; + } + + dev_set_drvdata(dev, priv); + + if (dev->of_node) + crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + + /* If no CRTCs were found, fall back to our old behaviour */ + if (crtcs == 0) { + dev_warn(dev, "Falling back to first CRTC\n"); + crtcs = 1 << 0; + } + + priv->base.encoder = &priv->encoder; + priv->connector.interlace_allowed = 1; + priv->encoder.possible_crtcs = crtcs; + + ret = adihdmi_create(client, &priv->base); + if (ret) + return ret; + + drm_encoder_helper_add(&priv->encoder, &adihdmi_encoder_helper_funcs); + ret = drm_encoder_init(drm, &priv->encoder, &adihdmi_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + if (ret) + goto err_encoder; + + drm_connector_helper_add(&priv->connector, + &adihdmi_connector_helper_funcs); + ret = drm_connector_init(drm, &priv->connector, + &adihdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) + goto err_connector; + + ret = drm_connector_register(&priv->connector); + if (ret) + goto err_sysfs; + + priv->connector.encoder = &priv->encoder; + drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); + + return 0; + +err_sysfs: + drm_connector_cleanup(&priv->connector); +err_connector: + drm_encoder_cleanup(&priv->encoder); +err_encoder: + adihdmi_destroy(&priv->base); + return ret; + + +} + +static void adihdmi_unbind(struct device *dev, struct device *master, void *data) +{ + struct adihdmi2 *priv = dev_get_drvdata(dev); + + drm_connector_cleanup(&priv->connector); + drm_encoder_cleanup(&priv->encoder); + adihdmi_destroy(&priv->base); +} + +static const struct component_ops adihdmi_ops = +{ + .bind = adihdmi_bind, + .unbind = adihdmi_unbind, +}; + +/* ----------------------------------------------------------------------------- + * Init operations + */ + +static int adihdmi_probe(struct i2c_client *i2c, const struct i2c_device_id *id) +{ + return component_add(&i2c->dev, &adihdmi_ops); +} + +static int adihdmi_remove(struct i2c_client *i2c) +{ + component_del(&i2c->dev, &adihdmi_ops); + + return 0; +} + +static int adihdmi_encoder_init(struct i2c_client *i2c, struct drm_device *dev, + struct drm_encoder_slave *encoder_slave) +{ + + struct adihdmi *adihdmi; + int ret; + + adihdmi = kzalloc(sizeof(*adihdmi), GFP_KERNEL); + if (!adihdmi) + return -ENOMEM; + + adihdmi->encoder = &encoder_slave->base; + + ret = adihdmi_create(i2c, adihdmi); + if (ret) { + kfree(adihdmi); + return ret; + } + + encoder_slave->slave_priv = adihdmi; + encoder_slave->slave_funcs = &adihdmi_encoder_slave_funcs; + + return 0; +} + +static const struct i2c_device_id adihdmi_i2c_ids[] = { + { "adv7511", 0 }, + { "adv7511w", 0 }, + { "adv7513", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, adihdmi_i2c_ids); + +static const struct of_device_id adihdmi_of_ids[] = { + { .compatible = "adi,adv7511", }, + { .compatible = "adi,adv7511w", }, + { .compatible = "adi,adv7513", }, + { } +}; +MODULE_DEVICE_TABLE(of, adihdmi_of_ids); + +static struct drm_i2c_encoder_driver adihdmi_driver = { + .i2c_driver = { + .driver = { + .name = "adihdmi", + .of_match_table = adihdmi_of_ids, + }, + .id_table = adihdmi_i2c_ids, + .probe = adihdmi_probe, + .remove = adihdmi_remove, + }, + + .encoder_init = adihdmi_encoder_init, +}; + +static int __init adihdmi_init(void) +{ + return drm_i2c_encoder_register(THIS_MODULE, &adihdmi_driver); +} +module_init(adihdmi_init); + +static void __exit adihdmi_exit(void) +{ + drm_i2c_encoder_unregister(&adihdmi_driver); +} +module_exit(adihdmi_exit); + +MODULE_AUTHOR("Lars-Peter Clausen "); +MODULE_DESCRIPTION("ADIHDMI HDMI transmitter driver"); +MODULE_LICENSE("GPL"); diff -Naur --no-dereference a/drivers/gpu/drm/i2c/adihdmi.h b/drivers/gpu/drm/i2c/adihdmi.h --- a/drivers/gpu/drm/i2c/adihdmi.h 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpu/drm/i2c/adihdmi.h 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,289 @@ +/* + * Analog Devices ADIHDMI HDMI transmitter driver + * + * Copyright 2012 Analog Devices Inc. + * + * Licensed under the GPL-2. + */ + +#ifndef __DRM_I2C_ADIHDMI_H__ +#define __DRM_I2C_ADIHDMI_H__ + +#include + +#define ADIHDMI_REG_CHIP_REVISION 0x00 +#define ADIHDMI_REG_N0 0x01 +#define ADIHDMI_REG_N1 0x02 +#define ADIHDMI_REG_N2 0x03 +#define ADIHDMI_REG_SPDIF_FREQ 0x04 +#define ADIHDMI_REG_CTS_AUTOMATIC1 0x05 +#define ADIHDMI_REG_CTS_AUTOMATIC2 0x06 +#define ADIHDMI_REG_CTS_MANUAL0 0x07 +#define ADIHDMI_REG_CTS_MANUAL1 0x08 +#define ADIHDMI_REG_CTS_MANUAL2 0x09 +#define ADIHDMI_REG_AUDIO_SOURCE 0x0a +#define ADIHDMI_REG_AUDIO_CONFIG 0x0b +#define ADIHDMI_REG_I2S_CONFIG 0x0c +#define ADIHDMI_REG_I2S_WIDTH 0x0d +#define ADIHDMI_REG_AUDIO_SUB_SRC0 0x0e +#define ADIHDMI_REG_AUDIO_SUB_SRC1 0x0f +#define ADIHDMI_REG_AUDIO_SUB_SRC2 0x10 +#define ADIHDMI_REG_AUDIO_SUB_SRC3 0x11 +#define ADIHDMI_REG_AUDIO_CFG1 0x12 +#define ADIHDMI_REG_AUDIO_CFG2 0x13 +#define ADIHDMI_REG_AUDIO_CFG3 0x14 +#define ADIHDMI_REG_I2C_FREQ_ID_CFG 0x15 +#define ADIHDMI_REG_VIDEO_INPUT_CFG1 0x16 +#define ADIHDMI_REG_CSC_UPPER(x) (0x18 + (x) * 2) +#define ADIHDMI_REG_CSC_LOWER(x) (0x19 + (x) * 2) +#define ADIHDMI_REG_SYNC_DECODER(x) (0x30 + (x)) +#define ADIHDMI_REG_DE_GENERATOR (0x35 + (x)) +#define ADIHDMI_REG_PIXEL_REPETITION 0x3b +#define ADIHDMI_REG_VIC_MANUAL 0x3c +#define ADIHDMI_REG_VIC_SEND 0x3d +#define ADIHDMI_REG_VIC_DETECTED 0x3e +#define ADIHDMI_REG_AUX_VIC_DETECTED 0x3f +#define ADIHDMI_REG_PACKET_ENABLE0 0x40 +#define ADIHDMI_REG_POWER 0x41 +#define ADIHDMI_REG_STATUS 0x42 +#define ADIHDMI_REG_EDID_I2C_ADDR 0x43 +#define ADIHDMI_REG_PACKET_ENABLE1 0x44 +#define ADIHDMI_REG_PACKET_I2C_ADDR 0x45 +#define ADIHDMI_REG_DSD_ENABLE 0x46 +#define ADIHDMI_REG_VIDEO_INPUT_CFG2 0x48 +#define ADIHDMI_REG_INFOFRAME_UPDATE 0x4a +#define ADIHDMI_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */ +#define ADIHDMI_REG_AVI_INFOFRAME_VERSION 0x52 +#define ADIHDMI_REG_AVI_INFOFRAME_LENGTH 0x53 +#define ADIHDMI_REG_AVI_INFOFRAME_CHECKSUM 0x54 +#define ADIHDMI_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */ +#define ADIHDMI_REG_AUDIO_INFOFRAME_VERSION 0x70 +#define ADIHDMI_REG_AUDIO_INFOFRAME_LENGTH 0x71 +#define ADIHDMI_REG_AUDIO_INFOFRAME_CHECKSUM 0x72 +#define ADIHDMI_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */ +#define ADIHDMI_REG_INT_ENABLE(x) (0x94 + (x)) +#define ADIHDMI_REG_INT(x) (0x96 + (x)) +#define ADIHDMI_REG_INPUT_CLK_DIV 0x9d +#define ADIHDMI_REG_PLL_STATUS 0x9e +#define ADIHDMI_REG_HDMI_POWER 0xa1 +#define ADIHDMI_REG_HDCP_HDMI_CFG 0xaf +#define ADIHDMI_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */ +#define ADIHDMI_REG_HDCP_STATUS 0xb8 +#define ADIHDMI_REG_BCAPS 0xbe +#define ADIHDMI_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */ +#define ADIHDMI_REG_EDID_SEGMENT 0xc4 +#define ADIHDMI_REG_DDC_STATUS 0xc8 +#define ADIHDMI_REG_EDID_READ_CTRL 0xc9 +#define ADIHDMI_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */ +#define ADIHDMI_REG_TIMING_GEN_SEQ 0xd0 +#define ADIHDMI_REG_POWER2 0xd6 +#define ADIHDMI_REG_HSYNC_PLACEMENT_MSB 0xfa + +#define ADIHDMI_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */ +#define ADIHDMI_REG_TMDS_CLOCK_INV 0xde +#define ADIHDMI_REG_ARC_CTRL 0xdf +#define ADIHDMI_REG_CEC_I2C_ADDR 0xe1 +#define ADIHDMI_REG_CEC_CTRL 0xe2 +#define ADIHDMI_REG_CHIP_ID_HIGH 0xf5 +#define ADIHDMI_REG_CHIP_ID_LOW 0xf6 + +#define ADIHDMI_CSC_ENABLE BIT(7) +#define ADIHDMI_CSC_UPDATE_MODE BIT(5) + +#define ADIHDMI_INT0_HDP BIT(7) +#define ADIHDMI_INT0_VSYNC BIT(5) +#define ADIHDMI_INT0_AUDIO_FIFO_FULL BIT(4) +#define ADIHDMI_INT0_EDID_READY BIT(2) +#define ADIHDMI_INT0_HDCP_AUTHENTICATED BIT(1) + +#define ADIHDMI_INT1_DDC_ERROR BIT(7) +#define ADIHDMI_INT1_BKSV BIT(6) +#define ADIHDMI_INT1_CEC_TX_READY BIT(5) +#define ADIHDMI_INT1_CEC_TX_ARBIT_LOST BIT(4) +#define ADIHDMI_INT1_CEC_TX_RETRY_TIMEOUT BIT(3) +#define ADIHDMI_INT1_CEC_RX_READY3 BIT(2) +#define ADIHDMI_INT1_CEC_RX_READY2 BIT(1) +#define ADIHDMI_INT1_CEC_RX_READY1 BIT(0) + +#define ADIHDMI_ARC_CTRL_POWER_DOWN BIT(0) + +#define ADIHDMI_CEC_CTRL_POWER_DOWN BIT(0) + +#define ADIHDMI_POWER_POWER_DOWN BIT(6) + +#define ADIHDMI_HDMI_CFG_MODE_MASK 0x2 +#define ADIHDMI_HDMI_CFG_MODE_DVI 0x0 +#define ADIHDMI_HDMI_CFG_MODE_HDMI 0x2 + +#define ADIHDMI_AUDIO_SELECT_I2C 0x0 +#define ADIHDMI_AUDIO_SELECT_SPDIF 0x1 +#define ADIHDMI_AUDIO_SELECT_DSD 0x2 +#define ADIHDMI_AUDIO_SELECT_HBR 0x3 +#define ADIHDMI_AUDIO_SELECT_DST 0x4 + +#define ADIHDMI_I2S_SAMPLE_LEN_16 0x2 +#define ADIHDMI_I2S_SAMPLE_LEN_20 0x3 +#define ADIHDMI_I2S_SAMPLE_LEN_18 0x4 +#define ADIHDMI_I2S_SAMPLE_LEN_22 0x5 +#define ADIHDMI_I2S_SAMPLE_LEN_19 0x8 +#define ADIHDMI_I2S_SAMPLE_LEN_23 0x9 +#define ADIHDMI_I2S_SAMPLE_LEN_24 0xb +#define ADIHDMI_I2S_SAMPLE_LEN_17 0xc +#define ADIHDMI_I2S_SAMPLE_LEN_21 0xd + +#define ADIHDMI_SAMPLE_FREQ_44100 0x0 +#define ADIHDMI_SAMPLE_FREQ_48000 0x2 +#define ADIHDMI_SAMPLE_FREQ_32000 0x3 +#define ADIHDMI_SAMPLE_FREQ_88200 0x8 +#define ADIHDMI_SAMPLE_FREQ_96000 0xa +#define ADIHDMI_SAMPLE_FREQ_176400 0xc +#define ADIHDMI_SAMPLE_FREQ_192000 0xe + +#define ADIHDMI_STATUS_POWER_DOWN_POLARITY BIT(7) +#define ADIHDMI_STATUS_HPD BIT(6) +#define ADIHDMI_STATUS_MONITOR_SENSE BIT(5) +#define ADIHDMI_STATUS_I2S_32BIT_MODE BIT(3) + +#define ADIHDMI_PACKET_ENABLE_N_CTS BIT(8+6) +#define ADIHDMI_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5) +#define ADIHDMI_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4) +#define ADIHDMI_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3) +#define ADIHDMI_PACKET_ENABLE_GC BIT(7) +#define ADIHDMI_PACKET_ENABLE_SPD BIT(6) +#define ADIHDMI_PACKET_ENABLE_MPEG BIT(5) +#define ADIHDMI_PACKET_ENABLE_ACP BIT(4) +#define ADIHDMI_PACKET_ENABLE_ISRC BIT(3) +#define ADIHDMI_PACKET_ENABLE_GM BIT(2) +#define ADIHDMI_PACKET_ENABLE_SPARE2 BIT(1) +#define ADIHDMI_PACKET_ENABLE_SPARE1 BIT(0) + +#define ADIHDMI_REG_POWER2_HDP_SRC_MASK 0xc0 +#define ADIHDMI_REG_POWER2_HDP_SRC_BOTH 0x00 +#define ADIHDMI_REG_POWER2_HDP_SRC_HDP 0x40 +#define ADIHDMI_REG_POWER2_HDP_SRC_CEC 0x80 +#define ADIHDMI_REG_POWER2_HDP_SRC_NONE 0xc0 +#define ADIHDMI_REG_POWER2_TDMS_ENABLE BIT(4) +#define ADIHDMI_REG_POWER2_GATE_INPUT_CLK BIT(0) + +#define ADIHDMI_LOW_REFRESH_RATE_NONE 0x0 +#define ADIHDMI_LOW_REFRESH_RATE_24HZ 0x1 +#define ADIHDMI_LOW_REFRESH_RATE_25HZ 0x2 +#define ADIHDMI_LOW_REFRESH_RATE_30HZ 0x3 + +#define ADIHDMI_AUDIO_CFG3_LEN_MASK 0x0f +#define ADIHDMI_I2C_FREQ_ID_CFG_RATE_MASK 0xf0 + +#define ADIHDMI_AUDIO_SOURCE_I2S 0 +#define ADIHDMI_AUDIO_SOURCE_SPDIF 1 + +#define ADIHDMI_I2S_FORMAT_I2S 0 +#define ADIHDMI_I2S_FORMAT_RIGHT_J 1 +#define ADIHDMI_I2S_FORMAT_LEFT_J 2 + +#define ADIHDMI_PACKET(p, x) ((p) * 0x20 + (x)) +#define ADIHDMI_PACKET_SDP(x) ADIHDMI_PACKET(0, x) +#define ADIHDMI_PACKET_MPEG(x) ADIHDMI_PACKET(1, x) +#define ADIHDMI_PACKET_ACP(x) ADIHDMI_PACKET(2, x) +#define ADIHDMI_PACKET_ISRC1(x) ADIHDMI_PACKET(3, x) +#define ADIHDMI_PACKET_ISRC2(x) ADIHDMI_PACKET(4, x) +#define ADIHDMI_PACKET_GM(x) ADIHDMI_PACKET(5, x) +#define ADIHDMI_PACKET_SPARE(x) ADIHDMI_PACKET(6, x) + +enum adihdmi_input_clock { + ADIHDMI_INPUT_CLOCK_1X, + ADIHDMI_INPUT_CLOCK_2X, + ADIHDMI_INPUT_CLOCK_DDR, +}; + +enum adihdmi_input_justification { + ADIHDMI_INPUT_JUSTIFICATION_EVENLY = 0, + ADIHDMI_INPUT_JUSTIFICATION_RIGHT = 1, + ADIHDMI_INPUT_JUSTIFICATION_LEFT = 2, +}; + +enum adihdmi_input_sync_pulse { + ADIHDMI_INPUT_SYNC_PULSE_DE = 0, + ADIHDMI_INPUT_SYNC_PULSE_HSYNC = 1, + ADIHDMI_INPUT_SYNC_PULSE_VSYNC = 2, + ADIHDMI_INPUT_SYNC_PULSE_NONE = 3, +}; + +/** + * enum adihdmi_sync_polarity - Polarity for the input sync signals + * @ADIHDMI_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of + * the currently configured mode. + * @ADIHDMI_SYNC_POLARITY_LOW: Sync polarity is low + * @ADIHDMI_SYNC_POLARITY_HIGH: Sync polarity is high + * + * If the polarity is set to either LOW or HIGH the driver will configure the + * ADIHDMI to internally invert the sync signal if required to match the sync + * polarity setting for the currently selected output mode. + * + * If the polarity is set to PASSTHROUGH, the ADIHDMI will route the signal + * unchanged. This is used when the upstream graphics core already generates + * the sync signals with the correct polarity. + */ +enum adihdmi_sync_polarity { + ADIHDMI_SYNC_POLARITY_PASSTHROUGH, + ADIHDMI_SYNC_POLARITY_LOW, + ADIHDMI_SYNC_POLARITY_HIGH, +}; + +/** + * struct adihdmi_link_config - Describes adihdmi hardware configuration + * @input_color_depth: Number of bits per color component (8, 10 or 12) + * @input_colorspace: The input colorspace (RGB, YUV444, YUV422) + * @input_clock: The input video clock style (1x, 2x, DDR) + * @input_style: The input component arrangement variant + * @input_justification: Video input format bit justification + * @clock_delay: Clock delay for the input clock (in ps) + * @embedded_sync: Video input uses BT.656-style embedded sync + * @sync_pulse: Select the sync pulse + * @vsync_polarity: vsync input signal configuration + * @hsync_polarity: hsync input signal configuration + */ +struct adihdmi_link_config { + unsigned int input_color_depth; + enum hdmi_colorspace input_colorspace; + enum adihdmi_input_clock input_clock; + unsigned int input_style; + enum adihdmi_input_justification input_justification; + + int clock_delay; + + bool embedded_sync; + enum adihdmi_input_sync_pulse sync_pulse; + enum adihdmi_sync_polarity vsync_polarity; + enum adihdmi_sync_polarity hsync_polarity; +}; + +/** + * enum adihdmi_csc_scaling - Scaling factor for the ADIHDMI CSC + * @ADIHDMI_CSC_SCALING_1: CSC results are not scaled + * @ADIHDMI_CSC_SCALING_2: CSC results are scaled by a factor of two + * @ADIHDMI_CSC_SCALING_4: CSC results are scalled by a factor of four + */ +enum adihdmi_csc_scaling { + ADIHDMI_CSC_SCALING_1 = 0, + ADIHDMI_CSC_SCALING_2 = 1, + ADIHDMI_CSC_SCALING_4 = 2, +}; + +/** + * struct adihdmi_video_config - Describes adihdmi hardware configuration + * @csc_enable: Whether to enable color space conversion + * @csc_scaling_factor: Color space conversion scaling factor + * @csc_coefficents: Color space conversion coefficents + * @hdmi_mode: Whether to use HDMI or DVI output mode + * @avi_infoframe: HDMI infoframe + */ +struct adihdmi_video_config { + bool csc_enable; + enum adihdmi_csc_scaling csc_scaling_factor; + const uint16_t *csc_coefficents; + + bool hdmi_mode; + struct hdmi_avi_infoframe avi_infoframe; +}; + +#endif /* __DRM_I2C_ADIHDMI_H__ */ diff -Naur --no-dereference a/drivers/gpu/drm/i2c/Kconfig b/drivers/gpu/drm/i2c/Kconfig --- a/drivers/gpu/drm/i2c/Kconfig 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i2c/Kconfig 2016-05-11 13:31:53.197225234 -0400 @@ -7,6 +7,12 @@ help Support for the Analog Device ADV7511(W) and ADV7513 HDMI encoders. +config DRM_I2C_ADIHDMI + tristate "ADI HDMI encoder" + default m if DRM_TILCDC + help + Support for ADI HDMI encoder. + config DRM_I2C_CH7006 tristate "Chrontel ch7006 TV encoder" default m if DRM_NOUVEAU @@ -28,6 +34,7 @@ config DRM_I2C_NXP_TDA998X tristate "NXP Semiconductors TDA998X HDMI encoder" default m if DRM_TILCDC + select SND_SOC_HDMI_CODEC if SND_SOC help Support for NXP Semiconductors TDA998X HDMI encoders. diff -Naur --no-dereference a/drivers/gpu/drm/i2c/Makefile b/drivers/gpu/drm/i2c/Makefile --- a/drivers/gpu/drm/i2c/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i2c/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -10,3 +10,6 @@ tda998x-y := tda998x_drv.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o + +adihdmi-y := adihdmi_drv.o +obj-$(CONFIG_DRM_I2C_ADIHDMI) += adihdmi.o diff -Naur --no-dereference a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c --- a/drivers/gpu/drm/i2c/tda998x_drv.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i2c/tda998x_drv.c 2016-05-11 13:31:53.197225234 -0400 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -29,6 +30,11 @@ #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) +struct tda998x_audio_port { + u8 format; /* AFMT_xxx */ + u8 config; /* AP value */ +}; + struct tda998x_priv { struct i2c_client *cec; struct i2c_client *hdmi; @@ -40,7 +46,9 @@ u8 vip_cntrl_0; u8 vip_cntrl_1; u8 vip_cntrl_2; - struct tda998x_encoder_params params; + struct tda998x_audio_params audio_params; + + struct platform_device *audio_pdev; wait_queue_head_t wq_edid; volatile int wq_edid_wait; @@ -52,6 +60,8 @@ struct drm_encoder encoder; struct drm_connector connector; + + struct tda998x_audio_port audio_port[2]; }; #define conn_to_tda998x_priv(x) \ @@ -665,26 +675,16 @@ reg_set(priv, REG_DIP_IF_FLAGS, bit); } -static void -tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) +static int tda998x_write_aif(struct tda998x_priv *priv, + struct hdmi_audio_infoframe *cea) { union hdmi_infoframe frame; - hdmi_audio_infoframe_init(&frame.audio); - - frame.audio.channels = p->audio_frame[1] & 0x07; - frame.audio.channel_allocation = p->audio_frame[4]; - frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3; - frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7; - - /* - * L-PCM and IEC61937 compressed audio shall always set sample - * frequency to "refer to stream". For others, see the HDMI - * specification. - */ - frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2; + frame.audio = *cea; tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); + + return 0; } static void @@ -709,20 +709,21 @@ } } -static void +static int tda998x_configure_audio(struct tda998x_priv *priv, - struct drm_display_mode *mode, struct tda998x_encoder_params *p) + struct tda998x_audio_params *params, + unsigned mode_clock) { u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; u32 n; /* Enable audio ports */ - reg_write(priv, REG_ENA_AP, p->audio_cfg); - reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); + reg_write(priv, REG_ENA_AP, params->config); /* Set audio input source */ - switch (p->audio_format) { + switch (params->format) { case AFMT_SPDIF: + reg_write(priv, REG_ENA_ACLK, 0); reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); clksel_aip = AIP_CLKSEL_AIP_SPDIF; clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; @@ -730,15 +731,29 @@ break; case AFMT_I2S: + reg_write(priv, REG_ENA_ACLK, 1); reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); clksel_aip = AIP_CLKSEL_AIP_I2S; clksel_fs = AIP_CLKSEL_FS_ACLK; - cts_n = CTS_N_M(3) | CTS_N_K(3); + switch (params->sample_width) { + case 16: + cts_n = CTS_N_M(3) | CTS_N_K(1); + break; + case 18: + case 20: + case 24: + cts_n = CTS_N_M(3) | CTS_N_K(2); + break; + default: + case 32: + cts_n = CTS_N_M(3) | CTS_N_K(3); + break; + } break; default: - BUG(); - return; + dev_err(&priv->hdmi->dev, "Unsupported I2S format\n"); + return -EINVAL; } reg_write(priv, REG_AIP_CLKSEL, clksel_aip); @@ -754,11 +769,11 @@ * assume 100MHz requires larger divider. */ adiv = AUDIO_DIV_SERCLK_8; - if (mode->clock > 100000) + if (mode_clock > 100000) adiv++; /* AUDIO_DIV_SERCLK_16 */ /* S/PDIF asks for a larger divider */ - if (p->audio_format == AFMT_SPDIF) + if (params->format == AFMT_SPDIF) adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */ reg_write(priv, REG_AUDIO_DIV, adiv); @@ -767,7 +782,7 @@ * This is the approximate value of N, which happens to be * the recommended values for non-coherent clocks. */ - n = 128 * p->audio_sample_rate / 1000; + n = 128 * params->sample_rate / 1000; /* Write the CTS and N values */ buf[0] = 0x44; @@ -786,19 +801,13 @@ reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); /* Write the channel status */ - buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT; - buf[1] = 0x00; - buf[2] = IEC958_AES3_CON_FS_NOTID; - buf[3] = IEC958_AES4_CON_ORIGFS_NOTID | - IEC958_AES4_CON_MAX_WORDLEN_24; - reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); + reg_write_range(priv, REG_CH_STAT_B(0), params->status, 4); tda998x_audio_mute(priv, true); msleep(20); tda998x_audio_mute(priv, false); - /* Write the audio information packet */ - tda998x_write_aif(priv, p); + return tda998x_write_aif(priv, ¶ms->cea); } /* DRM encoder functions */ @@ -819,7 +828,7 @@ VIP_CNTRL_2_SWAP_F(p->swap_f) | (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); - priv->params = *p; + priv->audio_params = p->audio; } static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) @@ -1073,9 +1082,11 @@ tda998x_write_avi(priv, adjusted_mode); - if (priv->params.audio_cfg) - tda998x_configure_audio(priv, adjusted_mode, - &priv->params); + if (priv->audio_params.format != AFMT_UNUSED) { + tda998x_configure_audio(priv, + &priv->audio_params, + adjusted_mode->clock); + } } } @@ -1175,6 +1186,8 @@ drm_mode_connector_update_edid_property(connector, edid); n = drm_add_edid_modes(connector, edid); priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); + drm_edid_to_eld(connector, edid); + kfree(edid); return n; @@ -1196,6 +1209,9 @@ cec_write(priv, REG_CEC_RXSHPDINTENA, 0); reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); + if (priv->audio_pdev) + platform_device_unregister(priv->audio_pdev); + if (priv->hdmi->irq) free_irq(priv->hdmi->irq, priv); @@ -1205,8 +1221,179 @@ i2c_unregister_device(priv->cec); } +static int tda998x_audio_hw_params(struct device *dev, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + int i, ret; + struct tda998x_audio_params audio = { + .sample_width = params->sample_width, + .sample_rate = params->sample_rate, + .cea = params->cea, + }; + + if (!priv->encoder.crtc) + return -ENODEV; + + memcpy(audio.status, params->iec.status, + min(sizeof(audio.status), sizeof(params->iec.status))); + + switch (daifmt->fmt) { + case HDMI_I2S: + if (daifmt->bit_clk_inv || daifmt->frame_clk_inv || + daifmt->bit_clk_master || daifmt->frame_clk_master) { + dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, + daifmt->bit_clk_inv, daifmt->frame_clk_inv, + daifmt->bit_clk_master, + daifmt->frame_clk_master); + return -EINVAL; + } + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) + if (priv->audio_port[i].format == AFMT_I2S) + audio.config = priv->audio_port[i].config; + audio.format = AFMT_I2S; + break; + case HDMI_SPDIF: + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) + if (priv->audio_port[i].format == AFMT_SPDIF) + audio.config = priv->audio_port[i].config; + audio.format = AFMT_SPDIF; + break; + default: + dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); + return -EINVAL; + } + + if (audio.config == 0) { + dev_err(dev, "%s: No audio configutation found\n", __func__); + return -EINVAL; + } + + ret = tda998x_configure_audio(priv, + &audio, + priv->encoder.crtc->hwmode.clock); + + if (ret == 0) + priv->audio_params = audio; + + return ret; +} + +static void tda998x_audio_shutdown(struct device *dev) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + + reg_write(priv, REG_ENA_AP, 0); + + priv->audio_params.format = AFMT_UNUSED; +} + +int tda998x_audio_digital_mute(struct device *dev, bool enable) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + + tda998x_audio_mute(priv, enable); + + return 0; +} + +static int tda998x_audio_get_eld(struct device *dev, uint8_t *buf, size_t len) +{ + struct tda998x_priv *priv = dev_get_drvdata(dev); + struct drm_mode_config *config = &priv->encoder.dev->mode_config; + struct drm_connector *connector; + int ret = -ENODEV; + + mutex_lock(&config->mutex); + list_for_each_entry(connector, &config->connector_list, head) { + if (&priv->encoder == connector->encoder) { + memcpy(buf, connector->eld, + min(sizeof(connector->eld), len)); + ret = 0; + } + } + mutex_unlock(&config->mutex); + + return ret; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = tda998x_audio_hw_params, + .audio_shutdown = tda998x_audio_shutdown, + .digital_mute = tda998x_audio_digital_mute, + .get_eld = tda998x_audio_get_eld, +}; + +static int tda998x_audio_codec_init(struct tda998x_priv *priv, + struct device *dev) +{ + struct hdmi_codec_pdata codec_data = { + .ops = &audio_codec_ops, + .max_i2s_channels = 2, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(priv->audio_port); i++) { + if (priv->audio_port[i].format == AFMT_I2S && + priv->audio_port[i].config != 0) + codec_data.i2s = 1; + if (priv->audio_port[i].format == AFMT_SPDIF && + priv->audio_port[i].config != 0) + codec_data.spdif = 1; + } + + priv->audio_pdev = platform_device_register_data( + dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(priv->audio_pdev); +} + /* I2C driver functions */ +static int tda998x_get_audio_ports(struct tda998x_priv *priv, + struct device_node *np) +{ + const u32 *port_data; + u32 size; + int i; + + port_data = of_get_property(np, "audio-ports", &size); + if (!port_data) + return 0; + + size /= sizeof(u32); + if (size > 2 * ARRAY_SIZE(priv->audio_port) || size % 2 != 0) { + dev_err(&priv->hdmi->dev, + "Bad number of elements in audio-ports dt-property\n"); + return -EINVAL; + } + + size /= 2; + + for (i = 0; i < size; i++) { + u8 afmt = be32_to_cpup(&port_data[2*i]); + u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); + + if (afmt != AFMT_SPDIF && afmt != AFMT_I2S) { + dev_err(&priv->hdmi->dev, + "Bad audio format %u\n", afmt); + return -EINVAL; + } + + priv->audio_port[i].format = afmt; + priv->audio_port[i].config = ena_ap; + } + + if (priv->audio_port[0].format == priv->audio_port[1].format) { + dev_err(&priv->hdmi->dev, + "There can only be on I2S port and one SPDIF port\n"); + return -EINVAL; + } + return 0; +} + static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) { struct device_node *np = client->dev.of_node; @@ -1320,7 +1507,7 @@ if (!np) return 0; /* non-DT */ - /* get the optional video properties */ + /* get the device tree parameters */ ret = of_property_read_u32(np, "video-ports", &video); if (ret == 0) { priv->vip_cntrl_0 = video >> 16; @@ -1328,8 +1515,14 @@ priv->vip_cntrl_2 = video; } - return 0; + ret = tda998x_get_audio_ports(priv, np); + if (ret) + goto fail; + if (priv->audio_port[0].format != AFMT_UNUSED) + tda998x_audio_codec_init(priv, &client->dev); + + return 0; fail: /* if encoder_init fails, the encoder slave is never registered, * so cleanup here: diff -Naur --no-dereference a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c 2016-05-11 13:31:53.197225234 -0400 @@ -1264,7 +1264,9 @@ if (ret) return ret; +#ifndef CONFIG_PREEMPT_RT_BASE trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); +#endif i915_gem_execbuffer_move_to_active(vmas, params->request); i915_gem_execbuffer_retire_commands(params); diff -Naur --no-dereference a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c --- a/drivers/gpu/drm/i915/i915_gem_shrinker.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c 2016-05-11 13:31:53.197225234 -0400 @@ -39,7 +39,7 @@ if (!mutex_is_locked(mutex)) return false; -#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) +#if (defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)) && !defined(CONFIG_PREEMPT_RT_BASE) return mutex->owner == task; #else /* Since UP may be pre-empted, we cannot assume that we own the lock */ diff -Naur --no-dereference a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c --- a/drivers/gpu/drm/i915/i915_irq.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i915/i915_irq.c 2016-05-11 13:31:53.197225234 -0400 @@ -812,6 +812,7 @@ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ + preempt_disable_rt(); /* Get optional system timestamp before query. */ if (stime) @@ -863,6 +864,7 @@ *etime = ktime_get(); /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ + preempt_enable_rt(); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); diff -Naur --no-dereference a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c --- a/drivers/gpu/drm/i915/intel_display.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i915/intel_display.c 2016-05-11 13:31:53.197225234 -0400 @@ -11376,7 +11376,7 @@ struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_unpin_work *work; - WARN_ON(!in_interrupt()); + WARN_ON_NONRT(!in_interrupt()); if (crtc == NULL) return; diff -Naur --no-dereference a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c --- a/drivers/gpu/drm/i915/intel_sprite.c 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/i915/intel_sprite.c 2016-05-11 13:31:53.197225234 -0400 @@ -38,6 +38,7 @@ #include "intel_drv.h" #include #include "i915_drv.h" +#include static bool format_is_yuv(uint32_t format) @@ -64,6 +65,8 @@ 1000 * adjusted_mode->crtc_htotal); } +static DEFINE_LOCAL_IRQ_LOCK(pipe_update_lock); + /** * intel_pipe_update_start() - start update of a set of display registers * @crtc: the crtc of which the registers are going to be updated @@ -96,7 +99,7 @@ min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); max = vblank_start - 1; - local_irq_disable(); + local_lock_irq(pipe_update_lock); if (min <= 0 || max <= 0) return; @@ -126,11 +129,11 @@ break; } - local_irq_enable(); + local_unlock_irq(pipe_update_lock); timeout = schedule_timeout(timeout); - local_irq_disable(); + local_lock_irq(pipe_update_lock); } finish_wait(wq, &wait); @@ -164,7 +167,7 @@ trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); - local_irq_enable(); + local_unlock_irq(pipe_update_lock); if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { diff -Naur --no-dereference a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile --- a/drivers/gpu/drm/Makefile 2016-05-04 17:50:15.000000000 -0400 +++ b/drivers/gpu/drm/Makefile 2016-05-11 13:31:53.197225234 -0400 @@ -62,7 +62,7 @@ obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ -obj-$(CONFIG_DRM_OMAP) += omapdrm/ +obj-y += omapdrm/ obj-y += tilcdc/ obj-$(CONFIG_DRM_QXL) += qxl/ obj-$(CONFIG_DRM_BOCHS) += bochs/ diff -Naur --no-dereference a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c --- a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c 1969-12-31 19:00:00.000000000 -0500 +++ b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c 2016-05-11 13:31:53.197225234 -0400 @@ -0,0 +1,320 @@ +/* + * Analog TV Connector driver + * + * Copyright (C) 2013 Texas Instruments + * Author: Tomi Valkeinen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include