# SvPortSim v0.1.0 - Table of Contents

> SvPortSim: Elixir interface for driving Verilated SystemVerilog modules through Ports, with each simulation instance managed as a GenServer.

## Pages

- [SvPortSim](readme.md)
- [Changelog](changelog.md)
- [LICENSE](license.md)

## Modules

- [SvPortSim](SvPortSim.md): A `SvPortSim` process owns exactly one simulator transport. The process
implementation lives in `SvPortSim.Server`; this module is the public facade
that keeps the stable user-facing API, validates command options, normalizes
command bodies, and delegates normalized runtime operations to the server.
- [SvPortSim.Compiler](SvPortSim.Compiler.md): Coordinates the high-level build pipeline for Verilated SystemVerilog modules.
- [SvPortSim.PortCodec](SvPortSim.PortCodec.md): Stateless request/response codec for simulator port payloads.
- [SvPortSim.Protocol](SvPortSim.Protocol.md): Runtime wire-format contract for communication between Elixir and the C++ wrapper process.
- [SvPortSim.Protocol.Command](SvPortSim.Protocol.Command.md): Defines the MVP command and response protocol for the C++ wrapper process.
- [SvPortSim.Protocol.DataType](SvPortSim.Protocol.DataType.md): Defines the MVP SystemVerilog data-type subset and runtime value encoding.
- [SvPortSim.Rtl](SvPortSim.Rtl.md): Expands SystemVerilog source strings into RTL source files.
- [SvPortSim.Server](SvPortSim.Server.md): Internal `GenServer` implementation for a single Verilated simulator instance.
- [SvPortSim.SignalSpec](SvPortSim.SignalSpec.md): Defines the metadata schema for SystemVerilog ports exposed to Elixir.
- [SvPortSim.Transport](SvPortSim.Transport.md): Behaviour for simulator transports owned by `SvPortSim`.
- [SvPortSim.Transport.Port](SvPortSim.Transport.Port.md): `SvPortSim.Transport` implementation backed by an Erlang port.
- [SvPortSim.Verilator.Docker](SvPortSim.Verilator.Docker.md): Builds a Verilated executable by running Verilator inside Docker.
- [SvPortSim.Verilator.Wrapper](SvPortSim.Verilator.Wrapper.md): Builds interactive C++ wrapper files for Verilated SystemVerilog top modules.
- [SvPortSim.Verilator.Wrapper.Accessor](SvPortSim.Verilator.Wrapper.Accessor.md): Builds deterministic C++ accessor fragments for generated Verilator wrappers.
- [SvPortSim.Verilator.Wrapper.JsonLiteral](SvPortSim.Verilator.Wrapper.JsonLiteral.md): Encodes deterministic JSON literals and escaped C++ string-literal bodies for
generated Verilator wrapper sources.
- [SvPortSim.Verilator.Wrapper.Template](SvPortSim.Verilator.Wrapper.Template.md): Renders the interactive C++ wrapper template for Verilated top modules.
- [SvPortSim.Verilator.Wrapper.Validator](SvPortSim.Verilator.Wrapper.Validator.md): Validates public inputs for generated Verilator wrapper source construction.

