Modules
A SvPortSim process owns exactly one simulator transport. The process
implementation lives in SvPortSim.Server; this module is the public facade
that keeps the stable user-facing API, validates command options, normalizes
command bodies, and delegates normalized runtime operations to the server.
Coordinates the high-level build pipeline for Verilated SystemVerilog modules.
Stateless request/response codec for simulator port payloads.
Runtime wire-format contract for communication between Elixir and the C++ wrapper process.
Defines the MVP command and response protocol for the C++ wrapper process.
Defines the MVP SystemVerilog data-type subset and runtime value encoding.
Expands SystemVerilog source strings into RTL source files.
Internal GenServer implementation for a single Verilated simulator instance.
Defines the metadata schema for SystemVerilog ports exposed to Elixir.
Behaviour for simulator transports owned by SvPortSim.
SvPortSim.Transport implementation backed by an Erlang port.
Builds a Verilated executable by running Verilator inside Docker.
Builds interactive C++ wrapper files for Verilated SystemVerilog top modules.
Builds deterministic C++ accessor fragments for generated Verilator wrappers.
Encodes deterministic JSON literals and escaped C++ string-literal bodies for generated Verilator wrapper sources.
Renders the interactive C++ wrapper template for Verilated top modules.
Validates public inputs for generated Verilator wrapper source construction.