Builds interactive C++ wrapper files for Verilated SystemVerilog top modules.
The generated executable creates one VerilatedContext and one
Verilator-generated top-module instance before entering the command loop. The
same simulation session is reused for every protocol request until stop,
shutdown, EOF, or a fatal wrapper/protocol failure terminates the process.
source/2 and write/3 accept SvPortSim.SignalSpec metadata and generate
C++ poke_signal and peek_signal dispatch functions for supported direct
top-level Verilated fields. Unsupported or ambiguous shapes are represented by
non-fatal invalid_signal paths instead of guessed field access.
The top_module argument is the SystemVerilog top-module name without
Verilator's V class-name prefix. For example, "Counter" maps to the
Verilator-generated class VCounter and to the wrapper file
Counter_wrapper.cpp.
Accepted top-module names are limited to a safe identifier subset: the name must start with an ASCII letter or underscore, followed by ASCII letters, digits, underscores, or dollar signs.
Summary
Functions
Explicit alias for source/1 that documents interactive wrapper generation.
Explicit alias for source/2 that documents interactive wrapper generation
with generated signal accessors.
Explicit alias for source/3 that documents interactive wrapper generation
with generated signal accessors.
Generates the interactive C++ wrapper source for top_module with no signal
accessors.
Generates the interactive C++ wrapper source for top_module with generated
poke and peek accessors derived from signal_specs.
Generates the interactive C++ wrapper source for top_module with generated
poke and peek accessors derived from signal_specs.
Writes the generated interactive C++ wrapper source for top_module into
dir.
Writes the generated interactive C++ wrapper source for top_module into
dir, including generated signal accessors derived from signal_specs.
Writes the generated interactive C++ wrapper source for top_module into
dir, including generated signal accessors derived from signal_specs.
Functions
Explicit alias for source/1 that documents interactive wrapper generation.
Explicit alias for source/2 that documents interactive wrapper generation
with generated signal accessors.
Explicit alias for source/3 that documents interactive wrapper generation
with generated signal accessors.
Generates the interactive C++ wrapper source for top_module with no signal
accessors.
Examples
iex> {:ok, source} = SvPortSim.Verilator.Wrapper.source("Counter")
iex> source =~ ~s(#include "VCounter.h")
true
iex> source =~ "while (true)"
true
iex> source =~ ~s(op == "tick" || op == "cycle")
true
Generates the interactive C++ wrapper source for top_module with generated
poke and peek accessors derived from signal_specs.
Examples
iex> specs = [SvPortSim.SignalSpec.data("enable", "input", "bit", 1)]
iex> {:ok, source} = SvPortSim.Verilator.Wrapper.source("Counter", specs)
iex> source =~ "AccessorResult poke_signal"
true
iex> source =~ "top->enable ="
true
Generates the interactive C++ wrapper source for top_module with generated
poke and peek accessors derived from signal_specs.
Writes the generated interactive C++ wrapper source for top_module into
dir.
Writes the generated interactive C++ wrapper source for top_module into
dir, including generated signal accessors derived from signal_specs.
Writes the generated interactive C++ wrapper source for top_module into
dir, including generated signal accessors derived from signal_specs.