Esp32.Reset (esp32 v0.2.0)

Sequences that reset an ESP into its serial bootloader.

Development boards wire DTR/RTS to EN/IO0 (classic/2); chips with a built-in USB-JTAG/Serial peripheral need usb_jtag_serial/1; custom hardware can drive the pins directly with gpio/2.

Summary

Types

strategy()

Functions

classic(uart, delay_ms)

DTR/RTS sequence for boards with the usual EN/IO0 transistor circuit.

gpio(reset_pin, boot_pin)

Holds IO0 low while pulsing EN, using Circuits.GPIO pin names.

hard(arg1, uart, opts, usb_otg?)

Resets the chip so it boots normally; USB-OTG ports need a longer pulse.

run(atom, uart, opts, attempt)

Runs strategy; odd attempts use a longer classic delay, as esptool does.

strategy(opts, usb_ids)

Picks the strategy from connect options and the port's USB vendor/product ids.

usb_jtag_serial(uart)

DTR/RTS sequence for the built-in USB-JTAG/Serial peripheral.

Types

strategy()

@type strategy() :: :none | :gpio | :usb_jtag_serial | :classic

Functions

classic(uart, delay_ms)

@spec classic(pid(), non_neg_integer()) :: :ok | {:error, term()}

DTR/RTS sequence for boards with the usual EN/IO0 transistor circuit.

gpio(reset_pin, boot_pin)

@spec gpio(term(), term()) :: :ok | {:error, term()}

Holds IO0 low while pulsing EN, using Circuits.GPIO pin names.

hard(arg1, uart, opts, usb_otg?)

@spec hard(strategy(), pid(), keyword(), boolean()) :: :ok | {:error, term()}

Resets the chip so it boots normally; USB-OTG ports need a longer pulse.

run(atom, uart, opts, attempt)

@spec run(strategy(), pid(), keyword(), non_neg_integer()) :: :ok | {:error, term()}

Runs strategy; odd attempts use a longer classic delay, as esptool does.

strategy(opts, usb_ids)

@spec strategy(
  keyword(),
  {non_neg_integer(), non_neg_integer()} | nil
) :: strategy()

Picks the strategy from connect options and the port's USB vendor/product ids.

usb_jtag_serial(uart)

@spec usb_jtag_serial(pid()) :: :ok | {:error, term()}

DTR/RTS sequence for the built-in USB-JTAG/Serial peripheral.