danm v0.1.4 Danm.Schematic

A schematic is a design entity composed inside Danm.

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Functions

A schematic is an extention of a black box. insts is a map of instances, keyed by instance name. Each instance is either a schematic or a blackbox. wires is a map of wires, keyed by wire name. Each wire is a list of tuples of: {i_name, p_name}, where i_name/p_name is connected instance name and port name in the case of a wire is also connected to a port, the i_name is :self, p_name has to be the same as the wire name in this case for wire as expression the tuple is {:expr, expr} module is the elixir module that it is defined in

add a sub module instance. optional arguments

assign an expression to a wire optional arguments

make some one bit wire that represent the state of a FSM

connect all pins in the design by name if possible Only connect conservatively, so all connected pins are of the same width, with 0 or 1 driver

expose every wire that is either not loaded or driven.

helper macro to maintain flow of the pipe operator

bundle expressions to a wire with given op optional arguments

pick one choice out of n choices based on first none zero condition. the list is a list of {condition, choice} tuple optional arguments

connect pins together as a wire pins are specified as a list of "inst/port". optional arguments

create an input port optional arguments

pick one choice out of 2^n choices based on condition value optional arguments

define an assertion. Assertions are auto-named. optional arguments

return a documentation string to embedded in the generated files

return the driver of wire as a conn tuple {inst, port}

expose the wire as a port. width and direction are automatically figured out

define a finite state machine optional arguments

return driver count, load count and calculated width

Invoke the func with s. This is used to keep the pipe flowing

produce a map of pin -> w_name for the design

This is basically Enum.reduce with first 2 argument switched, to keep the pipe flowing

sink a wire, so it has a fake load and not to be auto-exposed

return a sorted list of instances

return a sorted list of instances after filtering

pick one choice out of n choices based on subject matching condition. the list is a list of {condition, choice} tuple optional arguments

return the width of a wire. First driver rules, failing that, the widest load

produce a map of w_name -> width for the design

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%Danm.Schematic{}

(struct)

A schematic is an extention of a black box. insts is a map of instances, keyed by instance name. Each instance is either a schematic or a blackbox. wires is a map of wires, keyed by wire name. Each wire is a list of tuples of: {i_name, p_name}, where i_name/p_name is connected instance name and port name in the case of a wire is also connected to a port, the i_name is :self, p_name has to be the same as the wire name in this case for wire as expression the tuple is {:expr, expr} module is the elixir module that it is defined in

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add(s, name, options \\ [])

add a sub module instance. optional arguments:

  • :as, instance name. if nil, a name as u_MODULE_NAME is used
  • :parameters, a map of additional parameters to set before elaborate
  • :connections, a map of port to wire name for connection
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assign(s, str, options \\ [])

assign an expression to a wire optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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assign_fsm(s, fsm_name, options)

make some one bit wire that represent the state of a FSM

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auto_connect(s)

connect all pins in the design by name if possible Only connect conservatively, so all connected pins are of the same width, with 0 or 1 driver

expose every wire that is either not loaded or driven.

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bind_to(value, name)

(macro)

helper macro to maintain flow of the pipe operator

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bundle(s, strs, options \\ [])

bundle expressions to a wire with given op optional arguments:

  • :as, name of the wire. required
  • :with, one of (:comma, :and, :or, :xor). default to :comma
  • :flop_by, clock name of the flop
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condition(s, list, options \\ [])

pick one choice out of n choices based on first none zero condition. the list is a list of {condition, choice} tuple optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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connect(s, conns, options \\ [])

connect pins together as a wire pins are specified as a list of "inst/port". optional arguments

  • :as, wire name. if nil, a name as the first port name is used
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create_port(s, name, options \\ [])

create an input port optional arguments

  • :width, the width. default is 1
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decode(s, condition, choices, options \\ [])

pick one choice out of 2^n choices based on condition value optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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die_when(s, str, options \\ [])

define an assertion. Assertions are auto-named. optional arguments:

  • :flop_by, clock name of the flop if existed

return a documentation string to embedded in the generated files

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driver_of_wire(s, conns)

return the driver of wire as a conn tuple {inst, port}

expose the wire as a port. width and direction are automatically figured out

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fsm(s, graph, options \\ [])

define a finite state machine optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop, required
  • :reset_by, an expression of reset condition, optional
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inspect_wire(s, name)

return driver count, load count and calculated width

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invoke(s, func)

Invoke the func with s. This is used to keep the pipe flowing

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pin_to_wire_map(s)

produce a map of pin -> w_name for the design

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roll_in(s, enum, function)

This is basically Enum.reduce with first 2 argument switched, to keep the pipe flowing

sink a wire, so it has a fake load and not to be auto-exposed

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sort_sub_modules(s)

return a sorted list of instances

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sort_sub_modules(s, list)

return a sorted list of instances after filtering

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switch(s, subject, list, options \\ [])

pick one choice out of n choices based on subject matching condition. the list is a list of {condition, choice} tuple optional arguments:

  • :as, name of the wire. required
  • :flop_by, clock name of the flop
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width_of_wire(s, conns)

return the width of a wire. First driver rules, failing that, the widest load

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wire_width_map(s)

produce a map of w_name -> width for the design